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| PIC18F66K80 Family Data Sheet 28/40/44/64-Pin, Enhanced Flash Microcontrollers, with ECANTM and nanoWatt XLP Technology 2011 Microchip Technology Inc. Preliminary DS39977C Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-851-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39977C-page 2 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECANTM and nanoWatt XLP Technology Power-Managed Modes: * * * * * * * * * * * * Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Two-Speed Oscillator Start-up Fail-Safe Clock Monitor (FSCM) Power-Saving Peripheral Module Disable (PMD) Ultra Low-Power Wake-up Fast Wake-up, 1 s, Typical Low-Power WDT, 300 nA, Typical Run mode Currents Down to Very Low 3.8 A, Typical Idle mode Currents Down to Very Low 880 nA, Typical Sleep mode Current Down to Very Low 13 nA, Typical ECAN Bus Module Features (Continued): * 16 Full, 29-Bit Acceptance Filters with Dynamic Association * Three Full, 29-Bit Acceptance Masks * Automatic Remote Frame Handling * Advanced Error Management Features Special Microcontroller Features: * Operating Voltage Range: 1.8V to 5.5V * On-Chip 3.3V Regulator * Operating Speed up to 64 MHz * Up to 64 Kbytes On-Chip Flash Program Memory: - 10,000 erase/write cycle, typical - 20 years minimum retention, typical * 1,024 Bytes of Data EEPROM: - 100,000 Erase/write cycle data EEPROM memory, typical * 3.6 Kbytes of General Purpose Registers (SRAM) * Three Internal Oscillators: LF-INTOSC (31 KHz), MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz) * Self-Programmable under Software Control * Priority Levels for Interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 4,194s * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug via Two Pins * Programmable BOR * Programmable LVD Comparators BORMV/LVD Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ECAN Bus Module Features: * Conforms to CAN 2.0B Active Specification * Three Operating modes: - Legacy mode (full backward compatibility with existing PIC18CXX8/FXX8 CAN modules) - Enhanced mode - FIFO mode or programmable TX/RX buffers * Message Bit Rates up to 1 Mbps * DeviceNetTM Data Byte Filter Support * Six Programmable Receive/Transmit Buffers * Three Dedicated Transmit Buffers with Prioritization * Two Dedicated Receive Buffers TABLE 1: DEVICE COMPARISON Timers 8-Bit/16-Bit 12-Bit A/D Channels EUSART Program Memory 32 Kbytes 32 Kbytes 64 Kbytes 64 Kbytes 32 Kbytes 32 Kbytes 64 Kbytes 64 Kbytes 32 Kbytes 32 Kbytes 64 Kbytes 64 Kbytes Data Data EE Memory Pins (Bytes) (Bytes) 3,648 3,648 3,648 3,648 3,648 3,648 3,648 3,648 3,648 3,648 3,648 3,648 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 28 28 28 28 40/44 40/44 40/44 40/44 64 64 64 64 ECANTM CTMU MSSP CCP/ ECCP DSM No No No No No No No No Yes Yes Yes Yes Device I/O PIC18F25K80 PIC18LF25K80 PIC18F26K80 PIC18LF26K80 PIC18F45K80 PIC18LF45K80 PIC18F46K80 PIC18LF46K80 PIC18F65K80 PIC18LF65K80 PIC18F66K80 PIC18LF66K80 24 24 24 24 35 35 35 35 54 54 54 54 1 1 1 1 1 1 1 1 1 1 1 1 8-ch 8-ch 8-ch 8-ch 11-ch 11-ch 11-ch 11-ch 11-ch 11-ch 11-ch 11-ch 4/1 4/1 4/1 4/1 4/1 4/1 4/1 4/1 4/1 4/1 4/1 4/1 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2011 Microchip Technology Inc. Preliminary DS39977C-page 3 PIC18F66K80 FAMILY Peripheral Highlights: * Five CCP/ECCP modules: - Four Capture/Compare/PWM (CCP) modules - One Enhanced Capture/Compare/PWM (ECCP) module * Five 8/16-Bit Timer/Counter modules: - Timer0: 8/16-bit timer/counter with 8-bit programmable prescaler - Timer1, 3: 16-bit timer/counter - Timer2, 4: 8-bit timer/counter * Two Analog Comparators * Configurable Reference Clock Output * Charge Time Measurement Unit (CTMU): - Capacitance measurement - Time measurement with 1 ns typical resolution - Integrated voltage reference * High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) * Up to Four External Interrupts * One Master Synchronous Serial Port (MSSP) module: - 3/4-wire SPI (supports all four SPI modes) - I2CTM Master and Slave modes * Two Enhanced Addressable USART modules: - LIN/J2602 support - Auto-Baud Detect (ABD) * 12-Bit A/D Converter with up to 11 Channels: - Auto-acquisition and Sleep operation - Differential Input mode of operation * Data Signal Modulator module: - Select modulator and carrier sources from various module outputs * Integrated Voltage Reference DS39977C-page 4 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Diagrams 28-Pin QFN(1) 28 27 26 MCLR/RE3 RA1/AN1 25 24 RA2/VREF-/AN2 RA3/VREF+/AN3 VDDCORE/VCAP RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI VSS OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 23 22 RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0 RB5/T0CKI/T3CKI/CCP5/KBI1 RA0/CVREF/AN0/ULPWU RB7/PGD/T3G/RX2/DT2/KBI3 RB6/PGC/TX2/CK2/KBI2 1 2 3 4 5 6 7 PIC18F2XK80 PIC18LF2XK80 21 20 19 18 17 16 15 14 RB3/CANRX/C2OUT/P1D/CTED2/INT3 RB2/CANTX/C1OUT/P1C/CTED1/INT2 RB1/AN8/C1INB/P1B/CTDIN/INT1 RB0/AN10/C1INA/FLT0/INT0 VDD VSS RC7/CANRX/RX1/DT1/CCP4 RC0/SOSCO/SCLKI RC4/SDA/SDI RC5/SDO 9 10 11 12 13 RC1/SOSCI RC3/REFO/SCL/SCK RC2/T1G/CCP2 8 Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. 2011 Microchip Technology Inc. Preliminary RC6/CANTX/TX1/CK1/CCP3 DS39977C-page 5 PIC18F66K80 FAMILY Pin Diagrams (Continued) 28-Pin SSOP/SPDIP/SOIC MCLR/RE3 RA0/CVREF/AN0/ULPWU RA1/AN1 RA2/VREF-/AN2 RA3/VREF+/AN3 VDDCORE/VCAP RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI VSS OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 RC0/SOSCO/SCLKI RC1/ISOSCI RC2/T1G/CCP2 RC3/REFO/SCL/SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 RB7/PGD/T3G/RX2/DT2/KBI3 RB6/PGC/TX2/CK2/KBI2 RB5/T0CKI/T3CKI/CCP5/KBI1 RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0 RB3/CANRX/C2OUT/P1D/CTED2/INT3 RB2/CANTX/C1OUT/P1C/CTED1/INT2 RB1/AN8/C1INB/P1B/CTDIN/INT1 RB0/AN10/C1INA/FLT0/INT0 VDD VSS RC7/CANRX/RX1/DT1/CCP4 RC6/CANTX/TX1/CK1/CCP3 RC5/SDO RC4/SDA/SDI PIC18F2XK80 PIC18LF2XK80 22 21 20 19 18 17 16 15 40-Pin PDIP MCLR/RE3 RA0/CVREF/AN0/ULPWU RA1/AN1/C1INC RA2/VREF-/AN2/C2INC RA3/VREF+/AN3 VDDCORE/VCAP RA5/AN4/HLVDIN/T1CKI/SS RE0/AN5/RD RE1/AN6/C1OUT/WR RE2/AN7/C2OUT/CS VDD VSS OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 RC0/SOSCO/SCLKI RC1/SOSCI RC2/T1G/CCP2 RC3/REFO/SCL/SCK RD0/C1INA/PSP0 RD1/C1INB/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 RB7/PGD/T3G/KBI3 RB6/PGC/KBI2 RB5/T0CKI/T3CKI/CCP5/KBI1 RB4/AN9/CTPLS/KBI0 RB3/CANRX/CTED2/INT3 RB2/CANTX/CTED1/INT2 RB1/AN8/CTDIN/INT1 RB0/AN10/FLT0/INT0 VDD VSS RD7/RX2/DT2/P1D/PSP7 RD6/TX2/CK2/P1C/PSP6 RD5/P1B/PSP5 RD4/ECCP1/P1A/PSP4 RC7/CANRX/RX1/DT1/CCP4 RC6/CANTX/TX1/CK1/CCP3 RC5/SDO RC4/SDA/SDI RD3/C2INB/CTMUI/PSP3 RD2/C2INA/PSP2 PIC18F4XK80 PIC18LF4XK80 31 30 29 28 27 26 25 24 23 22 21 DS39977C-page 6 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RC6/CANTX/TX1/CK1/CCP3 RD3/C2INB/CTMUI/PSP3 RC3/REFO/SCL/SCK RD2/C2INA/PSP2 RD1/C1INB/PSP1 RD0/C1INA/PSP0 RC2/T1G/CCP2 RC4/SDA/SDI RC1/SOSCI RC5/SDO 42 41 40 38 37 36 35 44 43 39 34 N/C RC7/CANRX/RX1/DT1/CCP4 RD4/ECCP1/P1A/PSP4 RD5/P1B/PSP5 RD6/TX2/CK2/P1C/PSP6 RD7/RX2/DT2/P1D/PSP7 VSS VDD RB0/AN10/FLT0/INT0 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 RB3/CANRX/CTED2/INT3 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 N/C RC0/SOSCO/SCLKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 VSS VDD RE2/AN7/C2OUT/CS RE1/AN6/C1OUT/WR RE0/AN5/RD RA5/AN4/HLVDIN/T1CKI/SS VDDCORE/VCAP PIC18F4XK80 PIC18LF4XK80 14 15 16 18 19 20 21 RA0/CVREF/AN0/ULPWU RA2/VREF-/AN2/C2INC RA1/AN1/C1INC MCLR/RE3 12 13 17 RB5/T0CKI/T3CKI/CCP5/KBI1 RB4/AN9/CTPLS/KBI0 2011 Microchip Technology Inc. Preliminary RB7/PGD/T3G/KBI3 RA3/VREF+/AN3 N/C N/C RB6/PGC/KBI2 22 DS39977C-page 7 PIC18F66K80 FAMILY Pin Diagrams (Continued) 44-Pin QFN(1) RC6/CANTX/TX1/CK1/CCP3 RD3/C2INB/CTMUI/PSP3 RC3/REFO/SCL/SCK RD2/C2INA/PSP2 RD1/C1INB/PSP1 RD0/C1INA/PSP0 RC2/T1G/CCP2 RC4/SDA/SDI RC1/SOSCI RC5/SDO 42 41 40 38 37 36 35 44 43 39 34 N/C RC7/CANRX/RX1/DT1/CCP4 RD4/ECCP1/P1A/PSP4 RD5/P1B/PSP5 RD6/TX2/CK2/P1C/PSP6 RD7/RX2/DT2/P1D/PSP7 VSS VDD RB0/AN10/FLT0/INT0 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 RB3/CANRX/CTED2/INT3 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 N/C RC0/SOSCO/SCLKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 VSS VDD RE2/AN7/C2OUT/CS RE1/AN6/C1OUT/WR RE0/AN5/RD RA5/AN4/HLVDIN/T1CKI/SS VDDCORE/VCAP PIC18F4XK80 PIC18LF4XK80 14 15 16 18 19 20 21 RA0/CVREF/AN0/ULPWU RA2/VREF-/AN2/C2INC RA1/AN1/C1INC MCLR/RE3 12 13 17 RB5/T0CKI/T3CKI/CCP5/KBI1 RB4/AN9/CTPLS/KBI0 Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS39977C-page 8 Preliminary RB7/PGD/T3G/KBI3 RA3/VREF+/AN3 N/C N/C RB6/PGC/KBI2 22 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Diagrams (Continued) 64-Pin QFN(1)/TQFP RD3/C2INB/CTMUI/PSP3 RC3/REFO/SCL/SCK RD2/C2INA/PSP2 RD1/C1INB/PSP1 RD0/C1INA/PSP0 RC2/T1G/CCP2 RE6/RX2/DT2 RE7/TX2/CK2 RC4/SDA/SDI RF6/MDOUT 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 RC0/SOSCO/SCLKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 RF5 RF4/MDCIN2 VSS AVSS VDD AVDD RE2/AN7/C2OUT/CS RE1/AN6/C1OUT/WR RE0/AN5/RD RF3 RF2/MDCIN1 RA5/AN4/HLVDIN/T1CKI/SS VDDCORE/VCAP 64 RC7/CCP4 RD4/ECCP1/P1A/PSP4 RD5/P1B/PSP5 RD6/P1C/PSP6 RD7/P1D/PSP7 RG0/RX1/DT1 RG1/CANTX2 VSS AVDD VDD RG2/T3CKI RG3/TX1/CK1 RB0/AN10/FLT0/INT0 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 RB3/CANRX/CTED2/INT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 63 PIC18F6XK80 PIC18LF6XK80 41 40 39 38 37 36 35 34 33 RF0/MDMIN RG4/T0CKI RA2/VREF-/AN2/C2INC RA1/AN1/C1INC VSS RB5/T0CKI/T3CKI/CCP5/KBI1 RB4/AN9/CTPLS/KBI0 Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. 2011 Microchip Technology Inc. Preliminary RA0/CVREF/AN0/ULPWU RB7/PGD/T3G/KBI3 RA3/VREF+/AN3 RF1 VDD RE4/CANRX RB6/PGC/KBI2 RE5/CANTX MCLR/RE3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RC1/SOSCI RC6/CCP3 RC5/SDO RF7 VDD VSS DS39977C-page 9 PIC18F66K80 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers ......................................................................................... 47 3.0 Oscillator Configurations ............................................................................................................................................................ 53 4.0 Power-Managed Modes ............................................................................................................................................................. 67 5.0 Reset .......................................................................................................................................................................................... 81 6.0 Memory Organization ............................................................................................................................................................... 105 7.0 Flash Program Memory ............................................................................................................................................................ 135 8.0 Data EEPROM Memory ........................................................................................................................................................... 145 9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 151 10.0 Interrupts .................................................................................................................................................................................. 153 11.0 I/O Ports ................................................................................................................................................................................... 177 12.0 Data Signal Modulator .............................................................................................................................................................. 201 13.0 Timer0 Module ......................................................................................................................................................................... 211 14.0 Timer1 Module ......................................................................................................................................................................... 215 15.0 Timer2 Module ......................................................................................................................................................................... 227 16.0 Timer3 Module ......................................................................................................................................................................... 229 17.0 Timer4 Modules........................................................................................................................................................................ 239 18.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 241 19.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 259 20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 271 21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 293 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 339 23.0 12-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 363 24.0 Comparator Module.................................................................................................................................................................. 377 25.0 Comparator Voltage Reference Module ................................................................................................................................... 385 26.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 389 27.0 ECAN Module........................................................................................................................................................................... 395 28.0 Special Features of the CPU .................................................................................................................................................... 461 29.0 Instruction Set Summary .......................................................................................................................................................... 487 30.0 Development Support............................................................................................................................................................... 537 31.0 Electrical Characteristics .......................................................................................................................................................... 541 32.0 Packaging Information.............................................................................................................................................................. 589 Appendix A: Revision History............................................................................................................................................................. 609 Appendix B: Migration to PIC18F66K80 Family................................................................................................................................. 609 Index ................................................................................................................................................................................................. 611 The Microchip Web Site ..................................................................................................................................................................... 625 Customer Change Notification Service .............................................................................................................................................. 625 Customer Support .............................................................................................................................................................................. 625 Reader Response .............................................................................................................................................................................. 626 Product Identification System............................................................................................................................................................. 627 DS39977C-page 10 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2011 Microchip Technology Inc. Preliminary DS39977C-page 11 PIC18F66K80 FAMILY NOTES: DS39977C-page 12 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: * * * * * * PIC18F25K80 PIC18F26K80 PIC18F45K80 PIC18F46K80 PIC18F65K80 PIC18F66K80 * * * * * * PIC18LF25K80 PIC18LF26K80 PIC18LF45K80 PIC18LF46K80 PIC18LF65K80 PIC18LF66K80 * A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes which allows clock speeds of up to 64 MHz. PLL can also be used with the internal oscillator. * An internal oscillator block that provides a 16 MHz clock (2% accuracy) and an INTOSC source (approximately 31 kHz, stable over temperature and VDD) - Operates as HF-INTOSC or MF-INTOSC when block is selected for 16 MHz or 500 kHz - Frees the two oscillator pins for use as additional general purpose I/O The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. This family combines the traditional advantages of all PIC18 microcontrollers - namely, high computational performance and a rich feature set - with an extremely competitive price point. These features make the PIC18F66K80 family a logical choice for many high-performance applications where price is a primary consideration. 1.1 1.1.1 Core Features nanoWatt TECHNOLOGY All of the devices in the PIC18F66K80 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the Internal RC oscillator, power consumption during code execution can be reduced. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further. * On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * nanoWatt XLP: An extra low-power BOR and low-power Watchdog timer 1.1.3 MEMORY OPTIONS The PIC18F66K80 family provides ample room for application code, from 32 Kbytes to 64 Kbytes of code space. The Flash cells for program memory are rated to last up to 10,000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The Flash program memory is readable and writable. During normal operation, the PIC18F66K80 family also provides plenty of room for dynamic application data with up to 3.6 Kbytes of data RAM. 1.1.2 OSCILLATOR OPTIONS AND FEATURES 1.1.4 EXTENDED INSTRUCTION SET All of the devices in the PIC18F66K80 family offer different oscillator options, allowing users a range of choices in developing application hardware. These include: * External Resistor/Capacitor (RC); RA6 available * External Resistor/Capacitor with Clock Out (RCIO) * Three External Clock modes: - External Clock (EC); RA6 available - External Clock with Clock Out (ECIO) - External Crystal (XT, HS, LP) The PIC18F66K80 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as `C'. 2011 Microchip Technology Inc. Preliminary DS39977C-page 13 PIC18F66K80 FAMILY 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between the 28-pin, 40-pin, 44-pin and 64-pin members, or even jumping from smaller to larger memory devices. The PIC18F66K80 family is also largely pin compatible with other PIC18 families, such as the PIC18F4580, PIC18F4680, and PIC18F8680 families of microcontrollers with an ECAN module. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip's PIC18 portfolio, while maintaining a similar feature set. * Charge Time Measurement Unit (CTMU): The CTMU is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Together with other on-chip analog modules, the CTMU can precisely measure time, measure capacitance or relative changes in capacitance, or generate output pulses that are independent of the system clock. * LP Watchdog Timer (WDT): This enhanced version incorporates a 22-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 31.0 "Electrical Characteristics" for time-out periods. 1.3 1.2 Other Special Features Details on Individual Family Members * Communications: The PIC18F66K80 family incorporates a range of serial communication peripherals including two Enhanced USART that support LIN/J2602, one Master SSP module capable of both SPI and I2CTM (Master and Slave) modes of operation and an Enhanced CAN module. * CCP Modules: PIC18F66K80 family devices incorporate four Capture/Compare/PWM (CCP) modules. Up to four different time bases can be used to perform several different operations at once. * ECCP Modules: The PIC18F66K80 family has one Enhanced CCP (ECCP) module to maximize flexibility in control applications: - Up to four different time bases for performing several different operations at once - Up to four PWM outputs - Other beneficial features, such as polarity selection, programmable dead time, auto-shutdown and restart, and Half-Bridge and Full-Bridge Output modes * 12-Bit A/D Converter: The PIC18F66K80 family has a differential ADC. It incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reducing code overhead. Devices in the PIC18F66K80 family are available in 28-pin, 40/44-pin and 64-pin packages. Block diagrams for each package are shown in Figure 1-1, Figure 1-2 and Figure 1-3, respectively. The devices are differentiated from each other in these ways: * Flash Program Memory: - PIC18FX5K80 (PIC18F25K80, PIC18F45K80 and PIC18F45K80) - 32 Kbytes - PIC18FX6K80 (PIC18F26K80, PIC18F46K80 and PIC18F66K80) - 64 Kbytes * I/O Ports: - PIC18F2XK80 (28-pin devices) - Three bidirectional ports - PIC18F4XK80 (40/44-pin devices) - Five bidirectional ports - PIC18F6XK80 (64-pin devices) - Seven bidirectional ports All other features for devices in this family are identical. These are summarized in Table 1-1, Table 1-2 and Table 1-3. The pinouts for all devices are listed in Table 1-4, Table 1-5 and Table 1-6. DS39977C-page 14 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XK80 (28-PIN DEVICES) PIC18F25K80 DC - 64 MHz 32K 16,384 3.6K 31 Ports A, B, C Parallel Slave Port (PSP) Five Two Yes Four One One MSSP and Two Enhanced USARTs (EUSART) Eight Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 28-Pin QFN-S, SOIC, SPDIP and SSOP 64K 32,768 PIC18F26K80 Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Parallel Communications Timers Comparators CTMU Capture/Compare/PWM (CCP) Modules Enhanced CCP (ECCP) Modules Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XK80 (40/44-PIN DEVICES) PIC18F45K80 DC - 64 MHz 32K 16,384 3.6K 32 Ports A, B, C, D, E Parallel Slave Port (PSP) Five Two Yes Four One One MSSP and Two Enhanced USARTs (EUSART) Eleven Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 40-Pin PDIP and 44-Pin QFN and TQFP 64K 32,768 PIC18F46K80 Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Parallel Communications Timers Comparators CTMU Capture/Compare/PWM (CCP) Modules Enhanced CCP (ECCP) Modules Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2011 Microchip Technology Inc. Preliminary DS39977C-page 15 PIC18F66K80 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F6XK80 (64-PIN DEVICES) PIC18F65K80 DC - 64 MHz 32K 16,384 3.6K 32 Ports A, B, C, D, E, F, G Parallel Slave Port (PSP) Five Two Yes Four One Yes Eleven Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 64-Pin QFN and TQFP Yes One MSSP and Two Enhanced USARTs (EUSART) 64K 32,768 PIC18F66K80 Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Parallel Communications Timers Comparators CTMU Capture/Compare/PWM (CCP) Modules Enhanced CCP (ECCP) Modules DSM Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages DS39977C-page 16 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 1-1: PIC18F2XK80 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 8 PCLATU PCLATH Data Bus<8> Data Latch Data Memory (2/4 Kbytes) Address Latch PCU PCH PCL Program Counter 31-Level Stack 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC RC0:RC7(1) PORTB RB0:RB7(1) PORTA RA0:RA3 RA5:RA7(1,2) 8 Address Latch Program Memory Data Latch 8 STKPTR Table Latch ROM Latch Instruction Bus<16> IR Address Decode PORTE RE3(1,3) Instruction Decode and Control State Machine Control Signals 8 PRODH PRODL 3 BITOP 8 8 ALU<8> 8 8 x 8 Multiply 8 W 8 8 OSC2/CLKO OSC1/CLKI Timing Generation INTOSC Oscillator 16 MHz Oscillator Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD 8 VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer 2/4 Timer 3 CTMU ADC 12-Bit Comparator 1/2 CCP2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN Note 1: 2: 3: See Table 1-4 for I/O port pin descriptions. RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 "Oscillator Configurations". RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). 2011 Microchip Technology Inc. Preliminary DS39977C-page 17 PIC18F66K80 FAMILY FIGURE 1-2: PIC18F4XK80 (40/44-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 8 PCLATU PCLATH Data Bus<8> Data Latch Data Memory (2/4 Kbytes) Address Latch PCU PCH PCL Program Counter 31-Level Stack 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC RC0:RC7(1) PORTB RB0:RB7(1) PORTA RA0:RA3 RA5:RA7(1,2) 8 Address Latch Program Memory Data Latch 8 STKPTR Table Latch ROM Latch Instruction Bus<16> IR Address Decode PORTD RD0:RD7(1) 8 Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 ALU<8> 8 8 x 8 Multiply 8 W 8 8 PORTE RE0:RE3(1,3) OSC2/CLKO OSC1/CLKI Timing Generation INTOSC Oscillator 16 MHz Oscillator Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD 8 VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer2/4 Timer3 CTMU ADC 12-Bit Comparator 1/2 CCP 2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN PSP Note 1: 2: 3: See Table 1-5 for I/O port pin descriptions. RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 "Oscillator Configurations". RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). DS39977C-page 18 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 1-3: PIC18F6XK80 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 8 PCLATU PCLATH Data Bus<8> Data Latch Data Memory (2/4 Kbytes) Address Latch PCU PCH PCL Program Counter 31-Level Stack 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC RC0:RC7(1) PORTB RB0:RB7(1) PORTA RA0:RA3 RA5:RA7(1,2) 8 Address Latch Program Memory Data Latch 8 STKPTR Table Latch ROM Latch Instruction Bus<16> IR Address Decode PORTD RD0:RD7(1) 8 Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 ALU<8> 8 8 x 8 Multiply 8 W 8 8 PORTE RE0:RE7(1,3) OSC2/CLKO OSC1/CLKI Timing Generation INTOSC Oscillator 16 MHz Oscillator Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD 8 PORTF RF0:RF7(1) PORTG RG0:RG4(1) VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer2/4 Timer3 CTMU ADC 12-Bit Comparator 1/2 CCP2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN PSP DSM Note 1: 2: 3: See Table 1-6 for I/O port pin descriptions. RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 "Oscillator Configurations". RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). 2011 Microchip Technology Inc. Preliminary DS39977C-page 19 PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS Pin Number Pin Name SSOP/ Pin Buffer QFN SPDIP/ Type Type SOIC 26 1 I I 6 9 I I ST Oscillator crystal input. CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) ST/ General purpose I/O pin. CMOS -- -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. ST ST Master Clear (input) or programming voltage (input).This pin is an active-low Reset to the device. General purpose, input only pin. Description MCLR/RE3 MCLR RE3 OSC1/CLKIN/RA7 OSC1 CLKIN RA7 OSC2/CLKOUT/RA6 OSC2 CLKOUT 7 10 I/O O O RA6 Legend: CMOS ST I P I/O ST/ General purpose I/O pin. CMOS I2CTM = I2C/SMBus input buffer Analog = Analog input O = Output = CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Input = Power DS39977C-page 20 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SSOP/ Pin Buffer QFN SPDIP/ Type Type SOIC 27 2 I/O O I I 28 3 I/O I 1 4 I/O I I 2 5 I/O I I 4 7 I/O I I I I I ST/ Digital I/O. CMOS Analog Analog Input 4. Analog Comparator 2 Input B. Analog High/Low-Voltage Detect input. ST ST Timer1 clock input. SPI slave select input. CTMU pulse generator charger for the C2INB. = CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Input = Power I2CTM = I2C/SMBus input buffer Analog = Analog input O = Output ST/ Digital I/O. CMOS Analog A/D reference voltage (high) input. Analog Analog Input 3. ST/ Digital I/O. CMOS Analog A/D reference voltage (low) input. Analog Analog Input 2. ST/ Digital I/O. CMOS Analog Analog Input 1. ST/ General purpose I/O pin. CMOS Analog Comparator reference voltage output. Analog Analog Input 0. Analog Ultra low-power wake-up input. Description PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ULPWU RA0 CVREF AN0 ULPWU RA1/AN1 RA1 AN1 RA2/VREF-/AN2 RA2 VREFAN2 RA3/VREF+/AN3 RA3 VREF+ AN3 RA5/AN4/C2INB/HLVDIN/ T1CKI/SS/CTMUI RA5 AN4 C2INB HLVDIN T1CKI SS CTMUI Legend: CMOS ST I P 2011 Microchip Technology Inc. Preliminary DS39977C-page 21 PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SSOP/ Pin Buffer QFN SPDIP/ Type Type SOIC 18 21 I/O I I I I 19 22 I/O I I O I I 20 23 I/O O O O I I 21 24 I/O I O O I I ST/ Digital I/O. CMOS ST CAN bus RX. CMOS Comparator 2 output. CMOS Enhanced PWM1 Output D. ST ST CTMU Edge 2 input. External Interrupt 3. I2CTM = I2C/SMBus input buffer Analog = Analog input O = Output ST/ Digital I/O. CMOS CMOS CAN bus TX. CMOS Comparator 1 output. CMOS Enhanced PWM1 Output C. ST ST CTMU Edge 1 input. External Interrupt 2. ST/ Digital I/O. CMOS Analog Analog Input 8. Analog Comparator 1 Input B. CMOS Enhanced PWM1 Output B. ST ST CTMU pulse delay input. External Interrupt 1. ST/ Digital I/O. CMOS Analog Analog Input 10. Analog Comparator 1 Input A. ST ST Enhanced PWM Fault input for ECCP1. External Interrupt 0. Description PORTB is a bidirectional I/O port. RB0/AN10/C1INA/FLT0/ INT0 RB0 AN10 C1INA FLT0 INT0 RB1/AN8/C1INB/P1B/ CTDIN/INT1 RB1 AN8 C1INB P1B CTDIN INT1 RB2/CANTX/C1OUT/ P1C/CTED1/INT2 RB2 CANTX C1OUT P1C CTED1 INT2 RB3/CANRX/C2OUT/ P1D/CTED2/INT3 RB3 CANRX C2OUT P1D CTED2 INT3 Legend: CMOS ST I P = CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Input = Power DS39977C-page 22 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SSOP/ Pin Buffer QFN SPDIP/ Type Type SOIC 22 25 I/O I I I/O O O I 23 26 I/O I I I/O I 24 27 I/O I O I/O I 25 28 I/O I/O I I I/O I ST/ Digital I/O. CMOS ST ST ST ST ST In-Circuit Debugger and ICSP programming data pin. Timer3 external clock gate input. EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). Interrupt-on-change pin. I2CTM = I2C/SMBus input buffer Analog = Analog input O = Output ST/ Digital I/O. CMOS ST In-Circuit Debugger and ICSPTM programming clock input pin. EUSART synchronous clock (see related RX2/DT2). Interrupt-on-change pin. ST/ Digital I/O. CMOS ST ST Timer0 external clock input. Timer3 external clock input. ST/ Digital I/O. CMOS Analog Analog Input 9. Analog Comparator 2 Input A. ST ST ST Capture 1 input/Compare 1 output/PWM1 output. CTMU pulse generator output. Interrupt-on-change pin. CMOS Enhanced PWM1 Output A. Description RB4/AN9/C2INA/ECCP1/ P1A/CTPLS/KBI0 RB4 AN9 C2INA ECCP1 P1A CTPLS KBI0 RB5/T0CKI/T3CKI/CCP5/ KBI1 RB5 T0CKI T3CKI CCP5 KBI1 RB6/PGC/TX2/CK2/KBI2 RB6 PGC TX2 CK2 KBI2 RB7/PGD/T3G/RX2/DT2/ KBI3 RB7 PGD T3G RX2 DT2 KBI3 Legend: CMOS ST I P ST/ Capture 5 input/Compare 5 output/PWM5 output. CMOS ST Interrupt-on-change pin. CMOS EUSART asynchronous transmit. ST ST = CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Input = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 23 PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SSOP/ Pin Buffer QFN SPDIP/ Type Type SOIC 8 11 I/O I I 9 12 I/O I 10 13 I/O I I/O 11 14 I/O O I/O I/O 12 15 I/O I/O I 13 16 I/O O 14 17 I/O O O I/O I/O ST/ Digital I/O. CMOS CMOS CAN bus TX. CMOS EUSART asynchronous transmit. ST EUSART synchronous clock. (See related RX1/DT1.) ST/ Capture 3 input/Compare 3 output/PWM3 output. CMOS I2CTM = I2C/SMBus input buffer Analog = Analog input O = Output ST/ Digital I/O. CMOS CMOS SPI data out. ST/ Digital I/O. CMOS I2C ST I2C data input/output. SPI data in. ST/ Digital I/O. CMOS -- I2C ST Reference clock out. Synchronous serial clock input/output for I2C mode. Synchronous serial clock input/output for SPI mode. ST/ Digital I/O. CMOS ST ST Timer1 external clock gate input. Capture 2 input/Compare 2 output/PWM2 output. ST/ Digital I/O. CMOS CMOS SOSC oscillator input. ST/ Digital I/O. CMOS ST ST Timer1 oscillator output. Digital SOSC input. Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI RC0 SOSCO SCLKI RC1/SOSCI RC1 SOSCI RC2/T1G/CCP2 RC2 T1G CCP2 RC3/REFO/SCL/SCK RC3 REFO SCL SCK RC4/SDA/SDI RC4 SDA SDI RC5/SDO RC5 SDO RC6/CANTX/TX1/CK1/ CCP3 RC6 CANTX TX1 CK1 CCP3 Legend: CMOS ST I P = CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Input = Power DS39977C-page 24 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SSOP/ Pin Buffer QFN SPDIP/ Type Type SOIC 15 18 I/O I I I/O I/O 5 16 3 8 19 Ground reference for logic and I/O pins. 6 P External filter capacitor connection. External filter capacitor connection 17 20 P Positive supply for logic and I/O pins. = CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Input = Power I2CTM = I2C/SMBus input buffer Analog = Analog input O = Output P Ground reference for logic and I/O pins. ST/ Digital I/O. CMOS ST ST ST CAN bus RX. EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). Description RC7/CANRX/RX1/DT1/ CCP4 RC7 CANRX RX1 DT1 CCP4 VSS VSS VSS VSS VDDCORE/VCAP VDDCORE VCAP VDD VDD Legend: CMOS ST I P ST Capture 4 input/Compare 4 output/PWM4 output. CMOS 2011 Microchip Technology Inc. Preliminary DS39977C-page 25 PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP MCLR/RE3 MCLR RE3 OSC1/CLKIN/RA7 OSC1 CLKIN 13 30 I I ST Oscillator crystal input. CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins. ST/ General purpose I/O pin. CMOS -- -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. 1 Pin Buffer QFN/ Type Type TQFP 18 I I ST ST Master Clear (input) or programming voltage (input).This pin is an active-low Reset to the device. General purpose, input only pin. Description RA7 OSC2/CLKOUT/RA6 OSC2 CLKOUT 14 31 I/O O O RA6 I/O ST/ General purpose I/O pin. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39977C-page 26 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP 19 I/O O I I 3 20 I/O I I 4 21 I/O I I I 5 22 I/O I I 7 24 I/O I I I I 2CTM = I2C/SMBus Description PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ULPWU RA0 CVREF AN0 ULPWU RA1/AN1/C1INC RA1 AN1 C1INC RA2/VREF-/AN2/C2INC RA2 VREFAN2 C2INC RA3/VREF+/AN3 RA3 VREF+ AN3 RA5/AN4/HLVDIN/T1CKI/ SS RA5 AN4 HLVDIN T1CKI SS Legend: I ST I P 2 ST/ General purpose I/O pin. CMOS Analog Comparator reference voltage output. Analog Analog Input 0. Analog Ultra low-power wake-up input. ST/ Digital I/O. CMOS Analog Analog Input 1. Analog Comparator 1 Input C. ST/ Digital I/O. CMOS Analog A/D reference voltage (low) input. Analog Analog Input 2. Analog Comparator 2 Input C. ST/ Digital I/O. CMOS Analog A/D reference voltage (high) input. Analog Analog Input 3. ST/ Digital I/O. CMOS Analog Analog Input 4. Analog High/Low-Voltage Detect input. ST ST Timer1 clock input. SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output input buffer = Schmitt Trigger input with CMOS levels = Input = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 27 PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP 8 I/O I I I 34 9 I/O I I I 35 10 I/O O I I 36 11 I/O I I I 37 14 I/O I O I 38 15 I/O I I I/O I 2 2 Description PORTB is a bidirectional I/O port. RB0/AN10/FLT0/INT0 RB0 AN10 FLT0 INT0 RB1/AN8/CTDIN/INT1 RB1 AN8 CTDIN INT1 RB2/CANTX/CTED1/ INT2 RB2 CANTX CTED1 INT2 RB3/CANRX/CTED2/ INT3 RB3 CANRX CTED2 INT3 RB4/AN9/CTPLS/KBI0 RB4 AN9 CTPLS KBI0 RB5/T0CKI/T3CKI/CCP5/ KBI1 RB5 T0CKI T3CKI CCP5 KBI1 33 ST/ Digital I/O. CMOS Analog Analog Input 10. ST ST Enhanced PWM Fault input for ECCP1. External Interrupt 0. ST/ Digital I/O. CMOS Analog Analog Input 8. ST ST CTMU pulse delay input. External Interrupt 1. ST/ Digital I/O. CMOS CMOS CAN bus TX. ST ST CTMU Edge 1 input. External Interrupt 2. ST/ Digital I/O. CMOS ST ST ST CAN bus RX. CTMU Edge 2 input. External Interrupt 3. ST/ Digital I/O. CMOS Analog Analog Input 9. ST ST CTMU pulse generator output. Interrupt-on-change pin. ST/ Digital I/O. CMOS ST ST ST ST Timer0 external clock input. Timer3 external clock input. Capture 5 input/Compare 5 output/PWM5 output. Interrupt-on-change pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output Legend: I CTM = I C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39977C-page 28 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP RB6/PGC/KBI2 RB6 PGC KBI2 RB7/PGD/T3G/KBI3 RB7 PGD T3G KBI3 Legend: I ST I P 2CTM = I2C/SMBus Pin Buffer QFN/ Type Type TQFP 16 I/O I I ST/ Digital I/O. CMOS ST ST Description 39 In-Circuit Debugger and ICSPTM programming clock input pin. Interrupt-on-change pin. 40 17 I/O I/O I I ST/ Digital I/O. CMOS ST ST ST In-Circuit Debugger and ICSPTM programming data pin. Timer3 external clock gate input. Interrupt-on-change pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output input buffer = Schmitt Trigger input with CMOS levels = Input = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 29 PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP 32 I/O I I 16 35 I/O I 17 36 I/O I I/O 18 37 I/O O I/O I/O 23 42 I/O I/O I 24 43 I/O O 25 44 I/O O O I/O I/O 2CTM = I2C/SMBus Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI RC0 SOSCO SCLKI RC1/SOSCI RC1 SOSCI RC2/T1G/CCP2 RC2 T1G CCP2 RC3/REFO/SCL/SCK RC3 REFO SCL SCK RC4/SDA/SDI RC4 SDA SDI RC5/SDO RC5 SDO RC6/CANTX/TX1/CK1/ CCP3 RC6 CANTX TX1 CK1 CCP3 Legend: I ST I P 15 ST/ Digital I/O. CMOS ST ST SOSC oscillator output. Digital SOSC input. ST/ Digital I/O. CMOS CMOS SOSC oscillator input. ST/ Digital I/O. CMOS ST Timer1 external clock gate input. ST/ Capture 2 input/Compare 2 output/PWM2 output. CMOS ST/ Digital I/O. CMOS CMOS Reference clock out. I2C ST Synchronous serial clock input/output for I2C mode. Synchronous serial clock input/output for SPI mode. ST/ Digital I/O. CMOS I2C ST I2C data input/output. SPI data in. ST/ Digital I/O. CMOS CMOS SPI data out. ST/ Digital I/O. CMOS CMOS CAN bus TX. CMOS EUSART synchronous transmit. ST ST EUSART synchronous clock (see related RX2/DT2). Capture 3 input/Compare 3 output/PWM3 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output input buffer = Schmitt Trigger input with CMOS levels = Input = Power DS39977C-page 30 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP RC7/CANRX/RX1/DT1/ CCP4 RC7 CANRX RX1 DT1 CCP4 2 2 Pin Buffer QFN/ Type Type TQFP 1 I/O I I I/O I/O ST/ Digital I/O. CMOS ST ST ST ST CAN bus RX. Description 26 EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). Capture 4 input/Compare 4 output/PWM4 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output Legend: I CTM = I C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 31 PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP 38 I/O I I/O 20 39 I/O I I/O 21 40 I/O I I/O 22 41 I/O I I/O 27 2 I/O I/O O I/O 28 3 I/O O I/O ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output B. ST/ Parallel Slave Port data. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS ST Capture 1 input/Compare 1 output/PWM1 output. CMOS Enhanced PWM1 Output A. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 2 Input B. CTMU pulse generator charger for the C2INB. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 2 Input A. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 1 Input B. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 1 Input A. ST/ Parallel Slave Port data. CMOS Description PORTD is a bidirectional I/O port. RD0/C1INA/PSP0 RD0 C1INA PSP0 RD1/C1INB/PSP1 RD1 C1INB PSP1 RD2/C2INA/PSP2 RD2 C2INA PSP2 RD3/C2INB/CTMUI/ PSP3 RD3 C2INB CTMUI PSP3 RD4/ECCP1/P1A/PSP4 RD4 ECCP1 P1A PSP4 RD5/P1B/PSP5 RD5 P1B PSP5 19 Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39977C-page 32 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP RD6/TX2/CK2/P1C/PSP6 RD6 TX2 CK2 P1C PSP6 RD7/RX2/DT2/P1D/PSP7 RD7 RX2 DT2 P1D PSP7 RE0/AN5/RD RE0 AN5 RD RE1/AN6/C1OUT/WR RE1 AN6 C1OUT WR RE2/AN7/C2OUT/CS RE2 AN7 C2OUT CS RE3 Legend: I ST I P 2CTM = I2C/SMBus Pin Buffer QFN/ Type Type TQFP 4 I/O I I/O O I/O ST/ Digital I/O. CMOS ST ST Description 29 EUSART asynchronous transmit. EUSART synchronous clock (see related RX2/DT2). CMOS Enhanced PWM1 Output C. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS ST ST EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). 30 5 I/O I I/O O I/O CMOS Enhanced PWM1 Output D. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Analog Input 5. ST Parallel Slave Port read strobe. 8 25 I/O I I 9 26 I/O I O I ST/ Digital I/O. CMOS Analog Analog Input 6. CMOS Comparator 1 output. ST Parallel Slave Port write strobe. 10 27 I/O I O I ST/ Digital I/O. CMOS Analog Analog Input 7. CMOS Comparator 2 output. ST Parallel Slave Port chip select. See the MCLR/RE3 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output input buffer = Schmitt Trigger input with CMOS levels = Input = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 33 PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP VSS VSS VSS VSS VDDCORE/VCAP VDDCORE VCAP VDD VDD VDD VDD Legend: I ST I P 2CTM = I2C/SMBus Pin Buffer QFN/ Type Type TQFP 29 6 P Description 12 31 6 Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. 23 P External filter capacitor connection External filter capacitor connection 11 32 28 7 P Positive supply for logic and I/O pins. P Positive supply for logic and I/O pins. input buffer = Schmitt Trigger input with CMOS levels = Input = Power CMOS = CMOS compatible input or output Analog = Analog input O = Output DS39977C-page 34 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS Pin Num 28 I I 46 I I I/O 47 O O I/O -- -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. ST Oscillator crystal input. CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) ST/ General purpose I/O pin. CMOS ST ST Master Clear (input) or programming voltage (input).This pin is an active-low Reset to the device. General purpose, input only pin. Pin Type Buffer Type Description Pin Name MCLR/RE3 MCLR RE3 OSC1/CLKIN/RA7 OSC1 CLKIN RA7 OSC2/CLKOUT/RA6 OSC2 CLKOUT RA6 ST/ General purpose I/O pin. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 35 PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 29 I/O O I I 30 I/O I I 31 I/O I I I 32 I/O I I 34 I/O I I I I ST/ Digital I/O. CMOS Analog Analog Input 4. Analog High/Low-Voltage Detect input. ST ST Timer1 clock input. SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS Analog A/D reference voltage (high) input. Analog Analog Input 3. ST/ Digital I/O. CMOS Analog A/D reference voltage (low) input. Analog Analog Input 2. Analog Comparator 2 Input C. ST/ Digital I/O. CMOS Analog Analog Input 1. Analog Comparator 1 Input C. ST/ General purpose I/O pin. CMOS Analog Comparator reference voltage output. Analog Analog Input 0. Analog Ultra low-power wake-up input. Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ ULPWU RA0 CVREF AN0 ULPWU RA1/AN1/C1INC RA1 AN1 C1INC RA2/VREF-/AN2/C2INC RA2 VREFAN2 C2INC RA3/VREF+/AN3 RA3 VREF+ AN3 RA5/AN4/HLVDIN/ T1CKI/SS RA5 AN4 HLVDIN T1CKI SS Pin Name Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39977C-page 36 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 13 I/O I I I 14 I/O I I I 15 I/O O I I 16 I/O I I I 20 I/O I O I 21 I/O I I I/O I ST/ Digital I/O. CMOS ST ST Timer0 external clock input. Timer3 external clock input. ST/ Digital I/O. CMOS Analog Analog Input 9. ST ST CTMU pulse generator output. Interrupt-on-change pin. ST/ Digital I/O. CMOS ST ST ST CAN bus RX. CTMU Edge 2 input. External Interrupt 3. ST/ Digital I/O. CMOS CMOS CAN bus TX. ST ST CTMU Edge 1 input. External Interrupt 2. ST/ Digital I/O. CMOS Analog Analog Input 8. ST ST CTMU pulse delay input. External Interrupt 1. ST/ Digital I/O. CMOS Analog Analog Input 10. ST ST Enhanced PWM Fault input for ECCP1. External Interrupt 0. Pin Type Buffer Type Description PORTB is a bidirectional I/O port. RB0/AN10/FLT0/INT0 RB0 AN10 FLT0 INT0 RB1/AN8/CTDIN/INT1 RB1 AN8 CTDIN INT1 RB2/CANTX/CTED1/ INT2 RB2 CANTX CTED1 INT2 RB3/CANRX/CTED2/ INT3 RB3 CANRX CTED2 INT3 RB4/AN9/CTPLS/KBI0 RB4 AN9 CTPLS KBI0 RB5/T0CKI/T3CKI/CCP5/ KBI1 RB5 T0CKI T3CKI CCP5 KBI1 Pin Name ST/ Capture 5 input/Compare 5 output/PWM5 output. CMOS ST Interrupt-on-change pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 37 PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 22 I/O I I 23 I/O I/O I I 2CTM = Pin Name RB6/PGC/KBI2 RB6 PGC KBI2 RB7/PGD/T3G/KBI3 RB7 PGD T3G KBI3 Legend: I ST I P Pin Type Buffer Type ST/ Digital I/O. CMOS ST ST Description In-Circuit Debugger and ICSPTM programming clock input pin. Interrupt-on-change pin. ST/ Digital I/O. CMOS ST ST ST In-Circuit Debugger and ICSPTM programming data pin. Timer3 external clock gate input. Interrupt-on-change pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output input buffer = Schmitt Trigger input with CMOS levels = Input = Power I2C/SMBus DS39977C-page 38 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 48 I/O I I 49 I/O I 50 I/O I I/O 51 I/O O I/O I/O 62 I/O I/O I 63 I/O O 64 I/O I/O 1 I/O I/O ST/ Digital I/O. CMOS ST/ Capture 4 input/Compare 4 output/PWM4 output. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS ST/ Capture 3 input/Compare 3 output/PWM3 output. CMOS ST/ Digital I/O. CMOS CMOS SPI data out. ST/ Digital I/O. CMOS I2C ST I2C data input/output. SPI data in. ST/ Digital I/O. CMOS CMOS Reference clock out. I2C ST Synchronous serial clock input/output for I2C mode. Synchronous serial clock input/output for SPI mode. ST/ Digital I/O. CMOS ST ST Timer1 external clock gate input. Capture 2 input/Compare 2 output/PWM2 output. ST/ Digital I/O. CMOS CMOS SOSC oscillator input. ST/ Digital I/O. CMOS ST ST Timer1 oscillator output. Digital SOSC input. Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI RC0 SOSCO SCLKI RC1/SOSCI RC1 SOSCI RC2/T1G/CCP2 RC2 T1G CCP2 RC3/REFO/SCL/SCK RC3 REFO SCL SCK RC4/SDA/SDI RC4 SDA SDI RC5/SDO RC5 SDO RC6/CCP3 RC6 CCP3 RC7/CCP4 RC7 CCP4 Pin Name Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 39 PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 54 I/O I I/O 55 I/O I I/O 58 I/O I I/O 59 I/O I O I/O 2 I/O I/O O I/O 3 I/O O I/O ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output B. ST/ Parallel Slave Port data. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS ST Capture 1 input/Compare 1 output/PWM1 output. CMOS Enhanced PWM1 Output A. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 2 Input B. CMOS CTMU pulse generator charger for the C2INB. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 2 Input A. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 1 Input B. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS Analog Comparator 1 Input A. ST/ Parallel Slave Port data. CMOS Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/C1INA/PSP0 RD0 C1INA PSP0 RD1/C1INB/PSP1 RD1 C1INB PSP1 RD2/C2INA/PSP2 RD2 C2INA PSP2 RD3/C2INB/CTMUI/ PSP3 RD3 C2INB CTMUI PSP3 RD4/ECCP1/P1A/PSP4 RD4 ECCP1 P1A PSP4 RD5/P1B/PSP5 RD5 P1B PSP5 Pin Name Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39977C-page 40 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 4 I/O O I/O 5 I/O O I/O ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output D. ST/ Parallel Slave Port data. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output C. ST/ Parallel Slave Port data. CMOS Pin Type Buffer Type Description Pin Name RD6/P1C/PSP6 RD6 P1C PSP6 RD7/P1D/PSP7 RD7 P1D PSP7 Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 41 PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 37 I/O I I 38 I/O I O I 39 I/O I O I 27 I/O I 24 I/O O 60 I/O I I/O 61 I/O O I/O 2CTM = Pin Name Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/AN5/RD RE0 AN5 RD RE1/AN6/C1OUT/WR RE1 AN6 C1OUT WR RE2/AN7/C2OUT/CS RE2 AN7 C2OUT CS RE3 RE4/CANRX RE4 CANRX RE5/CANTX RE5 CANTX RE6/RX2/DT2 RE6 RX2 DT2 RE7/TX2/CK2 RE7 TX2 CK2 Legend: I ST I P ST/ Digital I/O. CMOS Analog Analog Input 5. ST Parallel Slave Port read strobe. ST/ Digital I/O. CMOS Analog Analog Input 6. CMOS Comparator 1 output. ST Parallel Slave Port write strobe. ST/ Digital I/O. CMOS Analog Analog Input 7. CMOS Comparator 2 output. ST Parallel Slave Port chip select. See the MCLR/RE3 pin. ST/ Digital I/O. CMOS ST CAN bus RX. ST/ Digital I/O. CMOS CMOS CAN bus TX. ST/ Digital I/O. CMOS ST ST EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). ST/ Digital I/O. CMOS CMOS EUSART asynchronous transmit. ST EUSART synchronous clock (see related RX2/DT2). CMOS = CMOS compatible input or output Analog = Analog input O = Output I2C/SMBus input buffer = Schmitt Trigger input with CMOS levels = Input = Power DS39977C-page 42 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 17 I/O I 19 I/O 35 I/O I 36 I/O 44 I/O I 45 I/O 52 I/O O 53 I/O ST/ Digital I/O. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS CMOS Modulator output. ST/ Digital I/O. CMOS ST/ Digital I/O. CMOS ST Modulator Carrier Input 2. ST/ Digital I/O. CMOS ST/ Digital I/O. CMOS ST Modulator Carrier Input 1. ST/ Digital I/O. CMOS ST/ Digital I/O. CMOS CMOS Modulator source input. Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/MDMIN RF0 MDMIN RF1 RF1 RF2/MDCIN1 RF2 MDCIN1 RF3 RF3 RF4/MDCIN2 RF4 MDCIN2 RF5 RF5 RF6/MDOUT RF6 MDOUT RF7 RF7 Pin Name Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2011 Microchip Technology Inc. Preliminary DS39977C-page 43 PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 6 I/O I I/O 7 I/O O 11 I/O I 12 I/O O I/O 18 I/O I ST/ Digital I/O. CMOS ST Timer0 external clock input. CMOS = CMOS compatible input or output Analog = Analog input O = Output ST/ Digital I/O. CMOS CMOS EUSART asynchronous transmit. ST EUSART synchronous clock (see related RX2/DT2). ST/ Digital I/O. CMOS ST Timer3 clock input. ST/ Digital I/O. CMOS CMOS CAN bus complimentary transmit output or CAN bus time clock. ST/ Digital I/O. CMOS ST ST EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/RX1/DT1 RG0 RX1 DT1 RG1/CANTX2 RG1 CANTX2 RG2/T3CKI RG2 T3CKI RG3/TX1/CK1 RG3 TX1 CK1 RG4/T0CKI RG4 T0CKI Pin Name Legend: I2CTM = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39977C-page 44 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num 8 26 42 43 56 9 10 25 33 Pin Type Buffer Type P Ground reference for logic and I/O pins. P Ground reference for logic and I/O pins. P Ground reference for analog modules. P Ground reference for logic and I/O pins. P Ground reference for logic and I/O pins. P Positive supply for analog modules. P Positive supply for logic and I/O pins. P Positive supply for logic and I/O pins. P External filter capacitor connection. External filter capacitor connection. 40 41 57 2CTM = Pin Name VSS VSS VSS VSS AVSS AVSS VSS VSS VSS VSS AVDD AVDD VDD VDD VDD VDD VDDCORE/VCAP VDDCORE VCAP AVDD AVDD VDD VDD VDD VDD Legend: I ST I P Description P Positive supply for analog modules. P Positive supply for logic and I/O pins. P Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output Analog = Analog input O = Output input buffer = Schmitt Trigger input with CMOS levels = Input = Power I2C/SMBus 2011 Microchip Technology Inc. Preliminary DS39977C-page 45 PIC18F66K80 FAMILY NOTES: DS39977C-page 46 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FXXKXX MICROCONTROLLERS Basic Connection Requirements FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(1) 2.1 VDD VDD MCLR VCAP/VDDCORE Getting started with the PIC18F66K80 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") These pins must also be connected if they are being used in the end application: * PGC/PGD pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins are used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. R1 R2 C1 PIC18FXXKXX VSS VDD VSS C7(1) C6(1) AVDD VDD VSS AVSS VDD VSS C3(1) C5(1) C4(1) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic R1: 10 k R2: 100 to 470 Note 1: The example shown is for a PIC18F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The minimum mandatory connections are shown in Figure 2-1. 2011 Microchip Technology Inc. Preliminary DS39977C-page 47 PIC18F66K80 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS 2.3 Master Clear (MCLR) Pin The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 EXAMPLE OF MCLR PIN CONNECTIONS R2 JP C1 MCLR PIC18FXXKXX 2.2.2 TANK CAPACITORS Note 1: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS39977C-page 48 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 2.4 Voltage Regulator Pins (VCAP/VDDCORE) FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP On the PIC18F66K80 family devices, the regulator is enabled and a low-ESR (< 5) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 F connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specifications can be used. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 31.0 "Electrical Characteristics" for additional information. When the regulator is disabled, a 0.1F capacitor should be connected from the VCAP/VDDCORE pin to ground. This capacitor's characteristics must be similar to those of the "decoupling" capacitors explained in Section 2.2.1. For details on the VDD requirement, when the regulator is disabled, see Parameter D001 in Section 31.0 "Electrical Characteristics". Some PIC18FXXKXX families or some devices within a family do not provide the option of enabling or disabling the on-chip voltage regulator: * The PIC18LFXXKXX devices permanently disable the voltage regulator. These devices require a 0.1F capacitor on the VCAP/VDDCORE pin. The VDD level of these devices must comply with the "voltage regulator disabled" specification for Parameter D001, in Section 31.0 "Electrical Characteristics". * PIC18FXXKXX devices permanently enable the voltage regulator. These devices require a 10 F capacitor on the VCAP/VDDCORE pin. For details on all members of the PIC18F66K80 family, see Section 28.3 "On-Chip Voltage Regulator". 10 1 ESR () 0.1 0.01 0.001 0.01 0.1 1 10 100 Frequency (MHz) 1000 10,000 Note: Typical data measurement at 25C, 0V DC bias. 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes, and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGCx/PGDx pins) programmed into the device matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 30.0 "Development Support". 2011 Microchip Technology Inc. Preliminary DS39977C-page 49 PIC18F66K80 FAMILY TABLE 2-1 Make TDK TDK Panasonic Panasonic Murata Murata SUITABLE CAPACITOR EQUIVALENTS Part # C3216X7R1C106K C3216X5R1C106K ECJ-3YX1C106K ECJ-4YB1C106K GRM32DR71C106KA01L GRM31CR61C106KC31L Nominal Capacitance 10 F 10 F 10 F 10 F 10 F 10 F Base Tolerance 10% 10% 10% 10% 10% 10% Rated Voltage 16V 16V 16V 16V 16V 16V Temp. Range -55 to 125C -55 to 85C -55 to 125C -55 to 85C -55 to 125C -55 to 85C 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 "Oscillator Configurations" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. DS39977C-page 50 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY In planning the application's routing and I/O assignments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" Primary Oscillator C1 C2 FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS OSC1 OSC2 GND T1OSO 2.7 Unused I/Os Timer1 Oscillator Crystal T1OS I Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low. T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 GND Oscillator Crystal C1 OSCI DEVICE PINS 2011 Microchip Technology Inc. Preliminary DS39977C-page 51 PIC18F66K80 FAMILY NOTES: DS39977C-page 52 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.0 3.1 OSCILLATOR CONFIGURATIONS Oscillator Types To optimize power consumption when using EC/HS/ XT/LP/RC as the primary oscillator, the frequency input range can be configured to yield an optimized power bias: * Low-Power Bias - External frequency less than 160 kHz * Medium Power Bias - External frequency between 160 kHz and 16 MHz * High-Power Bias - External frequency greater than 16 MHz All of these modes are selected by the user by programming the FOSC<3:0> Configuration bits (CONFIG1H<3:0>). In addition, PIC18F66K80 family devices can switch between different clock sources, either under software control, or under certain conditions, automatically. This allows for additional power savings by managing device clock speed in real time without resetting the application. The clock sources for the PIC18F66K80 family of devices are shown in Figure 3-1. For the HS and EC mode, there are additional power modes of operation, depending on the frequency of operation. HS1 is the Medium Power mode with a frequency range of 4 MHz to 16 MHz. HS2 is the High-Power mode, where the oscillator frequency can go from 16 MHz to 25 MHz. HS1 and HS2 are achieved by setting the CONFIG1H<3:0> bits correctly. (For details, see Register 28-2 on page 464.) EC mode has these modes of operation: * EC1 - For low power with a frequency range up to 160 kHz * EC2 - Medium power with a frequency range of 160 kHz to 16 MHz * EC3 - High power with a frequency range of 16 MHz to 64 MHz EC1, EC2 and EC3 are achieved by setting the CONFIG1H<3:0> correctly. (For details, see Register 28-2 on page 464.) Table 3-1 shows the HS and EC modes' frequency range and FOSC<3:0> settings. The PIC18F66K80 family of devices can be operated in the following oscillator modes: External Clock, RA6 Available External Clock, Clock Out RA6 (FOSC/4 on RA6) * HS High-Speed Crystal/Resonator * XT Crystal/Resonator * LP Low-Power Crystal * RC External Resistor/Capacitor, RA6 Available * RCIO External Resistor/Capacitor, Clock Out RA6 (FOSC/4 on RA6) * INTIO2 Internal Oscillator with I/O on RA6 and RA7 * INTIO1 Internal Oscillator with FOSC/4 Output on RA6 and I/O on RA7 There is also an option for running the 4xPLL on any of the clock sources in the input frequency range of 4 to 16 MHz. The PLL is enabled by setting the PLLCFG bit (CONFIG1H<4>) or the PLLEN bit (OSCTUNE<6>). For the EC and HS modes, the PLLEN (software) or PLLCFG (CONFIG1H<4>) bit can be used to enable the PLL. For the INTIOx modes (HF-INTOSC): * Only the PLLEN can enable the PLL (PLLCFG is ignored). * When the oscillator is configured for the internal oscillator (FOSC<3:0> = 100x), the PLL can be enabled only when the HF-INTOSC frequency is 4, 8 or 16 MHz. When the RA6 and RA7 pins are not used for an oscillator function or CLKOUT function, they are available as general purpose I/Os. * EC * ECIO 2011 Microchip Technology Inc. Preliminary DS39977C-page 53 PIC18F66K80 FAMILY TABLE 3-1: EC1 (low power) (EC1 & EC1IO) EC2 (medium power) (EC2 & EC2IO) EC3 (high power) (EC3 & EC3IO) HS1 (medium power) HS2 (high power) XT LP RC (External) INTIO HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS Mode Frequency Range DC-160 kHz 160 kHz-16 MHz 16 MHz-64 MHz 4 MHz-16 MHz 16 MHz-25 MHz 100 kHz-4 MHz 31.25 kHz 0-4 MHz 32 kHz-16 MHz FOSC<3:0> Setting 1101 1100 1011 1010 0101 0100 0011 0010 0001 0000 001x 100x (and OSCCON, OSCCON2) FIGURE 3-1: SOSCO SOSCI PIC18F66K80 FAMILY CLOCK DIAGRAM MUX OSC2 OSC1 MUX MUX 4x PLL Peripherals CPU FOSC<3:0> PLLEN and PLLCFG IDLEN 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 31 kHz 16 MHz 111 8 MHz 4 MHz 2 MHz 1 MHz 110 101 Clock Control SCS<1:0> HF-INTOSC 16 MHz to 31 kHz Postscaler MUX 100 011 FOSC<3:0> 500 kHz 010 250 kHz 001 31 kHz 000 MUX Postscaler MF-INTOSC 500 kHz to 31 kHz 500 kHz 250 kHz 31 kHz IRCF<2:0> MUX INTSRC MFIOSEL LF-INTOSC 31 kHz 31 kHz DS39977C-page 54 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.2 Control Registers The OSCCON register (Register 3-1) controls the main aspects of the device clock's operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. The OSCTUNE register (Register 3-3) controls the tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Section 3.5.3 "PLL Frequency Multiplier"). REGISTER 3-1: R/W-0 IDLEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 OSCCON: OSCILLATOR CONTROL REGISTER R/W-1 R/W-0 IRCF1 (2) R/W-0 IRCF0 (2) R(1) OSTS R-0 HFIOFS R/W-0 SCS1 (4) R/W-0 SCS0(4) bit 0 IRCF2 (2) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed IRCF<2:0>: Internal Oscillator Frequency Select bits(2) 111 = HF-INTOSC output frequency is used (16 MHz) 110 = HF-INTOSC/2 output frequency is used (8 MHz, default) 101 = HF-INTOSC/4 output frequency is used (4 MHz) 100 = HF-INTOSC/8 output frequency is used (2 MHz) 011 = HF-INTOSC/16 output frequency is used (1 MHz) If INTSRC = 0 and MFIOSEL = 0:(3,5) 010 = HF-INTOSC/32 output frequency is used (500 kHz) 001 = HF-INTOSC/64 output frequency is used (250 kHz) 000 = LF-INTOSC output frequency is used (31.25 kHz)(6) If INTSRC = 1 and MFIOSEL = 0:(3,5) 010 = HF-INTOSC/32 output frequency is used (500 kHz) 001 = HF-INTOSC/64 output frequency is used (250 kHz) 000 = HF-INTOSC/512 output frequency is used (31.25 kHz) If INTSRC = 0 and MFIOSEL = 1:(3,5) 010 = MF-INTOSC output frequency is used (500 kHz) 001 = MF-INTOSC/2 output frequency is used (250 kHz) 000 = LF-INTOSC output frequency is used (31.25 kHz)(6) If INTSRC = 1 and MFIOSEL = 1:(3,5) 010 = MF-INTOSC output frequency is used (500 kHz) 001 = MF-INTOSC/2 output frequency is used (250 kHz) 000 = MF-INTOSC/16 output frequency is used (31.25 kHz) OSTS: Oscillator Start-up Timer Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running, as defined by FOSC<3:0> 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready - device is running from internal oscillator (HF-INTOSC, MF-INTOSC or LF-INTOSC) Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>). Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Source selected by the INTSRC bit (OSCTUNE<7>). Modifying these bits will cause an immediate clock source switch. INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. Lowest power option for an internal source. bit 6-4 bit 3 Note 1: 2: 3: 4: 5: 6: 2011 Microchip Technology Inc. Preliminary DS39977C-page 55 PIC18F66K80 FAMILY REGISTER 3-1: bit 2 OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) HFIOFS: HF-INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable SCS<1:0>: System Clock Select bits(4) 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC) 01 = SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL. Defined by the FOSC<3:0> Configuration bits, CONFIG1H<3:0>.) Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>). Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Source selected by the INTSRC bit (OSCTUNE<7>). Modifying these bits will cause an immediate clock source switch. INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. Lowest power option for an internal source. bit 1-0 Note 1: 2: 3: 4: 5: 6: REGISTER 3-2: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0 U-0 -- R/W-0 SOSCDRV(1) R/W-0 SOSCGO U-0 -- R-x MFIOFS R/W-0 MFIOSEL bit 0 SOSCRUN W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC Unimplemented: Read as `0' SOSCDRV: Secondary Oscillator Drive Control bit(1) 1 = High-Power SOSC circuit is selected 0 = Low/High-Power select is done via the SOSCSEL<1:0> Configuration bits SOSCGO: Oscillator Start Control bit 1 = Oscillator is running even if no other sources are requesting it. 0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.) Unimplemented: Read as `0' MFIOFS: MF-INTOSC Frequency Stable bit 1 = MF-INTOSC is stable 0 = MF-INTOSC is not stable MFIOSEL: MF-INTOSC Select bit 1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MF-INTOSC is not used When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39977C-page 56 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 3-3: R/W-0 INTSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 PLLEN R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 16 MHz INTOSC source (divide-by-512 enabled, HF-INTOSC) 0 = 31 kHz device clock derived from INTOSC 31 kHz oscillator (LF-INTOSC) PLLEN: Frequency Multiplier PLL Enable bit 1 = PLL is enabled 0 = PLL is disabled TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits 011111 = Maximum frequency * * * * 000001 000000 = Center frequency; fast RC oscillator is running at the calibrated frequency 111111 * * * * 100000 = Minimum frequency bit 6 bit 5-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 57 PIC18F66K80 FAMILY 3.3 Clock Sources and Oscillator Switching In addition to being a primary clock source in some circumstances, the internal oscillator is available as a power-managed mode clock source. The LF-INTOSC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The internal oscillator block is discussed in more detail in Section 3.6 "Internal Oscillator Block". The PIC18F66K80 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. When an alternate clock source is enabled, various power-managed operating modes are available. Essentially, PIC18F66K80 family devices have these independent clock sources: * Primary oscillators * Secondary oscillators * Internal oscillator The primary oscillators can be thought of as the main device oscillators. These are any external oscillators connected to the OSC1 and OSC2 pins, and include the External Crystal and Resonator modes and the External Clock modes. If selected by the FOSC<3:0> Configuration bits (CONFIG1H<3:0>), the internal oscillator block may be considered a primary oscillator. The internal oscillator block can be one of the following: * 31 kHz LF-INTOSC source * 31 kHz to 500 kHz MF-INTOSC source * 31 kHz to 16 MHz HF-INTOSC source The particular mode is defined by the FOSC Configuration bits. The details of these modes are covered in Section 3.5 "External Oscillator Modes". The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pin. These sources may continue to operate, even after the controller is placed in a power-managed mode. PIC18F66K80 family devices offer the SOSC (Timer1/3/5/7) oscillator as a secondary oscillator source. The SOSC can be enabled from any peripheral that requests it. The SOSC can be enabled several ways by doing one of the following: * The SOSC is selected as the source by either of the odd timers, which is done by each respective SOSCEN bit (TxCON<3>) * The SOSC is selected as the CPU clock source by the SCS bits (OSCCON<1:0>) * The SOSCGO bit is set (OSCCON2<3>) The SOSCGO bit is used to warm up the SOSC so that it is ready before any peripheral requests it. The secondary oscillator has three Run modes. The SOSCSEL<1:0> bits (CONFIG1L<4:3>) decide the SOSC mode of operation: * 11 = High-Power SOSC Circuit * 10 = Digital (SCLKI) mode * 11 = Low-Power SOSC Circuit If a secondary oscillator is not desired and digital I/O on port pins, RC0 and RC1, is needed, the SOSCSEL bits must be set to Digital mode. 3.3.1 OSC1/OSC2 OSCILLATOR The OSC1/OSC2 oscillator block is used to provide the oscillator modes and frequency ranges: Mode LP XT HS EC EXTRC Design Operating Frequency 31.25-100 kHz 100 kHz to 4 MHz 4 MHz to 25 MHz 0 to 64 MHz (external clock) 0 to 4 MHz (external RC) The crystal-based oscillators (XT, HS and LP) have a built-in start-up time. The operation of the EC and EXTRC clocks is immediate. 3.3.2 CLOCK SOURCE SELECTION The System Clock Select bits, SCS<1:0> (OSCCON<1:0>), select the clock source. The available clock sources are the primary clock defined by the FOSC<3:0> Configuration bits, the secondary clock (SOSC oscillator) and the internal oscillator. The clock source changes after one or more of the bits is written to, following a brief clock transition interval. The OSTS (OSCCON<3>) and SOSCRUN (OSCCON2<6>) bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The SOSCRUN bit indicates when the SOSC oscillator (from Timer1/3/5/7) is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If neither of these bits is set, the INTOSC is providing the clock or the internal oscillator has just started and is not yet stable. The IDLEN bit (OSCCON<7>) determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. DS39977C-page 58 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 "Power-Managed Modes". Note 1: The Timer1/3/5/7 oscillator must be enabled to select the secondary clock source. The Timerx oscillator is enabled by setting the SOSCEN bit in the Timerx Control register (TxCON<3>). If the Timerx oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timerx oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timerx oscillator starts. 3.4 RC Oscillator For timing-insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings. The actual oscillator frequency is a function of several factors: * Supply voltage * Values of the external resistor (REXT) and capacitor (CEXT) * Operating temperature Given the same device, operating voltage and temperature, and component values, there will also be unit to unit frequency variations. These are due to factors such as: * Normal manufacturing variation * Difference in lead frame capacitance between package types (especially for low CEXT values) * Variations within the tolerance of the limits of REXT and CEXT In the RC Oscillator mode, the oscillator frequency, divided by 4, is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-2 shows how the R/C combination is connected. 3.3.2.1 System Clock Selection and Device Resets Since the SCS bits are cleared on all forms of Reset, this means the primary oscillator defined by the FOSC<3:0> Configuration bits is used as the primary clock source on device Resets. This could either be the internal oscillator block by itself, or one of the other primary clock sources (HS, EC, XT, LP, External RC and PLL-enabled modes). In those cases when the internal oscillator block, without PLL, is the default clock on Reset, the Fast RC Oscillator (INTOSC) will be used as the device clock source. It will initially start at 8 MHz; the postscaler selection that corresponds to the Reset value of the IRCF<2:0> bits (`110'). Regardless of which primary oscillator is selected, INTOSC will always be enabled on device power-up. It serves as the clock source until the device has loaded its configuration values from memory. It is at this point that the FOSC Configuration bits are read and the oscillator selection of the operational mode is made. Note that either the primary clock source or the internal oscillator will have two bit setting options for the possible values of the SCS<1:0> bits, at any given time. FIGURE 3-2: VDD REXT RC OSCILLATOR MODE OSC1 CEXT VSS FOSC/4 OSC2/CLKO Internal Clock PIC18F66K80 Recommended values: 3 k REXT 100 k 20 pF CEXT 300 pF The RCIO Oscillator mode (Figure 3-3) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). 3.3.3 OSCILLATOR TRANSITIONS FIGURE 3-3: VDD REXT RCIO OSCILLATOR MODE PIC18F66K80 family devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 "Entering Power-Managed Modes". OSC1 CEXT VSS RA6 I/O (OSC2) Internal Clock PIC18F66K80 Recommended values: 3 k REXT 100 k 20 pF CEXT 300 pF 2011 Microchip Technology Inc. Preliminary DS39977C-page 59 PIC18F66K80 FAMILY 3.5 3.5.1 External Oscillator Modes CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES) TABLE 3-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq. 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 C2 27 pF 22 pF 15 pF In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-4 shows the pin connections. The oscillator design requires the use of a crystal rated for parallel resonant operation. Note: Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer's specifications. Osc Type HS 27 pF 22 pF 15 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the Microchip application notes cited in Table 3-2 for oscillator specific information. Also see the notes following this table for additional information. TABLE 3-2: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode HS Freq. 8.0 MHz 16.0 MHz OSC1 27 pF 22 pF OSC2 27 pF 22 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the following application notes for oscillator-specific information: * AN588, "PIC(R) Microcontroller Oscillator Design Guide" * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" * AN849, "Basic PIC(R) Oscillator Design" * AN943, "Practical PIC(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" See the notes following Table 3-3 for additional information. Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. FIGURE 3-4: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION) OSC1 To Internal Logic Sleep C1(1) XTAL OSC2 C2(1) Note 1: 2: 3: RS(2) RF(3) PIC18F66K80 See Table 3-2 and Table 3-3 for initial values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the oscillator mode chosen. DS39977C-page 60 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.5.2 EXTERNAL CLOCK INPUT (EC MODES) 3.5.3.1 HSPLL and ECPLL Modes The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-5 shows the pin connections for the EC Oscillator mode. The HSPLL and ECPLL modes provide the ability to selectively run the device at four times the external oscillating source to produce frequencies up to 64 MHz. The PLL is enabled by setting the PLLEN bit (OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>). For the HF-INTOSC as primary, the PLL must be enabled with the PLLEN. This provides a software control for the PLL, enabling even if PLLCFG is set to `1', so that the PLL is enabled only when the HF-INTOSC frequency is within the 4 MHz to16 MHz input range. This also enables additional flexibility for controlling the application's clock speed in software. The PLLEN should be enabled in HF-INTOSC mode only if the input frequency is in the range of 4 MHz-16 MHz. FIGURE 3-5: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI Clock from Ext. System FOSC/4 FIGURE 3-7: PLL BLOCK DIAGRAM PIC18F66K80 OSC2/CLKO PLLCFG (CONFIG1H<4>) PLL Enable (OSCTUNE<6>) An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-6. In this configuration, the divide-by-4 output on OSC2 is not available. Current consumption in this configuration will be somewhat higher than EC mode, as the internal oscillator's feedback circuitry will be enabled (in EC mode, the feedback circuit is disabled). OSC2 HS or EC Mode OSC1 FIN FOUT Phase Comparator Loop Filter FIGURE 3-6: Clock from Ext. System Open OSC1 PIC18F66K80 (HS Mode) OSC2 3.5.3.2 PLL and HF-INTOSC 3.5.3 PLL FREQUENCY MULTIPLIER A Phase Lock Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. The PLL is available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up to 64 MHz. The operation of INTOSC with the PLL is described in Section 3.6.2 "INTPLL Modes". Care should be taken that the PLL is enabled only if the HF-INTOSC postscaler is configured for 4 MHz, 8 MHz or 16 MHz. 2011 Microchip Technology Inc. Preliminary DS39977C-page 61 MUX EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) 4 VCO SYSCLK PIC18F66K80 FAMILY 3.6 Internal Oscillator Block FIGURE 3-8: RA7 INTIO1 OSCILLATOR MODE I/O (OSC1) The PIC18F66K80 family of devices includes an internal oscillator block which generates two different clock signals. Either clock can be used as the microcontroller's clock source, which may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. The Internal oscillator consists of three blocks, depending on the frequency of operation. They are HF-INTOSC, MF-INTOSC and LF-INTOSC. In HF-INTOSC mode, the internal oscillator can provide a frequency ranging from 31 KHz to 16 MHz, with the postscaler deciding the selected frequency (IRCF<2:0>). The INTSRC bit (OSCTUNE<7>) and MFIOSEL bit (OSCCON2<0>) also decide which INTOSC provides the lower frequency (500 kHz to 31 KHz). For the HF-INTOSC to provide these frequencies, INTSRC = 1 and MFIOSEL = 0. In HF-INTOSC, the postscaler (IRCF<2:0>) provides the frequency range of 31 kHz to 16 MHz. If HF-INTOSC is used with the PLL, the input frequency to the PLL should be 4 MHz to 16 MHz (IRCF<2:0> = 111, 110 or 101). For MF-INTOSC mode to provide a frequency range of 500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1. The postscaler (IRCF<2:0>), in this mode, provides the frequency range of 31 kHz to 500 kHz. The LF-INTOSC can provide only 31 kHz if INTSRC = 0. The LF-INTOSC provides 31 kHz and is enabled if it is selected as the device clock source. The mode is enabled automatically when any of the following are enabled: * Power-up Timer * Fail-Safe Clock Monitor * Watchdog Timer * Two-Speed Start-up These features are discussed in greater detail in Section 28.0 "Special Features of the CPU". The clock source frequency (HF-INTOSC, MF-INTOSC or LF-INTOSC direct) is selected by configuring the IRCF bits of the OSCCON register, as well the INTSRC and MFIOSEL bits. The default frequency on device Resets is 8 MHz. PIC18F66K80 FOSC/4 OSC2 FIGURE 3-9: RA7 INTIO2 OSCILLATOR MODE I/O (OSC1) PIC18F66K80 RA6 I/O (OSC2) 3.6.2 INTPLL MODES The 4x Phase Lock Loop (PLL) can be used with the HF-INTOSC to produce faster device clock speeds than are normally possible with the internal oscillator sources. When enabled, the PLL produces a clock speed of 16 MHz or 64 MHz. PLL operation is controlled through software. The control bits, PLLEN (OSCTUNE<6>) and PLLCFG (CONFIG1H<4>), are used to enable or disable its operation. The PLL is available only to HF-INTOSC. The other oscillator is set with HS and EC modes. Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 16 MHz (OSCCON<6:4> = 111, 110 or 101). Like the INTIO modes, there are two distinct INTPLL modes available: * In INTPLL1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. Externally, this is identical in appearance to INTIO1 (Figure 3-8). * In INTPLL2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. Externally, this is identical to INTIO2 (Figure 3-9). 3.6.1 INTIO MODES Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct oscillator configurations, which are determined by the FOSC Configuration bits, are available: * In INTIO1 mode, the OSC2 pin (RA6) outputs FOSC/4, while OSC1 functions as RA7 (see Figure 3-8) for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 3-9). Both are available as digital input and output ports. DS39977C-page 62 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.6.3 INTERNAL OSCILLATOR OUTPUT FREQUENCY AND TUNING 3.6.4.3 Compensating with the CCP Module in Capture Mode The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 16 MHz. It can be adjusted in the user's application by writing to TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE register (Register 3-3). When the OSCTUNE register is modified, the INTOSC (HF-INTOSC and MF-INTOSC) frequency will begin shifting to the new frequency. The oscillator will require some time to stabilize. Code execution continues during this shift and there is no indication that the shift has occurred. The LF-INTOSC oscillator operates independently of the HF-INTOSC or the MF-INTOSC source. Any changes in the HF-INTOSC or the MF-INTOSC source, across voltage and temperature, are not necessarily reflected by changes in LF-INTOSC or vice versa. The frequency of LF-INTOSC is not affected by OSCTUNE. A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. 3.6.4 INTOSC FREQUENCY DRIFT 3.7 Reference Clock Output The INTOSC frequency may drift as VDD or temperature changes and can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. Depending on the device, this may have no effect on the LF-INTOSC clock source frequency. Tuning INTOSC requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. Three compensation techniques are shown here. In addition to the FOSC/4 clock output, in certain oscillator modes, the device clock in the PIC18F66K80 family can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 3-4). Setting the ROON bit (REFOCON<7>) makes the clock signal available on the REFO (RC3) pin. The RODIV<3:0> bits enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON<5:4>) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on RE3 when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for an EC or HS mode. If not, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. 3.6.4.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low. To compensate, increment OSCTUNE to increase the clock frequency. 3.6.4.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the SOSC oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2011 Microchip Technology Inc. Preliminary DS39977C-page 63 PIC18F66K80 FAMILY REGISTER 3-4: R/W-0 ROON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 -- R/W-0 ROSSLP R/W-0 ROSEL(1) R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 0 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output available on REFO pin 0 = Reference oscillator output disabled Unimplemented: Read as `0' ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit(1) 1 = Primary oscillator (EC or HS) used as the base clock 0 = System clock used as the base clock; base clock reflects any clock switching of the device RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value For ROSEL (REFOCON<4>), the primary oscillator is available only when configured as the default via the FOSC settings. This is regardless of whether the device is in Sleep mode. bit 6 bit 5 bit 4 bit 3-0 Note 1: DS39977C-page 64 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.8 Effects of Power-Managed Modes on the Various Clock Sources 3.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.6.1 "Power-up Timer (PWRT)". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up time of about 64 ms (Parameter 33, Table 31-11); it is always enabled. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS, XT or LP modes). The OST does this by counting 1,024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval, TCSD (Parameter 38, Table 31-11), following POR, while the controller becomes ready to execute instructions. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the SOSC oscillator is operating and providing the device clock. The SOSC oscillator may also run in all power-managed modes if required to clock SOSC. In RC_RUN and RC_IDLE modes, the internal oscillator provides the device clock source. The 31 kHz LF-INTOSC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 28.2 "Watchdog Timer (WDT)" through Section 28.5 "Fail-Safe Clock Monitor" for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTOSC is required to support WDT operation. The SOSC oscillator may be operating to support Timer1 or 3. Other features may be operating that do not require a device clock source (i.e., MSSP slave, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 31.2 "DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended)". TABLE 3-4: EC, ECPLL HS, HSPLL OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC1 Pin Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level I/O pin, RA6, direction controlled by TRISA<6> OSC2 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level I/O pin, RA6, direction controlled by TRISA<7> Oscillator Mode INTOSC, INTPLL1/2 Note: See Section 5.0 "Reset" for time-outs due to Sleep and MCLR Reset. 2011 Microchip Technology Inc. Preliminary DS39977C-page 65 PIC18F66K80 FAMILY NOTES: DS39977C-page 66 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 4.0 POWER-MANAGED MODES The PIC18F66K80 family of devices offers a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (such as battery-powered devices). There are three categories of power-managed mode: * Run modes * Idle modes * Sleep mode There is an Ultra Low-Power Wake-up (ULPWU) for waking from Sleep mode. These categories define which portions of the device are clocked, and sometimes, at what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block). The Sleep mode does not use a clock source. The ULPWU mode, on the RA0 pin, enables a slow falling voltage to generate a wake-up, even from Sleep, without excess current consumption. (See Section 4.7 "Ultra Low-Power Wake-up".) The power-managed modes include several powersaving features offered on previous PIC(R) devices. One is the clock switching feature, offered in other PIC18 devices. This feature allows the controller to use the SOSC oscillator instead of the primary one. Another power-saving feature is Sleep mode, offered by all PIC devices, where all device clocks are stopped. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1. 4.1.1 CLOCK SOURCES The SCS<1:0> bits select one of three clock sources for power-managed modes. Those sources are: * The primary clock as defined by the FOSC<3:0> Configuration bits * The secondary clock (the SOSC oscillator) * The internal oscillator block (for LF-INTOSC modes) 4.1.2 ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source and determine which Run or Idle mode is used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These considerations are discussed in Section 4.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entering the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current and impending mode, a change to a power-managed mode does not always require setting all of the previously discussed bits. Many transitions can be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured as desired, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. 4.1 Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: * Will the CPU be clocked or not * What will be the clock source TABLE 4-1: Mode Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1: 2: POWER-MANAGED MODES OSCCON Bits IDLEN<7> 0 N/A N/A N/A 1 1 1 (1) Module Clocking Available Clock and Oscillator Source CPU Off Clocked Clocked Clocked Off Off Off Peripherals Off Clocked Clocked Clocked Clocked Clocked Clocked None - All clocks are disabled Primary - XT, LP, HS, EC, RC and PLL modes. This is the normal, full-power execution mode. Secondary - SOSC Oscillator Internal oscillator block(2) Primary - LP, XT, HS, RC, EC Secondary - SOSC oscillator Internal oscillator block(2) SCS<1:0> N/A 00 01 1x 00 01 1x IDLEN reflects its value when the SLEEP instruction is executed. Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC source. 2011 Microchip Technology Inc. Preliminary DS39977C-page 67 PIC18F66K80 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS 4.1.4 MULTIPLE SLEEP COMMANDS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. The HFINTOSC and MF-INTOSC are termed as INTOSC in this chapter. Three bits indicate the current clock source and its status, as shown in Table 4-2. The three bits are: * OSTS (OSCCON<3>) * HFIOFS (OSCCON<2>) * SOSCRUN (OSCCON2<6>) The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. 4.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. TABLE 4-2: SYSTEM CLOCK INDICATOR HFIOFS or OSTS SOSCRUN MFIOFS 1 0 0 1 0 1 0 1 0 0 1 0 4.2.1 PRI_RUN MODE Main Clock Source Primary Oscillator INTOSC (HF-INTOSC or MF-INTOSC) Secondary Oscillator MF-INTOSC or HF-INTOSC as Primary Clock Source LF-INTOSC is Running or INTOSC is not yet Stable The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled. (For details, see Section 28.4 "Two-Speed Start-up".) In this mode, the OSTS bit is set. The HFIOFS or MFIOFS bit may be set if the internal oscillator block is the primary clock source. (See Section 3.2 "Control Registers".) 4.2.2 SEC_RUN MODE 0 0 0 When the OSTS bit is set, the primary clock is providing the device clock. When the HFIOFS or MFIOFS bit is set, the INTOSC output is providing a stable clock source to a divider that actually drives the device clock. When the SOSCRUN bit is set, the SOSC oscillator is providing the clock. If none of these bits are set, either the LF-INTOSC clock source is clocking the device or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC<3:0> Configuration bits (CONFIG1H<3:0>). Then, the OSTS and HFIOFS or MFIOFS bits can be set when in PRI_RUN or PRI_IDLE mode. This indicates that the primary clock (INTOSC output) is generating a stable output. Entering another INTOSC power-managed mode at the same frequency would clear the OSTS bit. Note 1: Caution should be used when modifying a single IRCF bit. At a lower VDD, it is possible to select a higher clock speed than is supportable by that VDD. Improper device operation may result if the VDD/ FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. The SEC_RUN mode is the compatible mode to the "clock-switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the SOSC oscillator. This enables lower power consumption while retaining a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> bits to `01'. The device clock source is switched to the SOSC oscillator (see Figure 4-1), the primary oscillator is shut down, the SOSCRUN bit (OSCCON2<6>) is set and the OSTS bit is cleared. Note: The SOSC oscillator can be enabled by setting the SOSCGO bit (OSCCON2<3>). If this bit is set, the clock switch to the SEC_RUN mode can switch immediately once SCS<1:0> are set to `01'. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the SOSC oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the SOSCRUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. DS39977C-page 68 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 SOSCI OSC1 CPU Clock Peripheral Clock Program Counter 1 2 3 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Clock Transition(1) PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 SOSC OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> Bits Changed PC OSTS Bit Set Clock Transition(2) PC + 2 PC + 4 Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the LF-INTOSC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block - either LF-INTOSC or INTOSC (MF-INTOSC or HF-INTOSC) - there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. This mode is entered by setting the SCS1 bit to `1'. To maintain software compatibility with future devices, it is recommended that the SCS0 bit also be cleared, even though the bit is ignored. When the clock source is switched to the INTOSC multiplexer (see Figure 4-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Note: Caution should be used when modifying a single IRCF bit. At a lower VDD, it is possible to select a higher clock speed than is supportable by that VDD. Improper device operation may result if the VDD/ FOSC specifications are violated. 2011 Microchip Technology Inc. Preliminary DS39977C-page 69 PIC18F66K80 FAMILY If the IRCF bits and the INTSRC bit are all clear, the INTOSC output (HF-INTOSC/MF-INTOSC) is not enabled and the HFIOFS and MFIOFS bits will remain clear. There will be no indication of the current clock source. The LF-INTOSC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC or MFIOSEL is set, the HFIOFS or MFIOFS bit is set after the INTOSC output becomes stable. For details, see Table 4-3. TABLE 4-3: IRCF<2:0> 000 000 000 Non-Zero Non-Zero INTERNAL OSCILLATOR FREQUENCY STABILITY BITS INTSRC 0 1 1 x x MFIOSEL x 0 1 0 1 Status of MFIOFS or HFIOFS when INTOSC is Stable MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the HFIOFS or MFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor (FSCM) is enabled. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST (Parameter 39, Table 31-11). If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the HFIOFS or MFIOFS bit will remain set. DS39977C-page 70 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 LF-INTOSC OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 1 2 3 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Clock Transition(1) Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> Bits Changed PC OSTS Bit Set PC + 2 PC + 4 TPLL(1) 1 2 n-1 n Clock Transition(2) Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 2011 Microchip Technology Inc. Preliminary DS39977C-page 71 PIC18F66K80 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode in the PIC18F66K80 family of devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Entering Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the LF-INTOSC source will continue to operate. If the SOSC oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-6). Alternately, the device will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor is enabled (see Section 28.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits. The CPU, however, will not be clocked. The clock source status bits are not affected. This approach is a quick method to switch from a given Run mode to its corresponding Idle mode. If the WDT is selected, the LF-INTOSC source will continue to operate. If the SOSC oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (Parameter 38, Table 31-11) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT timeout will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 PC + 2 FIGURE 4-6: OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(1) TPLL(1) PC Wake Event OSTS Bit Set PC + 2 PC + 4 PC + 6 Note1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39977C-page 72 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate, primary clock source, since the clock source does not have to "warm-up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<3:0> Configuration bits. The OSTS bit remains set (see Figure 4-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD (Parameter 39, Table 31-11), is required between the wake event and the start of code execution. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-8). In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS<1:0> bits to `01' and execute SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the SOSCRUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the SOSC oscillator. After an interval of TCSD following the wake event, the CPU begins executing code that is being clocked by the SOSC oscillator. The IDLEN and SCS bits are not affected by the wake-up and the SOSC oscillator continues to run (see Figure 4-8). FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 FIGURE 4-8: Q1 OSC1 CPU Clock Peripheral Clock Program Counter TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q2 Q3 Q4 TCSD PC Wake Event 2011 Microchip Technology Inc. Preliminary DS39977C-page 73 PIC18F66K80 FAMILY 4.4.3 RC_IDLE MODE 4.5 In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode provides controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. To maintain software compatibility with future devices, it is recommended that SCS0 also be cleared, though its value is ignored. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC/MFIOSEL bit is set, the INTOSC output is enabled. The HFIOFS/MFIOFS bits become set, after the INTOSC output becomes stable, after an interval of TIOBST (Parameter 38, Table 31-11). For information on the HFIOFS/MFIOFS bits, see Table 4-3. Clocks to the peripherals continue while the INTOSC source stabilizes. The HFIOFS/MFIOFS bits will remain set if the IRCF bits were previously at a nonzero value or if INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the HFIOFS/MFIOFS bits will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD (Parameter 38, Table 31-11) following the wake event, the CPU begins executing code clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. Selective Peripheral Module Control Idle mode allows users to substantially reduce power consumption by stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what this mode does not provide: the allocation of power resources to the CPU processing with minimal power consumption from the peripherals. PIC18F66K80 family devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: * Peripheral Enable bit, generically named XXXEN - Located in the respective module's main control register * Peripheral Module Disable (PMD) bit, generically named, XXXMD - Located in one of the PMDx Control registers (PMD0, PMD1 or PMD2) Disabling a module by clearing its XXXEN bit disables the module's functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as the second approach. Most peripheral modules have an enable bit. In contrast, setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral are also disabled, so writes to those registers have no effect and read values are invalid. Many peripheral modules have a corresponding PMD bit. There are three PMD registers in PIC18F66K80 family devices: PMD0, PMD1 and PMD2. These registers have bits associated with each module for disabling or enabling a particular peripheral. DS39977C-page 74 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 4-1: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 -- U-0 -- U-0 -- R/W-0 MODMD R/W-0 ECANMD R/W-0 CMP2MD R/W-0 CMP1MD bit 0 Unimplemented: Read as `0' MODMD: Modulator Output Module Disable bit(1) 1 = The modulator output module is disabled. All Modulator Output registers are held in Reset and are not writable. 0 = The modulator output module is enabled ECANMD: Enhanced CAN Module Disable bit 1 = The Enhanced CAN module is disabled. All Enhanced CAN registers are held in Reset and are not writable. 0 = The Enhanced CAN module is enabled CMP2MD: Comparator 2 Module Disable bit 1 = The Comparator 2 module is disabled. All Comparator 2 registers are held in Reset and are not writable. 0 = The Comparator 2 module is enabled CMP1MD: Comparator 1 Module Disable bit 1 = The Comparator 1 module is disabled. All Comparator 1 registers are held in Reset and are not writable. 0 = The Comparator 1 module is enabled Only implemented on devices with 64 pins (PIC18F6XK80, PIC18LF6XK80). bit 2 bit 1 bit 0 Note 1: 2011 Microchip Technology Inc. Preliminary DS39977C-page 75 PIC18F66K80 FAMILY REGISTER 4-2: R/W-0 PSPMD bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 CTMUMD R/W-0 ADCMD R/W-0 TMR4MD R/W-0 TMR3MD R/W-0 TMR2MD R/W-0 TMR1MD R/W-0 TMR0MD bit 0 PSPMD: Peripheral Module Disable bit(1) 1 = The PSP module is disabled. All PSP registers are held in Reset and are not writable. 0 = The PSP module is enabled CTMUMD: PMD CTMU Disable bit 1 = The CTMU module is disabled. All CTMU registers are held in Reset and are not writable. 0 = The CTMU module is enabled ADCMD: ADC Module Disable bit 1 = The ADC module is disabled. All ADC registers are held in Reset and are not writable. 0 = The ADC module is enabled TMR4MD: TMR4MD Disable bit 1 = The Timer4 module is disabled. All Timer4 registers are held in Reset and are not writable. 0 = The Timer4 module is enabled TMR3MD: TMR3MD Disable bit 1 = The Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable. 0 = The Timer3 module is enabled TMR2MD: TMR2MD Disable bit 1 = The Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable. 0 = The Timer2 module is enabled TMR1MD: TMR1MD Disable bit 1 = The Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable. 0 = The Timer1 module is enabled TMR0MD: Timer0 Module Disable bit 1 = The Timer0 module is disabled. All Timer0 registers are held in Reset and are not writable. 0 = The Timer0 module is enabled Unimplemented on devices with 28-pin devices (PIC18F2XK80, PIC18LF2XK80). bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39977C-page 76 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 4-3: R/W-0 CCP5MD bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 CCP4MD R/W-0 CCP3MD R/W-0 CCP2MD R/W-0 CCP1MD R/W-0 UART2MD R/W-0 UART1MD R/W-0 SSPMD bit 0 CCP5MD: CCP5 Module Disable bit 1 = The CCP5 module is disabled. All CCP5 registers are held in Reset and are not writable. 0 = The CCP5 module is enabled CCP4MD: CCP4 Module Disable bit 1 = The CCP4 module is disabled. All CCP4 registers are held in Reset and are not writable. 0 = The CCP4 module is enabled CCP3MD: CCP3 Module Disable bit 1 = The CCP3 module is disabled. All CCP3 registers are held in Reset and are not writable. 0 = The CCP3 module is enabled CCP2MD: CCP2 Module Disable bit 1 = The CCP2 module is disabled. All CCP2 registers are held in Reset and are not writable. 0 = The CCP2 module is enabled CCP1MD: ECCP1 Module Disable bit 1 = The ECCP1 module is disabled. All ECCP1 registers are held in Reset and are not writable. 0 = The ECCP1 module is enabled UART2MD: EUSART2 Module Disable bit 1 = The USART2 module is disabled. All USART2 registers are held in Reset and are not writable. 0 = The USART2 module is enabled UART1MD: EUSART1 Module Disable bit 1 = The USART1 module is disabled. All USART1 registers are held in Reset and are not writable. 0 = The USART1 module is enabled SSPMD: MSSP Module Disable bit 1 = The MSSP module is disabled. All SSP registers are held in Reset and are not writable. 0 = The MSSP module is enabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 77 PIC18F66K80 FAMILY 4.6 Exiting Idle and Sleep Modes 4.6.3 EXIT BY RESET An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 4.2 "Run Modes", Section 4.3 "Sleep Mode" and Section 4.4 "Idle Modes"). Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the HFIOFS/MFIOFS bits are set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up, and the type of oscillator, if the new clock source is the primary clock. Exit delays are summarized in Table 4-4. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 28.4 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 28.5 "Fail-Safe Clock Monitor") is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. 4.6.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCONx or PIEx registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 10.0 "Interrupts"). 4.6.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 "Run Modes" and Section 4.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 28.2 "Watchdog Timer (WDT)"). Executing a SLEEP or CLRWDT instruction clears the WDT timer and postscaler, loses the currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifies the IRCF bits in the OSCCON register (if the internal oscillator block is the device clock source). 4.6.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. The two cases are: * When in PRI_IDLE mode, where the primary clock source is not stopped * When the primary clock source is not any of the LP, XT, HS or HSPLL modes In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally, does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval, TCSD, following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. DS39977C-page 78 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. 2. 3. 4. 5. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to `1'. Stop charging the capacitor by configuring RA0 as an input. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the WDTCON register. Configure Sleep mode. Enter Sleep mode. A series resistor, between RA0 and the external capacitor, provides overcurrent protection for the RA0/ CVREF/AN0/ULPWU pin and enables software calibration of the time-out (see Figure 4-9). FIGURE 4-9: ULTRA LOW-POWER WAKE-UP INITIALIZATION RA0/CVREF/AN0/ULPWU When the voltage on RA0 drops below VIL, the device wakes up and executes the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. The time-out is dependent on the discharge time of the RC circuit on RA0. When the ULPWU module wakes the device from Sleep mode, the ULPLVL bit (WDTCON<5>) is set. Software can check this bit upon wake-up to determine the wake-up source. See Example 4-1 for initializing the ULPWU module. A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired delay in Sleep. This technique compensates for the affects of temperature, voltage and component accuracy. The peripheral can also be configured as a simple programmable Low-Voltage Detect (LVD) or temperature sensor. Note: For more information, see AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879). EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for(i = 0; i < 10000; i++) Nop(); //***************************** //Stop Charging the capacitor //on RA0 //***************************** TRISAbits.TRISA0 = 1; //***************************** //Enable the Ultra Low Power //Wakeup module and allow //capacitor discharge //***************************** WDTCONbits.ULPEN = 1; WDTCONbits.ULPSINK = 1; //For Sleep OSCCONbits.IDLEN = 0; //Enter Sleep Mode // Sleep(); //for sleep, execution will //resume here 2011 Microchip Technology Inc. Preliminary DS39977C-page 79 PIC18F66K80 FAMILY TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source(5) Exit Delay Clock Ready Status Bits Power-Managed Mode LP, XT, HS HSPLL PRI_IDLE mode EC, RC HF-INTOSC(2) MF-INTOSC(2) LF-INTOSC SEC_IDLE mode RC_IDLE mode SOSC HF-INTOSC(2) MF-INTOSC(2) LF-INTOSC LP, XT, HS HSPLL Sleep mode EC, RC HF-INTOSC(2) MF-INTOSC(2) LF-INTOSC Note 1: 2: 3: 4: 5: OSTS TCSD(1) HFIOFS MFIOFS None TCSD(1) TCSD(1) TOST(3) TOST + trc(3) TCSD(1) HFIOFS TIOBST(4) MFIOFS None OSTS SOSCRUN HFIOFS MFIOFS None TCSD (Parameter 38, Table 31-11) is a required delay when waking from Sleep and all Idle modes, and runs concurrently with any other required delays (see Section 4.4 "Idle Modes"). Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz. TOST is the Oscillator Start-up Timer (Parameter 32, Table 31-11). TRC is the PLL Lock-out Timer (Parameter F12, Table 31-7); it is also designated as TPLL. Execution continues during TIOBST (Parameter 39, Table 31-11), the INTOSC stabilization period. The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) and FOSC (CONFIG1H<3:0>) bits. DS39977C-page 80 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 5.0 RESET The PIC18F66K80 family devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) i) Power-on Reset (POR) MCLR Reset during Normal Operation MCLR Reset during Power-Managed modes Watchdog Timer (WDT) Reset (during execution) Configuration Mismatch (CM) Reset Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.7 "Reset State of Registers". The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 10.0 "Interrupts". BOR is covered in Section 5.4 "Brown-out Reset (BOR)". This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. Stack Reset events are covered in Section 6.1.3.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 28.2 "Watchdog Timer (WDT)". FIGURE 5-1: Instruction Stack Pointer SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Stack Full/Underflow Reset External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset BOREN OST/PWRT OST OSC1 32 s INTOSC(1) 1024 Cycles R Q 10-Bit Ripple Counter Chip_Reset S POR Pulse PWRT 65.5 ms 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: 2: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. See Table 5-2 for time-out situations. 2011 Microchip Technology Inc. Preliminary DS39977C-page 81 PIC18F66K80 FAMILY REGISTER 5-1: R/W-0 IPEN bit 7 Legend: RCON: RESET CONTROL REGISTER R/W-1(1) SBOREN R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0(2) POR R/W-0 BOR bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and reads as `0'. CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred. 0 = A Configuration Mismatch Reset occurred. Must be set in software once the Reset occurs. RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 5.7 "Reset State of Registers" for additional information. Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset). DS39977C-page 82 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 5.2 Master Clear Reset (MCLR) FIGURE 5-2: The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F66K80 family devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.6 "PORTE, TRISE and LATE Registers" for more information. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD VDD D R R1 C MCLR PIC18FXX80 Note 1: 5.3 Power-on Reset (POR) 2: A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (Parameter D004). For a slow rise time, see Figure 5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any Power-on Reset. External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode, D, helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. R1 1 k will limit any current flowing into MCLR from external capacitor, C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 3: 2011 Microchip Technology Inc. Preliminary DS39977C-page 83 PIC18F66K80 FAMILY 5.4 * * * * Brown-out Reset (BOR) The PIC18F66K80 family has four BOR Power modes: High-Power BOR Medium Power BOR Low-Power BOR Zero-Power BOR Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: Each power mode is selected by the BORPWR<1:0> setting (CONFIG2L<6:5>). For low, medium and high-power BOR, the module monitors the VDD depending on the BORV<1:0> setting (CONFIG1L<3:2>). The typical current draw (IBOR) for zero, low and medium power BOR is 200 nA, 750 nA and 3 A, respectively. A BOR event re-arms the Power-on Reset. It also causes a Reset, depending on which of the trip levels has been set: 1.8V, 2V, 2.7V or 3V. BOR is enabled by BOREN<1:0> (CONFIG2L<2:1>) and the SBOREN bit (RCON<6>). The four BOR configurations are summarized in Table 5-1. In Zero-Power BOR (ZPBORMV), the module monitors the VDD voltage and re-arms the POR at about 2V. ZPBORMV does not cause a Reset, but re-arms the POR. The BOR accuracy varies with its power level. The lower the power setting, the less accurate the BOR trip levels are. Therefore, the high-power BOR has the highest accuracy and the low-power BOR has the lowest accuracy. The trip levels (BVDD, Parameter D005), current consumption (Section 31.2 "DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended)") and time required below BVDD (TBOR, Parameter 35) can all be found in Section 31.0 "Electrical Characteristics". Even when BOR is under software control, the Brown-out Reset voltage level is still set by the BORV<1:0> Configuration bits; it cannot be changed in software. 5.4.2 DETECTING BOR When Brown-out Reset is enabled, the BOR bit always resets to `0' on any Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any Power-on Reset event. IF BOR is `0' while POR is `1', it can be reliably assumed that a Brown-out Reset event has occurred. 5.4.3 DISABLING BOR IN SLEEP MODE When BOREN<1:0> = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. 5.4.1 SOFTWARE ENABLED BOR When BOREN<1:0> = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as `0'. TABLE 5-1: BOR CONFIGURATIONS Status of SBOREN (RCON<6>) BOR Operation BOR Configuration BOREN1 0 0 1 1 BOREN0 0 1 0 1 Unavailable Available Unavailable Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes; disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39977C-page 84 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Device Reset Timers The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread, single bit changes throughout the device and result in catastrophic failure. In PIC18FXXKXX Flash devices, the device Configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary Shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>) being set to `0'. This bit does not change for any other Reset event. A CM Reset behaves similarly to a Master Clear Reset, RESET instruction, WDT time-out or Stack Event Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. PIC18F66K80 family devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * PLL Lock Time-out 5.6.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F66K80 family devices is an 11-bit counter which uses the INTOSC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTOSC clock and will vary from chip-to-chip due to temperature and process variation. See DC Parameter 33 for details. The PWRT is enabled by clearing the PWRTEN Configuration bit. 2011 Microchip Technology Inc. Preliminary DS39977C-page 85 PIC18F66K80 FAMILY 5.6.2 OSCILLATOR START-UP TIMER (OST) 5.6.4 1. 2. TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: After the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (Parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset or on exit from most power-managed modes. 5.6.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 5-3 through 5-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up and Brown-out PWRTEN = 0 PWRTEN = 1 Exit from Power-Managed Mode Oscillator Configuration HSPLL HS, XT, LP EC, ECIO RC, RCIO INTIO1, INTIO2 Note 1: 2: 66 ms(1) + 1024 TOSC + 2 ms(2) 66 ms(1) + 1024 TOSC ms(1) ms(1) 66 66 1024 TOSC + 2 ms(2) 1024 TOSC -- -- -- 1024 TOSC + 2 ms(2) 1024 TOSC -- -- -- 66 ms(1) 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the PLL to lock. FIGURE 5-3: VDD MCLR INTERNAL POR TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST DS39977C-page 86 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 5-4: VDD MCLR INTERNAL POR TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 TPWRT TOST PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: VDD MCLR INTERNAL POR TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD MCLR 0V 1V INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2011 Microchip Technology Inc. Preliminary DS39977C-page 87 PIC18F66K80 FAMILY FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. Note: DS39977C-page 88 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on a Power-on Reset and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, CM, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 5-3. These bits are used in software to determine the nature of the Reset. Table 5-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter(1) SBOREN RCON Register CM 1 u 1 u u RI 1 0 1 u u TO 1 u 1 1 1 PD 1 u 1 u 0 STKPTR Register POR BOR STKFUL STKUNF 0 u u u u 0 u 0 u u 0 u u u u 0 u u u u Condition Power-on Reset RESET Instruction 0000h 0000h 0000h 0000h 0000h 1 u(2) u(2) u(2) u(2) Brown-out Reset MCLR Reset during Power-Managed Run modes MCLR Reset during Power-Managed Idle modes and Sleep mode WDT Time-out during Full Power or Power-Managed Run modes MCLR Reset during Full-Power execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT Time-out during Power-Managed Idle or Sleep modes Interrupt Exit from Power-Managed modes 0000h 0000h 0000h 0000h 0000h PC + 2 u(2) u(2) u(2) u(2) u(2) u(2) u u u u u u u u u u u u 0 u u u u 0 u u u u u 0 u u u u u u u u u u u u u u 1 u u u u u u 1 1 u PC + 2 u(2) u u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is `1' for POR and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is `0'. 2011 Microchip Technology Inc. Preliminary DS39977C-page 89 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11x0 0x00 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx ---- 0000 N/A MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11x0 0x00 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- 0000 N/A Wake-up via WDT or Interrupt ---0 uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu -u-u(1) uuuu uuuu(1) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- uuuu N/A TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 90 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset N/A N/A N/A N/A ---- xxxx xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0100 q000 -x-x x-xx 0-x0 -xx0 0111 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx -000 0000 0000 0qqq 0-00 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu 1111 1111 0100 00q0 -0-0 0-01 0-x0 -xx0 0111 qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu -000 0000 0000 0qqq 0-00 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 Wake-up via WDT or Interrupt N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuqu -u-u u-uu u-u0 -uu0 uuuu qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu u-uu uuuu xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON OSCCON2 WDTCON RCON(4) TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 ECCP1AS CCPR1H CCPR1L CCP1CON Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 91 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset 0000 0010 01x0 0-00 1111 -111 0000 -000 0000 -000 0000 0000 11-- ---xxxx xxxx xxxx xxxx 0000 0000 0000 0x00 0000 0000 0000 0000 xxxx xxxx 0000 0010 0000 000x 0000 0x00 1111 1111 0000 0000 01x0 0-00 0000 000x --11 111--x0 xxx0000 0000 1--- 111x 0--- 000x 0--- 000x 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 00-0 0001 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0010 01x0 0-00 1111 -111 0000 -000 0000 -000 0000 0000 11-- ---uuuu uuuu uuuu uuuu 0000 0000 0000 0x00 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x 0000 0x00 1111 1111 0000 0000 01x0 0-00 0000 000x --11 111--x0 xxx0000 0000 1--- 111x 0--- 000x 0--- 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 xx-x xxxx Wake-up via WDT or Interrupt uuuu uuuu uuuu u-uu uuuu -uuu uuuu -uuu uuuu -uuu uuuu uuuu uu-- ---uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu --uu uuu--uu uuuuuuu uuuu u--- uuuu u--- uuuu(1) u--- uuuu uuuu uuuu -uuu uuuu uuuu uuuu(1) -uuu uuuu uuuu uuuu -uuu uuuu -- TXSTA2 BAUDCON2 IPR4 PIR4 PIE4 CVRCON CMSTAT TMR3H TMR3L T3CON T3GCON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 T1GCON PR4 HLVDCON BAUDCON1 RCSTA2 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 PSTR1CON Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 92 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset 0000 0000 0-00 0000 ---1 1111 ---1 111 1111 1111 1111 -111 1111 1111 1111 1111 1111 1111 111- 1111 0000 0000 -111 1111 ---x xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx(5) -000 0000 0000 0000 ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx(5) xx-0 x000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 (5) MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0000 0-00 0000 ---1 1111 ---1 1111 1111 1111 1111 -111 1111 1111 1111 1111 1111 1111 111- 1111 0000 0000 -111 1111 ---x xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx(5) -000 0000 0000 0000 ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx(5) uu-0 u000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 (5) Wake-up via WDT or Interrupt uuuu uuuu u-uu uuuu ---u uuuu ---u uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu(5) uuuu uuuu -111 1111 ---u uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu(5) -uuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu(5) uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu OSCTUNE REFOCON CCPTMRS TRISG TRISF TRISE TRISD TRISC TRISB TRISA (5) PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 ODCON SLRCON LATG LATF LATE LATD LATC LATB LATA(5) T4CON TMR4 PORTG PORTF PORTE PORTD PORTC PORTB PORTA(5) EECON1 EECON2 SPBRGH1 SPBRGH2 SPBRG2 RCREG2 Legend: Note 1: 2: 3: 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 93 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset 0000 0000 1111 1111 0000 0000 0000 0000 ---- --00 0000 0000 0000 0000 0001 0000 0000 0000 0000 ---0 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 0000 0000 0001 1111 0001 1111 1111 1111 -111 1111 1111 1111 1111 ---0000 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0000 1111 1111 0000 0000 0000 0000 ---- --00 0000 0000 0000 0000 0001 0000 0000 0000 0000 ---0 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 0000 0000 0001 1111 0001 1111 1111 1111 -111 1111 1111 1111 1111 ---0000 0000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu ---uuuu uuuu TXREG2 IPR5 PIR5 PIE5 EEADRH EEADR EEDATA ECANCON COMSTAT CIOCON CANCON CANSTAT RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON RXB0CON CM1CON CM2CON ANCON0 ANCON1 WPUB IOCB PMD0 Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 94 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset 0000 0000 ---- 0000 0000 ---0 0-00 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 0000 ---0010 0--0 0--- xxxx 0xx- xxxx 0xx- xxxx 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0xxx xxxx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0000 ---- 0000 0000 ---0 0-00 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 0000 ---0010 0--0 0--- xxxx 0xx- xxxx 0xx- xxxx 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu Wake-up via WDT or Interrupt uuuu uuuu ---- uuuu uuuu ---u u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu ---uuuu u--u u--- uuuu uuu- uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx xxxx PMD1 PMD2 PADCFG1 CTMUCONH CTMUCONL CTMUICONH CCPR2H CCPR2L CCP2CON CCPR3H CCPR3L CCP3CON CCPR4H CCPR4L CCP4CON CCPR5H CCPR5L CCP5CON PSPCON MDCON MDSRC MDCARH MDCARL CANCON_RO0 CANSTAT_RO0 RXB1D7 RXB1D6 RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 95 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxxx x0xx xxxx xxxx 0000 0000 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0000 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -x-- xxxx xxxx xxxx xxxx xxxx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuuu u0uu uuuu uuuu 0000 0000 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0000 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -u-- uuuu uuuu uuuu uuuu uuuu Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -u-- uuuu uuuu uuuu uuuu uuuu RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON CANCON_RO1 CANSTAT_RO1 TXB0D7 TXB0D6 TXB0D5 TXB0D4 TXB0D3 TXB0D2 TXB0D1 TXB0D0 TXB0DLC TXB0EIDL TXB0EIDH TXB0SIDL TXB0SIDH TXB0CON CANCON_RO2 CANSTAT_RO2 TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 96 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset xxxx x-xx xxxx xxxx 0000 0000 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -x-- xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0-00 xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets uuuu u-uu uuuu uuuu 0000 0000 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -u-- uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu 0000 0-00 uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu Wake-up via WDT or Interrupt uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -u-- uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu TXB1SIDL TXB1SIDH TXB1CON CANCON_RO3 CANSTAT_RO3 TXB2D7 TXB2D6 TXB2D5 TXB2D4 TXB2D3 TXB2D2 TXB2D1 TXB2D0 TXB2DLC TXB2EIDL TXB2EIDH TXB2SIDL TXB2SIDH TXB2CON RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EIDL RXF5EIDH RXF5SIDL RXF5SIDH RXF4EIDL RXF4EIDH RXF4SIDL Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 97 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 1000 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 1000 0000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RXF4SIDH RXF3EIDL RXF3EIDH RXF3SIDL RXF3SIDH RXF2EIDL RXF2EIDH RXF2SIDL RXF2SIDH RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDL RXF0EIDH RXF0SIDL RXF0SIDH CANCON_RO4 CANSTAT_RO4 B5D7 B5D6 B5D5 B5D4 B5D3 B5D2 B5D1 B5D0 B5DLC B5EIDL B5EIDH B5SIDL B5SIDH B5CON CANCON_RO5 Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 98 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 1000 0000 xxxx xxxx xxxx xxxx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 1000 0000 uuuu uuuu uuuu uuuu Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu CANSTAT_RO5 B4D7 B4D6 B4D5 B4D4 B4D3 B4D2 B4D1 B4D0 B4DLC B4EIDL B4EIDH B4SIDL B4SIDH B4CON CANCON_RO6 CANSTAT_RO6 B3D7 B3D6 B3D5 B3D4 B3D3 B3D2 B3D1 B3D0 B3DLC B3EIDL B3EIDH B3SIDL B3SIDH B3CON CANCON_RO7 B2D7 B2D6 Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 99 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 1000 0000 1000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 1000 0000 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu B2D5 B2D4 B2D3 B2D2 B2D1 B2D0 B2DLC B2EIDL B2EIDH B2SIDL B2SIDH B2CON CANCON_RO8 B1D7 B1D6 B1D5 B1D4 B1D3 B1D2 B1D1 B1D0 B1DLC B1EIDL B1EIDH B1SIDL B1SIDH B1CON CANCON_RO9 CANSTAT_RO B0D7 B0D6 B0D5 B0D4 B0D3 Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 100 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 ---0 00-0000 0000 0000 00-0000 0000 0000 0000 0000 0000 0101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0000 0000 ---0 0000 xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 0000 0000 ---u uu-0000 0000 0000 00-0000 0000 0000 0000 0000 0000 0101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0000 0000 ---0 0000 uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uu-uuuu uuuu uuuu uu-uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu B0D2 B0D1 B0D0 B0DLC B0EIDL B0EIDH B0SIDL B0SIDH B0CON TXBIE BIE0 BSEL0 MSEL3 MSEL2 MSEL1 MSEL0 RXFBCON7 RXFBCON6 RXFBCON5 RXFBCON4 RXFBCON3 RXFBCON2 RXFBCON1 RXFBCON0 SDFLC RXF15EIDL RXF15EIDH RXF15SIDL RXF15SIDH RXF14EIDL RXF14EIDH RXF14SIDL RXF14SIDH RXF13EIDL Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 101 PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxx- x-xx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0000 0000 0000 00-- -000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuu- u-uu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu 0000 0000 0000 0000 00-- -000 Wake-up via WDT or Interrupt uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuu- u-uu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu -- RXF13EIDH RXF13SIDL RXF13SIDH RXF12EIDL RXF12EIDH RXF12SIDL RXF12SIDH RXF11EIDL RXF11EIDH RXF11SIDL RXF11SIDH RXF10EIDL RXF10EIDH RXF10SIDL RXF10SIDH RXF9EIDL RXF9EIDH RXF9SIDL RXF9SIDH RXF8EIDL RXF8EIDH RXF8SIDL RXF8SIDH RXF7EIDL RXF7EIDH RXF7SIDL RXF7SIDH RXF6EIDL RXF6EIDH RXF6SIDL RXF6SIDH RXFCON0 RXFCON1 BRGCON3 Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39977C-page 102 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset 0000 0000 0000 0000 0000 0000 0000 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0000 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BRGCON2 BRGCON1 TXERRCNT RXERRCNT Legend: Note 1: 2: 3: PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F2XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F4XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 PIC18F6XK80 4: 5: 6: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 5-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 103 PIC18F66K80 FAMILY NOTES: DS39977C-page 104 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.0 MEMORY ORGANIZATION PIC18F66K80 family devices have these types of memory: * Program Memory * Data RAM * Data EEPROM As Harvard architecture devices, the data and program memories use separate busses. This enables concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 "Flash Program Memory". The data EEPROM is discussed separately in Section 8.0 "Data EEPROM Memory". FIGURE 6-1: MEMORY MAPS FOR PIC18F66K80 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1 Stack Level 31 PIC18FX5K80 On-Chip Memory PIC18FX6K80 On-Chip Memory 000000h 007FFFh 00FFFFh Unimplemented Read as `0' Unimplemented Read as `0' 1FFFFFh Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2011 Microchip Technology Inc. Preliminary DS39977C-page 105 User Memory Space PIC18F66K80 FAMILY 6.1 Program Memory Organization FIGURE 6-2: PIC18 microcontrollers implement a 21-bit program counter that is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The entire PIC18F66K80 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (16,384 single-word instructions) to 64 Kbytes (32,768 single-word instructions). * PIC18F25K80, PIC18F45K80 and PIC18F65K80 - 32 Kbytes of Flash memory, storing up to 16,384 single-word instructions * PIC18F26K80, PIC18F46K80 and PIC18F66K80 - 64 Kbytes of Flash memory, storing up to 32,768 single-word instructions The program memory maps for individual family members are shown in Figure 6-1. HARD VECTOR FOR PIC18F66K80 FAMILY DEVICES Reset Vector 0000h 0008h 0018h High-Priority Interrupt Vector Low-Priority Interrupt Vector On-Chip Program Memory 6.1.1 HARD MEMORY VECTORS Read `0' All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets. It is located at 0000h. PIC18 devices also have two interrupt vector addresses for handling high-priority and low-priority interrupts. The high-priority interrupt vector is located at 0008h and the low-priority interrupt vector is at 0018h. The locations of these vectors are shown, in relation to the program memory map, in Figure 6-2. 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39977C-page 106 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 6.1.5.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit (LSb) of PCL is fixed to a value of `0'. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed. 6.1.3.1 Top-of-Stack Access 6.1.3 RETURN ADDRESS STACK The return address stack enables execution of any combination of up to 31 program calls and interrupts. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. The value is also pulled off the stack on ADDULNK and SUBULNK instructions if the extended instruction set is enabled. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. Only the top of the return address stack is readable and writable. A set of three registers, TOSU:TOSH:TOSL, holds the contents of the stack location pointed to by the STKPTR register (Figure 6-3). This allows users to implement a software stack, if necessary. After a CALL, RCALL or interrupt (or ADDULNK and SUBULNK instructions, if the extended instruction set is enabled), the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. While accessing the stack, users must disable the global interrupt enable bits to prevent inadvertent stack corruption. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack<20:0> Top-of-Stack Registers 11111 11110 11101 Stack Pointer TOSU 00h TOSH 1Ah TOSL 34h STKPTR<4:0> 00010 Top-of-Stack 001A34h 000D58h 00011 00010 00001 00000 2011 Microchip Technology Inc. Preliminary DS39977C-page 107 PIC18F66K80 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off of the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. What happens when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (For a description of the device Configuration bits, see Section 28.1 "Configuration Bits".) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. 6.1.3.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off of the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. REGISTER 6-1: R/C-0 STKFUL(1) bit 7 Legend: STKPTR: STACK POINTER REGISTER R/C-0 U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown STKUNF(1) R = Readable bit -n = Value at POR bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack has become full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP<4:0>: Stack Pointer Location bits bit 6 bit 5 bit 4-0 Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS39977C-page 108 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.1.3.4 Stack Full and Underflow Resets 6.1.5 Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit (CONFIG4L<0>). When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 6.1.5.1 Computed GOTO 6.1.4 FAST REGISTER STACK A Fast Register Stack is provided for the STATUS, WREG and BSR registers to provide a "fast return" option for interrupts. This stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the Stack registers. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. Example 6-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value, `nn', to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of two (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 6-2: MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh ORG TABLE 6.1.5.2 Table Reads EXAMPLE 6-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word while programming. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program memory one byte at a time. The table read operation is discussed further in Section 7.1 "Table Reads and Table Writes". SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2011 Microchip Technology Inc. Preliminary DS39977C-page 109 PIC18F66K80 FAMILY 6.2 6.2.1 PIC18 Instruction Cycle CLOCKING SCHEME 6.2.2 INSTRUCTION FLOW/PIPELINING The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1, with the instruction fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 6-4. An "Instruction Cycle" consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction (such as GOTO) causes the program counter to change, two cycles are required to complete the instruction. (See Example 6-3.) A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle, Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode) CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Internal Phase Clock PC PC + 2 PC + 4 Execute INST (PC - 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1 Fetch 1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. DS39977C-page 110 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two or four bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSB will always read `0' (see Section 6.1.2 "Program Counter"). Figure 6-5 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1> which accesses the desired byte address in program memory. Instruction #2 in Figure 6-5 shows how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. For more details on the instruction set, see Section 29.0 "Instruction Set Summary". FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 Program Memory Byte Locations LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h Instruction 1: Instruction 2: Instruction 3: MOVLW GOTO MOVFF 055h 0006h 123h, 456h 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h 6.2.4 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four, two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits (MSbs). The other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence, immediately after the first word, the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 shows how this works. Note: For information on two-word instructions in the extended instruction set, see Section 6.5 "Program Memory and the Extended Instruction Set". EXAMPLE 6-4: CASE 1: Object Code TWO-WORD INSTRUCTIONS Source Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code TSTFSZ MOVFF ADDWF Source Code REG1 ; is RAM location 0? ; Execute this word as a NOP REG1, REG2 ; No, skip this word REG3 ; continue code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; 2nd word of instruction REG1, REG2 ; Yes, execute this word REG3 ; continue code 2011 Microchip Technology Inc. Preliminary DS39977C-page 111 PIC18F66K80 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 "Data Memory and the Extended Instruction Set" for more information. 6.3.1 BANK SELECT REGISTER The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory. The memory space is divided into 16 banks that contain 256 bytes each. Figure 6-6 and Figure 6-7 show the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this section. To ensure that commonly used registers (select SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to select SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register. For details on the Access RAM, see Section 6.3.2 "Access Bank". Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an eight-bit, low-order address and a four-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the four Most Significant bits of a location's address. The instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused and always read as `0', and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 6-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an eight-bit address of F9h while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39977C-page 112 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 6-6: BSR<3:0> 00h = 0000 Bank 0 FFh 00h Bank 1 FFh 00h Bank 2 FFh 00h Bank 3 FFh 00h Bank 4 FFh 00h Bank 5 FFh 00h Bank 6 FFh 00h Bank 7 FFh 00h Bank 8 FFh 00h Bank 9 FFh 00h Bank 10 Bank 11 FFh 00h FFh 00h FFh 00h FFh 00h Bank 14 Bank 15 FFh 00h FFh Note 1: DATA MEMORY MAP FOR PIC18FX5K80 AND PIC18FX6K80 DEVICES Data Memory Map Access RAM GPR GPR = 0001 000h 05Fh 060h 0FFh 100h 1FFh 200h When a = 0: The BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When a = 1: = 0010 GPR 2FFh 300h GPR 3FFh 400h 4FFh 500h GPR 5FFh 600h GPR 6FFh 700h GPR 7FFh 800h GPR 8FFh 900h GPR 9FFh A00h GPR GPR AFFh B00h BFFh C00h CFFh D00h DFFh E00h GPR(1) GPR(1) SFR EFFh F00h F5Fh F60h FFFh = 0011 = 0100 The BSR specifies the bank used by the instruction. GPR = 0101 = 0110 = 0111 Access Bank = 1000 5Fh Access RAM High 60h (SFRs) FFh Access RAM Low 00h = 1001 = 1010 = 1011 = 1100 Bank 12 GPR GPR = 1101 Bank 13 = 1110 = 1111 Addresses, E41h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address, or load the proper BSR value, to access these registers. 2011 Microchip Technology Inc. Preliminary DS39977C-page 113 PIC18F66K80 FAMILY FIGURE 6-7: 7 0 0 0 USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 0 0 0 1 0 0 000h 100h Bank 1 200h 300h Bank 2 Data Memory Bank 0 00h FFh 00h FFh 00h FFh 00h 7 1 1 From Opcode(2) 1 1 1 1 1 1 1 1 0 1 1 Bank Select(2) Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK While the use of the BSR, with an embedded 8-bit address, allows users to address the entire range of data memory, it also means that the user must ensure that the correct bank is selected. If not, data may be read from, or written to, the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Bank 15. The lower half is known as the "Access RAM" and is composed of GPRs. The upper half is where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an eight-bit address (Figure 6-6). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', however, the instruction is forced to use the Access Bank address map. In that case, the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 6.6.3 "Mapping the Access Bank in Indexed Literal Offset Mode". 6.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. DS39977C-page 114 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy all of Bank 15 (F00h to FFFh) and the top part of Bank 14 (EF4h to EFFh). A list of these registers is given in Table 6-1 and Table 6-2. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's. TABLE 6-1: Addr. FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY Addr. FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1) POSTINC0(1) POSTDEC0(1) PREINC0(1) PLUSW0(1) FSR0H FSR0L WREG INDF1(1) POSTINC1(1) POSTDEC1(1) PREINC1(1) PLUSW1(1) FSR1H FSR1L BSR Name INDF2(1) POSTINC2 PREINC2 PLUSW2 FSR2L STATUS TMR0H TMR0L T0CON --(2) OSCCON OSCCON2 WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 FSR2H (1) (1) Addr. FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h Name ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON TXSTA2 BAUDCON2 IPR4 PIR4 PIE4 CVRCON CMSTAT TMR3H TMR3L T3CON T3GCON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 T1GCON PR4 HLVDCON BAUDCON1 RCSTA2 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 Addr. F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h Name IPR1 PIR1 PIE1 PSTR1CON OSCTUNE REFOCON CCPTMRS TRISG(3) TRISF(3) TRISE(4) TRISD (4) Addr. F7Fh F7Eh Name EECON1 EECON2 Addr. Name F5Fh CM1CON(5) F5Eh CM2CON(5) F5Dh F5Ch F5Bh F5Ah F59h F58h F57h ANCON0(5) ANCON1(5) WPUB(5) IOCB(5) PMD0(5) PMD1(5) PMD2(5) POSTDEC2 F7Dh SPBRGH1 F7Ch SPBRGH2 F7Bh F7Ah F79h F78h F77h F76h F75h F74h F73h SPBRG2 RCREG2 TXREG2 IPR5 PIR5 PIE5 EEADRH EEADR EEDATA (1) (1) F56h PADCFG1(5) F55h CTMUCONH(5) F54h CTMUCONL(5) TRISC TRISB TRISA ODCON SLRCON LATG(3) LATF(3) LATE(4) LATD(4) LATC LATB LATA T4CON TMR4 PORTG(3) PORTF(3) PORTE PORTD(4) PORTC PORTB PORTA F72h ECANCON F71h COMSTAT F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h CIOCON CANCON CANSTAT RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC F64h RXB0EIDL F63h RXB0EIDH F62h RXB0SIDL F61h RXB0SIDH F60h RXB0CON F53h CTMUICONH(5) F52h CCPR2H(5) F51h CCPR2L(5) F50h CCP2CON(4,5) F4Fh CCPR3H(4,5) F4Eh CCPR3L(4,5) F4Dh CCP3CON(5) F4Ch CCPR4H(5) F4Bh CCPR4L(5) F4Ah CCP4CON(5) F49h CCPR5H(5) F48h CCPR5L(5) F47h CCP5CON(5) F46h PSPCON(4,5) F45h MDCON(3,5) F44h MDSRC(3,5) F43h MDCARH(3,5) F42h MDCARL(3,5) F41h --(2) F40h --(2) Note 1: 2: 3: 4: 5: This is not a physical register. Unimplemented registers are read as `0'. This register is only available on devices with 64 pins. This register is not available on devices with 28-pins. Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value. 2011 Microchip Technology Inc. Preliminary DS39977C-page 115 PIC18F66K80 FAMILY TABLE 6-1: Addr. SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY (CONTINUED) Addr. Name Name Addr. Name Addr. Name Addr. E7Fh E7Eh E7Dh E7Ch E7Bh E7Ah E79h Name TXBIE(5) BIE0(5) BSEL0(5) MSEL3(5) MSEL2(5) MSEL1(5) MSEL0 (5) (5) Addr. Name F3Fh CANCON_RO0(5) F3Eh CANSTAT_RO0(5) F3Dh F3Ch F3Bh F3Ah F39h F38h F37h F36h F35h F34h F33h F32h F31h F30h F30h RXB1D7(5) RXB1D6(5) RXB1D5(5) RXB1D4(5) RXB1D3 RXB1D2 RXB1D1 RXB1D0 (5) (5) (5) (5) F0Fh CANCON_RO3(5) EDFh CANCON_RO4(5) F0Eh CANSTAT_RO3(5) EDEh CANSTAT_RO4(5) F0Dh F0Ch F0Bh F0Ah F09h F08h F07h F06h F05h F04h F03h F02h F01h F00h EFFh EFEh EFDh EFCh EFBh EFAh EF9h EF8h EF7h EF6h EF5h EF4h EF3h EF2h EF1h EF0h EEFh TXB2D7(5) TXB2D6(5) TXB2D5(5) TXB2D4(5) TXB2D3 TXB2D2 TXB2D1 TXB2D0 (5) (5) (5) (5) EAFh CANCON_RO7(5) EAEh CANSTAT_RO7(5) EADh EACh EABh EAAh EA9h EA8h EA7h EA6h EA5h EA4h EA3h EA2h EA1h EA0h B2D7(5) B2D6(5) B2D5(5) B2D4(5) B2D3 B2D2 B2D1 B2D0 (5) (5) (5) (5) E4Fh RXF7EIDL(5) E4Eh RXF7EIDH(5) E4Dh RXF7SIDL(5) E4Ch RXF7SIDH(5) E4Bh RXF6EIDL(5) E4Ah RXF6EIDH(5) E49h RXF6SIDL(5) E48h RXF6SIDH(5) E47h RXFCON0(5) E46h RXFCON1(5) E45h BRGCON3(5) E44h BRGCON2(5) E43h BRGCON1(5) E42h TXERRCNT(5) E41h RXERRCNT(5) (5) (5) EDDh EDCh EDBh EDAh ED9h ED8h ED7h ED6h ED5h ED4h ED3h ED2h ED1h ED0h B5D7(5) B5D6(5) B5D5(5) B5D4(5) B5D3 B5D2 B5D1 B5D0 (5) (5) (5) (5) E78h RXFBCON7 E77h RXFBCON6 E76h RXFBCON5 RXB1DLC(5) RXB1EIDL(5) RXB1EIDH(5) RXB1SIDL(5) RXB1SIDH(5) RXB1CON(5) RXB1CON(5) (5) TXB2DLC(5) TXB2EIDL(5) TXB2EIDH(5) TXB2SIDL(5) TXB2SIDH(5) TXB2CON(5) RXM1EIDL(5) RXM1EIDH(5) RXM1SIDL (5) (5) B5DLC(5) B5EIDL(5) B5EIDH(5) B5SIDL(5) B5SIDH(5) B5CON(5) B2DLC(5) B2EIDL(5) B2EIDH(5) B2SIDL(5) B2SIDH(5) B2CON(5) E75h RXFBCON4(5) E74h RXFBCON3(5) E73h RXFBCON2(5) E72h RXFBCON1(5) E71h E70h RXFBCON0(5) SDFLC(5) ECFh CANCON_RO5(5) ECEh CANSTAT_RO5(5) ECDh ECCh ECBh ECAh EC9h EC8h EC7h EC6h EC5h EC4h EC3h EC2h EC1h EC0h B4D7 B4D6 (5) (5) E9Fh CANCON_RO8(5) E9Eh CANSTAT_RO8(5) E9Dh E9Ch E9Bh E9Ah E99h E98h E97h E96h E95h E94h E93h E92h E91h E90h E90h B1D7 B1D6 (5) (5) E6Fh RXF15EIDL(5) E6Eh RXF15EIDH(5) E6Dh RXF15SIDL(5) E6Ch RXF15SIDH(5) E6Bh RXF14EIDL(5) E6Ah RXF14EIDH(5) E69h RXF14SIDL(5) E68h RXF14SIDH(5) E67h RXF13EIDL(5) E66h RXF13EIDH(5) E65h RXF13SIDL(5) E64h RXF13SIDH(5) E63h RXF12EIDL(5) E62h RXF12EIDH(5) E61h RXF12SIDL(5) E60h RXF12SIDH(5) E5Fh RXF11EIDL(5) E5Eh RXF11EIDH(5) E5Dh RXF11SIDL(5) E5Ch RXF11SIDH(5) E5Bh RXF10EIDL(5) E5Ah RXF10EIDH(5) E59h RXF10SIDL(5) E58h RXF10SIDH(5) E57h RXF9EIDL(5) E56h RXF9EIDH(5) E55h RXF9SIDL(5) E54h RXF9SIDH(5) E53h RXF8EIDL(5) E52h RXF8EIDH(5) E51h RXF8SIDL(5) E50h RXF8SIDH(5) F2Fh CANCON_RO1(5) F2Eh CANSTAT_RO1 F2Dh F2Ch F2Bh F2Ah F29h F28h F27h F26h F25h F24h F23h F22h F21h F20h TXB0D7 (5) RXM1SIDH TXB0D6(5) TXB0D5(5) TXB0D4(5) TXB0D3(5) TXB0D2(5) TXB0D1 (5) RXM0EIDL(5) RXM0EIDH(5) RXM0SIDL(5) RXM0SIDH(5) RXF5EIDL(5) RXF5EIDH RXF5SIDH RXF4EIDL (5) B4D5(5) B4D4(5) B4D3(5) B4D2(5) B4D1(5) B4D0 (5) B1D5(5) B1D4(5) B1D3(5) B1D2(5) B1D1(5) B1D0 (5) TXB0D0(5) TXB0DLC (5) (5) RXF5SIDL(5) (5) (5) B4DLC(5) B4EIDL (5) (5) B1DLC(5) B1EIDL (5) (5) TXB0EIDL B4EIDH B1EIDH TXB0EIDH(5) TXB0SIDL(5) TXB0SIDH(5) TXB0CON(5) (5) RXF4EIDH(5) RXF4SIDL(5) RXF4SIDH(5) RXF3EIDL(5) RXF3EIDH(5) RXF3SIDL RXF2EIDL (5) B4SIDL(5) B4SIDH(5) B4CON(5) B1SIDL(5) B1SIDH(5) B1CON(5) B1CON(5) (5) EBFh CANCON_RO6(5) EBEh CANSTAT_RO6(5) EBDh EBCh EBBh EBAh EB9h EB8h EB7h EB6h EB5h EB4h EB3h EB2h EB1h EB0h B3D7 (5) F1Fh CANCON_RO2(5) EEEh F1Eh CANSTAT_RO2 F1Dh F1Ch F1Bh F1Ah F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h Note 1: 2: 3: 4: 5: TXB1D7(5) TXB1D6 (5) (5) E8Fh CANCON_RO9(5) E8Eh CANSTAT_RO9 E8Dh E8Ch E8Bh E8Ah E89h E88h E87h E86h E85h E84h E83h E82h E81h E80h B0D7(5) B0D6 (5) (5) EEDh EECh EEBh EEAh EE9h EE8h EE7h EE6h EE5h EE4h EE3h EE2h EE1h EE0h RXF3SIDH(5) (5) (5) B3D6(5) B3D5 B3D4 (5) (5) TXB1D5 RXF2EIDH B0D5 TXB1D4(5) TXB1D3(5) TXB1D2(5) TXB1D1(5) TXB1D0(5) TXB1DLC(5) TXB1EIDL(5) TXB1EIDH(5) TXB1SIDL (5) RXF2SIDL(5) RXF2SIDH(5) RXF1EIDL(5) RXF1EIDH(5) RXF1SIDL(5) RXF1SIDH(5) RXF0EIDL(5) RXF0EIDH(5) RXF0SIDL (5) B3D3(5) B3D2(5) B3D1(5) B3D0(5) B3DLC(5) B3EIDL(5) B3EIDH(5) B3SIDL(5) B3SIDH (5) B0D4(5) B0D3(5) B0D2(5) B0D1(5) B0D0(5) B0DLC(5) B0EIDL(5) B0EIDH(5) B0SIDL (5) TXB1SIDH(5) TXB1CON(5) RXF0SIDH(5) B3CON(5) B0SIDH(5) B0CON(5) This is not a physical register. Unimplemented registers are read as `0'. This register is only available on devices with 64 pins. This register is not available on devices with 28-pins. Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value. DS39977C-page 116 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 6-2: Addr. FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON Unimplemented OSCCON OSCCON2 WDTCON RCON IDLEN -- REGSLP IPEN IRCF2 SOSCRUN -- SBOREN IRCF1 -- ULPLVL CM IRCF0 SOSCDRV SRETEN RI OSTS SOSCGO -- TO HFIOFS -- ULPEN PD SCS1 MFIOFS ULPSINK POR SCS0 MFIOSEL SWDTEN BOR PIC18F66K80 FAMILY REGISTER FILE SUMMARY Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR on page 90 90 90 SP4 SP3 SP2 SP1 SP0 90 90 90 90 Bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 90 90 90 90 90 90 TMR0IE INTEDG1 INT3IE INT0IE INTEDG2 INT2IE RBIE INTEDG3 INT1IE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 Bank Select Register 90 90 91 91 91 91 91 91 OV Z DC C 91 91 91 T0CS T0SE PSA T0PS2 T0PS1 T0PS0 91 -- 91 91 91 91 Holding Register for PC<20:16> Top-of-Stack Upper Byte (TOS<20:16>) Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- Bit 21 Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W -- Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 1 High Byte Indirect Data Memory Address Pointer 1 Low Byte Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W -- -- -- -- -- -- -- N Indirect Data Memory Address Pointer 2 High Byte Indirect Data Memory Address Pointer 2 Low Byte Timer0 Register High Byte Timer0 Register Low Byte TMR0ON T08BIT -- -- -- Indirect Data Memory Address Pointer 0 High Byte Indirect Data Memory Address Pointer 0 Low Byte 2011 Microchip Technology Inc. Preliminary DS39977C-page 117 PIC18F66K80 FAMILY TABLE 6-2: Addr. FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h File Name TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON TXSTA2 BAUDCON2 IPR4 PIR4 PIE4 CVRCON CMSTAT TMR3H TMR3L T3CON T3GCON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 T1GCON PR4 HLVDCON BAUDCON1 RCSTA2 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR on page 91 91 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON 91 91 91 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 91 91 91 MSK0 BF SSPM0 SEN 91 91 91 91 91 91 CHS3 VCFG1 ACQT2 ECCP1AS1 P1DC5 CHS2 VCFG0 ACQT1 ECCP1AS0 P1DC4 CHS1 VNCFG ACQT0 PSS1AC1 P1DC3 CHS0 CHSN2 ADCS2 PSS1AC0 P1DC2 GO/DONE CHSN1 ADCS1 PSS1BD1 P1DC1 ADON CHSN0 ADCS0 PSS1BD0 P1DC0 91 91 91 91 91 91 91 DC1B0 SYNC TXCKP CMP1IP CMP1IF CMP1IE CVR4 -- CCP1M3 SENDB BRG16 -- -- -- CVR3 -- CCP1M2 BRGH -- CCP5IP CCP5IF CCP5IE CVR2 -- CCP1M1 TRMT WUE CCP4IP CCP4IF CCP4IE CVR1 -- CCP1M0 TX9D ABDEN CCP3IP CCP3IF CCP3IE CVR0 -- 91 92 92 92 92 92 92 92 92 92 T3CKPS1 T3GTM T3CKPS0 T3GSPM SOSCEN T3GGO/ T3DONE T3SYNC T3GVAL RD16 T3GSS1 TMR3ON T3GSS0 92 92 92 92 92 TXEN SREN T1GTM SYNC CREN T1GSPM SENDB ADDEN T1GGO/ T1DONE HLVDL3 BRG16 ADDEN CTMUIP CTMUIF CTMUIE BCLIP BCLIF BCLIE BRGH FERR T1GVAL TRMT OERR T1GSS1 TX9D RX9D T1GSS0 92 92 92 92 IRVST RXDTP SREN RC2IP RC2IF RC2IE -- -- -- HLVDEN TXCKP CREN TX2IP TX2IF TX2IE -- -- -- HLVDL2 -- FERR CCP2IP CCP2IF CCP2IE HLVDIP HLVDIF HLVDIE HLVDL1 WUE OERR CCP1IP CCP1IF CCP1IE TMR3IP TMR3IF TMR3IE HLVDL0 ABDEN RX9D -- -- -- TMR3GIP TMR3GIF TMR3GIE 92 92 92 92 92 92 92 92 92 MSK4 P CKP ACKEN MSK3 S SSPM3 RCEN MSK2 R/W SSPM2 PEN MSK1 UA SSPM1 RSEN Timer1 Register High Byte Timer1 Register Low Bytes TMR1CS1 TMR1CS0 Timer2 Register Timer2 Period Register -- T2OUTPS3 MSSP Receive Buffer/Transmit Register MSSP Address Register (I2CTM Slave Mode), MSSP Baud Rate Reload Register (I2C Master Mode) MSK7 SMP WCOL GCEN MSK6 CKE SSPOV ACKSTAT MSK5 D/A SSPEN ACKDT A/D Result Register High Byte A/D Result Register Low Byte -- TRIGSEL1 ADFM P1RSEN CHS4 TRIGSEL0 -- P1DC6 ECCP1ASE ECCP1AS2 Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte P1M1 CSRC ABDOVF TMR4IP TMR4IF TMR4IE CVREN CMP2OUT P1M0 TX9 RCIDL EEIP EEIF EEIE CVROE CMP1OUT DC1B1 TXEN RXDTP CMP2IP CMP2IF CMP2IE CVRSS -- Timer3 Register High Byte Timer3 Register Low Bytes TMR3CS1 TMR3GE TMR3CS0 T3GPOL EUSART1 Baud Rate Generator Register Low Byte EUSART1 Receive Register EUSART1 Transmit Register CSRC SPEN TMR1GE TX9 RX9 T1GPOL Timer4 Period Register VDIRMAG ABDOVF SPEN -- -- -- OSCFIP OSCFIF OSCFIE BGVST RCIDL RX9 -- -- -- -- -- -- DS39977C-page 118 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 6-2: Addr. F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76H F75h F74h F73h F72h F71h F70h F6Fh F6Eh File Name IPR1 PIR1 PIE1 PSTR1CON OSCTUNE REFOCON CCPTMRS TRISG TRISF TRISE TRISD TRISC TRISB TRISA ODCON SLRCON LATG LATF LATE LATD LATC LATB LATA T4CON TMR4 PORTG PORTF PORTE PORTD PORTC PORTB PORTA EECON1 EECON2 SPBRGH1 SPBRGH2 SPBRG2 RCREG2 TXREG2 IPR5 PIR5 PIE5 EEADRH EEADR EEDATA ECANCON COMSTAT CIOCON CANCON CANSTAT PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 PSPIP PSPIF PSPIE CMPL1 INTSRC ROON -- -- TRISF7 TRISE7 TRISD7 TRISC7 TRISB7 TRISA7 SSPOD -- -- LATF7 LATE7 LATD7 LATC7 LATB7 LATA7 -- -- RF7 RE7 RD7 RC7 RB7 RA7 EEPGD Timer4 Register -- RF6 RE6 RD6 RC6 RB6 RA6 CFGS -- RF5 RE5 RD5 RC5 RB5 RA5 -- RG4 RF4 RE4 RD4 RC4 RB4 -- FREE RG3 RF3 RE3 RD3 RC3 RB3 RA3 WRERR RG2 RF2 RE2 RD2 RC2 RB2 RA2 WREN RG1 RF1 RE1 RD1 RC1 RB1 RA1 WR RG0 RF0 RE0 RD0 RC0 RB0 RA0 RD Bit 6 ADIP ADIF ADIE CMPL0 PLLEN -- -- -- TRISF6 TRISE6 TRISD6 TRISC6 TRISB6 TRISA6 CCP5OD SLRG -- LATF6 LATE6 LATD6 LATC6 LATB6 LATA6 T4OUTPS3 Bit 5 RC1IP RC1IF RC1IE -- TUN5 ROSSLP -- -- TRISF5 TRISE5 TRISD5 TRISC5 TRISB5 TRISA5 CCP4OD SLRF -- LATF5 LATE5 LATD5 LATC5 LATB5 LATA5 T4OUTPS2 Bit 4 TX1IP TX1IF TX1IE STRSYNC TUN4 ROSEL C5TSEL TRISG4 TRISF4 TRISE4 TRISD4 TRISC4 TRISB4 -- CCP3OD SLRE LATG4 LATF4 LATE4 LATD4 LATC4 LATB4 -- T4OUTPS1 Bit 3 SSPIP SSPIF SSPIE STRD TUN3 RODIV3 C4TSEL TRISG3 TRISF3 -- TRISD3 TRISC3 TRISB3 TRISA3 CCP2OD SLRD LATG3 -- -- LATD3 LATC3 LATB3 LATA3 T4OUTPS0 Bit 2 TMR1GIP TMR1GIF TMR1GIE STRC TUN2 RODIV2 C3TSEL TRISG2 TRISF2 TRISE2 TRISD2 TRISC2 TRISB2 TRISA2 CCP1OD SLRC LATG2 LATF2 LATE2 LATD2 LATC2 LATB2 LATA2 TMR4ON Bit 1 TMR2IP TMR2IF TMR2IE STRB TUN1 RODIV1 C2TSEL TRISG1 TRISF1 TRISE1 TRISD1 TRISC1 TRISB1 TRISA1 U2OD SLRB LATG1 LATF1 LATE1 LATD1 LATC1 LATB1 LATA1 T4CKPS1 Bit 0 TMR1IP TMR1IF TMR1IE STRA TUN0 RODIV0 C1TSEL TRISG0 TRISF0 TRISE0 TRISD0 TRISC0 TRISB0 TRISA0 U1OD SLRA LATG0 LATF0 LATE0 LATD0 LATC0 LATB0 LATA0 T4CKPS0 Value on POR, BOR on page 92 92 92 92 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 94 ERRIP ERRIF ERRIE TX2BIP TXB2IF TX2BIE TXB1IP TXB1IF TXB1IE TXB0IP TXB0IF TXB0IE RXB1IP RXB1IF RXB1IE RXB0IP RXB0IF RXB0IE 94 94 94 94 94 94 FIFOWM TXBO ENDRHI REQOP0 OPMODE0 EWIN4 TXBP CANCAP ABAT --/ EICOD4 EWIN3 RXBP -- WIN2/FP3 ICODE2/ EICODE3 EWIN2 TXWARN -- WIN1/FP2 ICODE1/ EICODE2 EWIN1 RXWARN -- WIN0/FP1 ICODE0/ EICODE1 EWIN0 EWARN CLKSEL FP0 --/ EICODE0 94 94 94 94 94 Flash Self-Program Control Register (not a physical register) EUSART1 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte EUSART2 Receive Register EUSART2 Transmit Register IRXIP IRXIF IRXIE WAKIP WAKIF WAKIE Data EE Address Register High Byte Data EE Address Register Low Byte Data EE Data Register MDSEL1 TX2SRC REQOP2 OPMODE2 MDSEL0 TX2EN REQOP1 OPMODE1 RXB0OVFL RXB1OVFL 2011 Microchip Technology Inc. Preliminary DS39977C-page 119 PIC18F66K80 FAMILY TABLE 6-2: Addr. F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h F60h F5Fh F5Eh F5Dh F5Ch F5Bh F5Ah F59h F58h F57h F56h F55h F54h F53h F52h F51h F50h F4Fh F4Eh F4Dh F4Ch F4Bh F4Ah F49H F48h F47h F46h F45h F44h F43h F42h F41h F40h F3Fh F3Eh F3Dh F3Ch File Name RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON RXB0CON CM1CON CM2CON ANCON0 ANCON1 WPUB IOCB PMD0 PMD1 PMD2 PADCFG1 CTMUCONH CTMUCONL CTMUICON CCPR2H CCPR2L CCP2CON CCPR3H CCPR3L CCP3CON CCPR4H CCPR4L CCP4CON CCPR5H CCPR5L CCP5CON PSPCON MDCON MDSRC MDCARH MDCARL Unimplemented Unimplemented CANCON_RO0 CANSTAT_RO0 RXB1D7 RXB1D6 CANCON_RO0 CANSTAT_RO0 RXB1D77 RXB1D67 RXB1D76 RXB1D66 RXB1D75 RXB1D65 RXB1D74 RXB1D64 RXB1D73 RXB1D63 RXB1D72 RXB1D62 RXB1D71 RXB1D61 RXB1D70 RXB1D60 PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 RXB0D77 RXB0D67 RXB0D57 RXB0D47 RXB0D37 RXB0D27 RXB0D17 RXB0D07 -- EID7 EID15 SID2 SID10 RXFUL RXFUL CON CON ANSEL7 -- WPUB7 IOCB7 CCP5MD PSPMD -- RDPU CTMUEN EDG2POL ITRIM5 Bit 6 RXB0D76 RXB0D66 RXB0D56 RXB0D46 RXB0D36 RXB0D26 RXB0D16 RXB0D06 RXRTR EID6 EID14 SID1 SID9 RXM1 RXM1 COE COE ANSEL6 ANSEL14 WPUB6 IOCB6 CCP4MD CTMUMD -- REPU -- EDG2SEL1 ITRIM4 Bit 5 RXB0D75 RXB0D65 RXB0D55 RXB0D45 RXB0D35 RXB0D25 RXB0D15 RXB0D05 RB1 EID5 EID13 SID0 SID8 RXM0 RTRRO CPOL CPOL ANSEL5 ANSEL13 WPUB5 IOCB5 CCP3MD ADCMD -- RFPU CTMUSIDL EDG2SEL0 ITRIM3 Bit 4 RXB0D74 RXB0D64 RXB0D54 RXB0D44 RXB0D34 RXB0D24 RXB0D14 RXB0D04 RB0 EID4 EID12 SRR SID7 -- FILHIT4 EVPOL1 EVPOL1 ANSEL4 ANSEL12 WPUB4 IOCB4 CCP2MD TMR4MD -- RGPU TGEN EDG1POL ITRIM2 Bit 3 RXB0D73 RXB0D63 RXB0D53 RXB0D43 RXB0D33 RXB0D23 RXB0D13 RXB0D03 DLC3 EID3 EID11 EXID SID6 RXRTRRO FILHIT3 EVPOL0 EVPOL0 ANSEL3 ANSEL11 WPUB3 -- CCP1MD TMR3MD MODMD -- EDGEN ITRIM1 Bit 2 RXB0D72 RXB0D62 RXB0D52 RXB0D42 RXB0D32 RXB0D22 RXB0D12 RXB0D02 DLC2 EID2 EID10 -- SID5 RXB0DBEN FILHIT2 CREF CREF ANSEL2 ANSEL10 WPUB2 -- UART2MD TMR2MD ECANMD -- EDGSEQEN ITRIM0 Bit 1 RXB0D71 RXB0D61 RXB0D51 RXB0D41 RXB0D31 RXB0D21 RXB0D11 RXB0D01 DLC1 EID1 EID9 EID17 SID4 JTOFF FILHIT1 CCH1 CCH1 ANSEL1 ANSEL9 WPUB1 -- UART1MD TMR1MD CMP2MD -- IDISSEN EDG2STAT IRNG1 Bit 0 RXB0D70 RXB0D60 RXB0D50 RXB0D40 RXB0D30 RXB0D20 RXB0D10 RXB0D00 DLC0 EID0 EID8 EID16 SID3 FILHIT0 FILHIT0 CCH0 CCH0 ANSEL0 ANSEL8 WPUB0 -- SSPMD TMR0MD CMP1MD CTMUDS CTTRIG EDG1STAT IRNG0 Value on POR, BOR on page 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 95 95 95 95 95 95 95 95 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 95 95 95 D32B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 95 95 95 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 95 95 95 DC5B0 PSPMODE MDOPOL -- -- -- CCP5M3 -- MDO MDSRC3 MDCH3 MDCL3 CCP5M2 -- -- MDSRC2 MDCH2 MDCL2 CCP5M1 -- -- MDSRC1 MDCH1 MDCL1 CCP5M0 -- MDBIT MDSRC0 MDCH0 MDCL0 95 95 95 95 95 95 -- -- 95 95 95 95 EDG1SEL1 EDG1SEL0 Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte -- -- DC2B1 Capture/Compare/PWM Register 3 High Byte Capture/Compare/PWM Register 3 Low Byte -- -- DC3B1 Capture/Compare/PWM Register 4 High Byte Capture/Compare/PWM Register 4 Low Byte -- -- DC4B1 Capture/Compare/PWM Register 5 High Byte Capture/Compare/PWM Register 5 Low Byte -- IBF MDEN MDSODIS MDCLODIS -- OBF MDOE -- MDCLPOL DC5B1 IBOV MDSLR -- MDCHSYNC MDCLSYNC MDCHODIS MDCHPOL DS39977C-page 120 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 6-2: Addr. F3Bh F3Ah F39h F38h F37h F36h F35h F34h F33h F32h F31h F30h F30h F2Fh F2Eh F2Dh F2Ch F2Bh F2Ah F29h F28h F27h F26h F25h F24h F23h F22h F21h F20h F1Fh F1Eh F1Dh F1Ch F1Bh F1Ah F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h F0Fh F0Eh F0Dh F0Ch F0Bh F0Ah File Name RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON RXB1CON CANCON_RO1 CANSTAT_RO1 TXB0D7 TXB0D6 TXB0D5 TXB0D4 TXB0D3 TXB0D2 TXB0D1 TXB0D0 TXB0DLC TXB0EIDL TXB0EIDH TXB0SIDL TXB0SIDH TXB0CON CANCON_RO2 CANSTAT_RO2 TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH TXB1SIDL TXB1SIDH TXB1CON CANCON_RO3 CANSTAT_RO3 TXB2D7 TXB2D6 TXB2D5 TXB2D4 PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 RXB1D57 RXB1D47 RXB1D37 RXB1D27 RXB1D17 RXB1D07 -- EID7 EID15 SID2 SID10 RXFUL RXFUL CANCON_RO1 CANSTAT_RO1 TXB0D77 TXB0D67 TXB0D57 TXB0D47 TXB0D37 TXB0D27 TXB0D17 TXB0D07 -- EID7 EID15 SID2 SID10 TXBIF CANCON_RO2 CANSTAT_RO2 TXB1D77 TXB1D67 TXB1D57 TXB1D47 TXB1D37 TXB1D27 TXB1D17 TXB1D07 -- EID7 EID15 SID2 SID10 TXBIF CANCON_RO3 CANSTAT_RO3 TXB2D77 TXB2D67 TXB2D57 TXB2D47 TXB2D76 TXB2D66 TXB2D56 TXB2D46 TXB2D75 TXB2D65 TXB2D55 TXB2D45 TXB2D74 TXB2D64 TXB2D54 TXB2D44 TXB2D73 TXB2D63 TXB2D53 TXB2D43 TXB2D72 TXB2D62 TXB2D52 TXB2D42 TXB2D71 TXB2D61 TXB2D51 TXB2D41 TXB2D70 TXB2D60 TXB2D50 TXB2D40 TXB1D76 TXB1D66 TXB1D56 TXB1D46 TXB1D36 TXB1D26 TXB1D16 TXB1D06 TXRTR EID6 EID14 SID1 SID9 TXABT TXB1D75 TXB1D65 TXB1D55 TXB1D45 TXB1D35 TXB1D25 TXB1D15 TXB1D05 -- EID5 EID13 SID0 SID8 TXLARB TXB1D74 TXB1D64 TXB1D54 TXB1D44 TXB1D34 TXB1D24 TXB1D14 TXB1D04 -- EID4 EID12 SRR SID7 TXERR TXB1D73 TXB1D63 TXB1D53 TXB1D43 TXB1D33 TXB1D23 TXB1D13 TXB1D03 DLC3 EID3 EID11 EXID SID6 TXREQ TXB1D72 TXB1D62 TXB1D52 TXB1D42 TXB1D32 TXB1D22 TXB1D12 TXB1D02 DLC2 EID2 EID10 -- SID5 -- TXB1D71 TXB1D61 TXB1D51 TXB1D41 TXB1D31 TXB1D21 TXB1D11 TXB1D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 TXB1D70 TXB1D60 TXB1D50 TXB1D40 TXB1D30 TXB1D20 TXB1D10 TXB1D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 TXB0D76 TXB0D66 TXB0D56 TXB0D46 TXB0D36 TXB0D26 TXB0D16 TXB0D06 TXRTR EID6 EID14 SID1 SID9 TXABT TXB0D75 TXB0D65 TXB0D55 TXB0D45 TXB0D35 TXB0D25 TXB0D15 TXB0D05 -- EID5 EID13 SID0 SID8 TXLARB TXB0D74 TXB0D64 TXB0D54 TXB0D44 TXB0D34 TXB0D24 TXB0D14 TXB0D04 -- EID4 EID12 SRR SID7 TXERR TXB0D73 TXB0D63 TXB0D53 TXB0D43 TXB0D33 TXB0D23 TXB0D13 TXB0D03 DLC3 EID3 EID11 EXID SID6 TXREQ TXB0D72 TXB0D62 TXB0D52 TXB0D42 TXB0D32 TXB0D22 TXB0D12 TXB0D02 DLC2 EID2 EID10 -- SID5 -- TXB0D71 TXB0D61 TXB0D51 TXB0D41 TXB0D31 TXB0D21 TXB0D11 TXB0D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 TXB0D70 TXB0D60 TXB0D50 TXB0D40 TXB0D30 TXB0D20 TXB0D10 TXB0D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 Bit 6 RXB1D56 RXB1D46 RXB1D36 RXB1D26 RXB1D16 RXB1D06 RXRTR EID6 EID14 SID1 SID9 RXM1 RXM1 Bit 5 RXB1D55 RXB1D45 RXB1D35 RXB1D25 RXB1D15 RXB1D05 RB1 EID5 EID13 SID0 SID8 RXM0 RTRRO Bit 4 RXB1D54 RXB1D44 RXB1D34 RXB1D24 RXB1D14 RXB1D04 RB0 EID4 EID12 SRR SID7 -- FILHIT4 Bit 3 RXB1D53 RXB1D43 RXB1D33 RXB1D23 RXB1D13 RXB1D03 DLC3 EID3 EID11 EXID SID6 FILHIT3 Bit 2 RXB1D52 RXB1D42 RXB1D32 RXB1D22 RXB1D12 RXB1D02 DLC2 EID2 EID10 -- SID5 FILHIT2 Bit 1 RXB1D51 RXB1D41 RXB1D31 RXB1D21 RXB1D11 RXB1D01 DLC1 EID1 EID9 EID17 SID4 JTOFF FILHIT1 Bit 0 RXB1D50 RXB1D40 RXB1D30 RXB1D20 RXB1D10 RXB1D00 DLC0 EID0 EID8 EID16 SID3 FILHIT0 FILHIT0 Value on POR, BOR on page 95 95 95 95 95 95 95 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 97 97 -- RXRTRRO RXBODBEN 2011 Microchip Technology Inc. Preliminary DS39977C-page 121 PIC18F66K80 FAMILY TABLE 6-2: Addr. F09h F08h F07h F06h F05h F04h F03h F02h F01h F00h EFFh EFEh EFDh EFCh EFBh EFAh EF9h EF8h EF7h EF6h EF5h EF4h EF3h EF2h EF1h EF0h EEFh EEEh EEDh EECh EEBh EEAh EE9h EE8h EE7h EE6h EE5h EE4h EE3h EE2h EE1h EE0h EDFh EDEh EDDh EDCh EDBh EDAh ED9h ED8h ED7h File Name TXB2D3 TXB2D2 TXB2D1 TXB2D0 TXB2DLC TXB2EIDL TXB2EIDH TXB2SIDL TXB2SIDH TXB2CON RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EIDL RXF5EIDH RXF5SIDL RXF5SIDH RXF4EIDL RXF4EIDH RXF4SIDL RXF4SIDH RXF3EIDL RXF3EIDH RXF3SIDL RXF3SIDH RXF2EIDL RXF2EIDH RXF2SIDL RXF2SIDH RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDL RXF0EIDH RXF0SIDL RXF0SIDH CANCON_RO4 CANSTAT_RO4 B5D7 B5D6 B5D5 B5D4 B5D3 B5D2 B5D1 PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 TXB2D37 TXB2D27 TXB2D17 TXB2D07 -- EID7 EID15 SID2 SID10 TXBIF EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 CANCON_RO4 CANSTAT_RO4 B5D77 B5D67 B5D57 B5D47 B5D37 B5D27 B5D17 B5D76 B5D66 B5D56 B5D46 B5D36 B5D26 B5D16 B5D75 B5D65 B5D55 B5D45 B5D35 B5D25 B5D15 B5D74 B5D64 B5D54 B5D44 B5D34 B5D24 B5D14 B5D73 B5D63 B5D53 B5D43 B5D33 B5D23 B5D13 B5D72 B5D62 B5D52 B5D42 B5D32 B5D22 B5D12 B5D71 B5D61 B5D51 B5D41 B5D31 B5D21 B5D11 B5D70 B5D60 B5D50 B5D40 B5D30 B5D20 B5D10 Bit 6 TXB2D36 TXB2D26 TXB2D16 TXB2D06 TXRTR EID6 EID14 SID1 SID9 TXABT EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 Bit 5 TXB2D35 TXB2D25 TXB2D15 TXB2D05 -- EID5 EID13 SID0 SID8 TXLARB EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 Bit 4 TXB2D34 TXB2D24 TXB2D14 TXB2D04 -- EID4 EID12 SRR SID7 TXERR EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 Bit 3 TXB2D33 TXB2D23 TXB2D13 TXB2D03 DLC3 EID3 EID11 EXID SID6 TXREQ EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 Bit 2 TXB2D32 TXB2D22 TXB2D12 TXB2D02 DLC2 EID2 EID10 -- SID5 -- EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 Bit 1 TXB2D31 TXB2D21 TXB2D11 TXB2D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 Bit 0 TXB2D30 TXB2D20 TXB2D10 TXB2D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 Value on POR, BOR on page 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 97 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 98 DS39977C-page 122 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 6-2: Addr. ED6h ED5h ED4h ED3h ED2h ED1h ED0h ECFh ECEh ECDh ECCh ECBh ECAh EC9h EC8h EC7h EC6h EC5h EC4h EC3h EC2h EC1h EC0h EBFh EBEh EBDh EBCh EBBh EBAh EB9h EB8h EB7h EB6h EB5h EB4h EB3h EB2h EB1h EB0h EAFh EAEh EADh EACh EABh EAAh EA9h EA8h EA7h EA6h EA5h EA4h File Name B5D0 B5DLC B5EIDL B5EIDH B5SIDL B5SIDH B5CON CANCON_RO5 CANSTAT_RO5 B4D7 B4D6 B4D5 B4D4 B4D3 B4D2 B4D1 B4D0 B4DLC B4EIDL B4EIDH B4SIDL B4SIDH B4CON CANCON_RO6 CANSTAT_RO6 B3D7 B3D6 B3D5 B3D4 B3D3 B3D2 B3D1 B3D0 B3DLC B3EIDL B3EIDH B3SIDL B3SIDH B3CON CANCON_RO7 CANSTAT_RO7 B2D7 B2D6 B2D5 B2D4 B2D3 B2D2 B2D1 B2D0 B2DLC B2EIDL PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 B5D07 -- EID7 EID15 SID2 SID10 TXBIF CANCON_RO5 CANSTAT_RO5 B4D77 B4D67 B4D57 B4D47 B4D37 B4D27 B4D17 B4D07 -- EID7 EID15 SID2 SID10 TXBIF CANCON_RO6 CANSTAT_RO6 B3D77 B3D67 B3D57 B3D47 B3D37 B3D27 B3D17 B3D07 -- EID7 EID15 SID2 SID10 TXBIF CANCON_RO7 CANSTAT_RO7 B2D77 B2D67 B2D57 B2D47 B2D37 B2D27 B2D17 B2D07 -- EID7 B2D76 B2D66 B2D56 B2D46 B2D36 B2D26 B2D16 B2D06 TXRTR EID6 B2D75 B2D65 B2D55 B2D45 B2D35 B2D25 B2D15 B2D05 -- EID5 B2D72 B2D62 B2D52 B2D42 B2D32 B2D22 B2D12 B2D02 -- EID4 B2D73 B2D63 B2D53 B2D43 B2D33 B2D23 B2D13 B2D03 DLC3 EID3 B2D72 B2D62 B2D52 B2D42 B2D32 B2D22 B2D12 B2D02 DLC2 EID2 B2D71 B2D61 B2D51 B2D41 B2D31 B2D21 B2D11 B2D01 DLC1 EID1 B2D70 B2D60 B2D50 B2D40 B2D30 B2D20 B2D10 B2D00 DLC0 EID0 B3D76 B3D66 B3D56 B3D46 B3D36 B3D26 B3D16 B3D06 TXRTR EID6 EID14 SID1 SID9 TXABT B3D75 B3D65 B3D55 B3D45 B3D35 B3D25 B3D15 B3D05 -- EID5 EID13 SID0 SID8 TXLARB B3D73 B3D63 B3D53 B3D43 B3D33 B3D23 B3D13 B3D03 -- EID4 EID12 SRR SID7 TXERR B3D73 B3D63 B3D53 B3D43 B3D33 B3D23 B3D13 B3D03 DLC3 EID3 EID11 EXID SID6 TXREQ B3D72 B3D62 B3D52 B3D42 B3D32 B3D22 B3D12 B3D02 DLC2 EID2 EID10 -- SID5 -- B3D71 B3D61 B3D51 B3D41 B3D31 B3D21 B3D11 B3D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 B3D70 B3D60 B3D50 B3D40 B3D30 B3D20 B3D10 B3D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 B4D76 B4D66 B4D56 B4D46 B4D36 B4D26 B4D16 B4D06 TXRTR EID6 EID14 SID1 SID9 TXABT B4D75 B4D65 B4D55 B4D45 B4D35 B4D25 B4D15 B4D05 -- EID5 EID13 SID0 SID8 TXLARB B4D74 B4D64 B4D54 B4D44 B4D34 B4D24 B4D14 B4D04 -- EID4 EID12 SRR SID7 TXERR B4D73 B4D63 B4D53 B4D43 B4D33 B4D23 B4D13 B4D03 DLC3 EID3 EID11 EXID SID6 TXREQ B4D72 B4D62 B4D52 B4D42 B4D32 B4D22 B4D12 B4D02 DLC2 EID2 EID10 -- SID5 -- B4D71 B4D61 B4D51 B4D41 B4D31 B4D21 B4D11 B4D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 B4D70 B4D60 B4D50 B4D40 B4D30 B4D20 B4D10 B4D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 Bit 6 B5D06 TXRTR EID6 EID14 SID1 SID9 TXABT Bit 5 B5D05 -- EID5 EID13 SID0 SID8 TXLARB Bit 4 B5D04 -- EID4 EID12 SRR SID7 TXERR Bit 3 B5D03 DLC3 EID3 EID11 EXID SID6 TXREQ Bit 2 B5D02 DLC2 EID2 EID10 -- SID5 -- Bit 1 B5D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 Bit 0 B5D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 Value on POR, BOR on page 98 98 98 98 98 98 98 98 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 100 100 100 100 100 100 100 100 2011 Microchip Technology Inc. Preliminary DS39977C-page 123 PIC18F66K80 FAMILY TABLE 6-2: Addr. EA3h EA2h EA1h EA0h E9Fh E9Eh E9Dh E9Ch E9Bh E9Ah E99h E98h E97h E96h E95h E94h E93h E92h E91h E90h E90h E8Fh E8Eh E8Dh E8Ch E8Bh E8Ah E89h E88h E87h E86h E85h E84h E83h E82h E81h E80h E80h E7Fh E7Eh E7Dh E7Ch E7Bh E7Ah E79h E78h E77h E76h E75h E74h E73h File Name B2EIDH B2SIDL B2SIDH B2CON CANCON_RO8 CANSTAT_RO8 B1D7 B1D6 B1D5 B1D4 B1D3 B1D2 B1D1 B1D0 B1DLC B1EIDL B1EIDH B1SIDL B1SIDH B1CON B1CON CANCON_RO9 CANSTAT_RO9 B0D7 B0D6 B0D5 B0D4 B0D3 B0D2 B0D1 B0D0 B0DLC B0EIDL B0EIDH B0SIDL B0SIDH B0CON B0CON TXBIE BIE0 BSEL0 MSEL3 MSEL2 MSEL1 MSEL0 RXFBCON7 RXFBCON6 RXFBCON5 RXFBCON4 RXFBCON3 RXFBCON2 PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 EID15 SID2 SID10 TXBIF CANCON_RO8 CANSTAT_RO8 B1D77 B1D67 B1D57 B1D47 B1D37 B1D27 B1D17 B1D07 -- EID7 EID15 SID2 SID10 TXBIF RXFUL CANCON_RO9 CANSTAT_RO9 B0D77 B0D67 B0D57 B0D47 B0D37 B0D27 B0D17 B0D07 -- EID7 EID15 SID2 SID10 TXBIF RTXFUL -- B0D76 B0D66 B0D56 B0D46 B0D36 B0D26 B0D16 B0D06 RXRTR EID6 EID14 SID1 SID9 TXABT RXM1 -- B0D75 B0D65 B0D55 B0D45 B0D35 B0D25 B0D15 B0D05 RB1 EID5 EID13 SID0 SID8 TXLARB RXRTRRO -- B0D70 B0D60 B0D50 B0D40 B0D30 B0D20 B0D10 B0D00 RB0 EID4 EID12 SRR SID7 TXERR FILHIT4 B0D73 B0D63 B0D53 B0D43 B0D33 B0D23 B0D13 B0D03 DLC3 EID3 EID11 EXID SID6 TXREQ FILHIT3 B0D72 B0D62 B0D52 B0D42 B0D32 B0D22 B0D12 B0D02 DLC2 EID2 EID10 -- SID5 RTREN FILHIT2 B0D71 B0D61 B0D51 B0D41 B0D31 B0D21 B0D11 B0D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 FILHIT1 -- -- B0D70 B0D60 B0D50 B0D40 B0D30 B0D20 B0D10 B0D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 FILHIT0 -- -- B1D76 B1D66 B1D56 B1D46 B1D36 B1D26 B1D16 B1D06 TXRTR EID6 EID14 SID1 SID9 TXABT RXM1 B1D75 B1D65 B1D55 B1D45 B1D35 B1D25 B1D15 B1D05 -- EID5 EID13 SID0 SID8 TXLARB RXRTRRO B1D71 B1D61 B1D51 B1D41 B1D31 B1D21 B1D11 B1D01 -- EID4 EID12 SRR SID7 TXERR FILHIT4 B1D73 B1D63 B1D53 B1D43 B1D33 B1D23 B1D13 B1D03 DLC3 EID3 EID11 EXID SID6 TXREQ FILHIT3 B1D72 B1D62 B1D52 B1D42 B1D32 B1D22 B1D12 B1D02 DLC2 EID2 EID10 -- SID5 RTREN FILHIT2 B1D71 B1D61 B1D51 B1D41 B1D31 B1D21 B1D11 B1D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 FILHIT1 B1D70 B1D60 B1D50 B1D40 B1D30 B1D20 B1D10 B1D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 FILHIT0 Bit 6 EID14 SID1 SID9 TXABT Bit 5 EID13 SID0 SID8 TXLARB Bit 4 EID12 SRR SID7 TXERR Bit 3 EID11 EXID SID6 TXREQ Bit 2 EID10 -- SID5 -- Bit 1 EID9 EID17 SID4 TXPRI1 Bit 0 EID8 EID16 SID3 TXPRI0 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 Value on POR, BOR on page 100 CAN TX Buffer Interrupt Enable CAN Buffer Interrupt Enable Mode Select Register 0 CAN Mask Select Register 3 CAN Mask Select Register 2 CAN Mask Select Register 1 CAN Mask Select Register 0 CAN Buffer 15/14 Pointer Register CAN Buffer 13/12 Pointer Register CAN Buffer 11/10 Pointer Register CAN Buffer 9/8 Pointer Register CAN Buffer 7/6 Pointer Register CAN Buffer 5/4 Pointer Register DS39977C-page 124 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 6-2: Addr. E72h File Name RXFBCON1 PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR on page 101 CAN Buffer 3/2 Pointer Register 2011 Microchip Technology Inc. Preliminary DS39977C-page 125 PIC18F66K80 FAMILY TABLE 6-2: Addr. E71h E70h E6Fh E6Eh E6Dh E6Ch E6Bh E6Ah E69h E68h E67h E66h E65h E64h E63h E62h E61h E60h E5Fh E5Eh E5Dh E5Ch E5Bh E5Ah E59h E58h E57h E56h E55h E54h E53h E52h E51h E50h E4Fh E4Eh E4Dh E4Ch E4Bh E4Ah E49h E48h E47h E46h E45h E44h E43h E42h E41h File Name RXFBCON0 SDFLC RXF15EIDL RXF15EIDH RXF15SIDL RXF15SIDH RXF14EIDL RXF14EIDH RXF14SIDL RXF14SIDH RXF13EIDL RXF13EIDH RXF13SIDL RXF13SIDH RXF12EIDL RXF12EIDH RXF12SIDL RXF12SIDH RXF11EIDL RXF11EIDH RXF11SIDL RXF11SIDH RXF10EIDL RXF10EIDH RXF10SIDL RXF10SIDH RXF9EIDL RXF9EIDH RXF9SIDL RXF9SIDH RXF8EIDL RXF8EIDH RXF8SIDL RXF8SIDH RXF7EIDL RXF7EIDH RXF7SIDL RXF7SIDH RXF6EIDL RXF6EIDH RXF6SIDL RXF6SIDH RXFCON0 RXFCON1 BRGCON3 BRGCON2 BRGCON1 TXERRCNT RXERRCNT PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR on page 101 -- EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 CAN Device Net Count Register EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID4 EID12 SRR SID7 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID3 EID11 EXID SID6 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 101 101 101 101 101 101 101 101 101 101 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 102 -- SEG1PH1 BRP4 TEC4 REC4 -- SEG1PH0 BRP3 TEC3 REC3 SEG2PH2 PRSEG2 BRP2 TEC2 REC2 SEG2PH1 PRSEG1 BRP1 TEC1 REC1 SEG2PH0 PRSEG0 BRP0 TEC0 REC0 102 103 103 103 103 CAN Buffer 1/0 Pointer Register -- EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 -- EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 CAN Receive Filter Control Register 0 CAN Receive Filter Control Register 1 WAKDIS SEG2PHTS SJW1 TEC7 REC7 WAKFIL SAM SJW0 TEC6 REC6 -- SEG1PH2 BRP5 TEC5 REC5 DS39977C-page 126 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will set the Z bit but leave the other bits unchanged. The STATUS register then reads back as `000u u1uu'. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions not affecting any Status bits, see the instruction set summaries in Table 29-2 and Table 29-3. Note: The C and DC bits operate, in subtraction, as borrow and digit borrow bits, respectively. REGISTER 6-2: U-0 -- bit 7 Legend: STATUS REGISTER U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC(1) R/W-x C(2) bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the seven-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred bit 3 bit 2 bit 1 bit 0 Note 1: 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2011 Microchip Technology Inc. Preliminary DS39977C-page 127 PIC18F66K80 FAMILY 6.4 Note: Data Addressing Modes The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. For more information, see Section 6.6 "Data Memory and the Extended Instruction Set". of data RAM (see Section 6.3.3 "General Purpose Register File") or a location in the Access Bank (see Section 6.3.2 "Access Bank"). The Access RAM bit, `a', determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 6.3.1 "Bank Select Register") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit, `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction, either the target register being operated on or the W register. While the program memory can be addressed in only one way, through the program counter, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). For details on this mode's operation, see Section 6.6.1 "Indexed Addressing with Literal Offset". 6.4.3 INDIRECT ADDRESSING 6.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all. They either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples of this mode include SLEEP, RESET and DAW. Other instructions work in a similar way, but require an additional explicit argument in the opcode. This method is known as the Literal Addressing mode because the instructions require some literal value as an argument. Examples of this include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code using loops, such as the example of clearing an entire RAM bank in Example 6-5. It also enables users to perform Indexed Addressing and other Stack Pointer operations for program memory in data memory. 6.4.2 DIRECT ADDRESSING EXAMPLE 6-5: Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies the instruction's data source as either a register address in one of the banks HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue NEXT LFSR CLRF BTFSS BRA CONTINUE DS39977C-page 128 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers. The operands are mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 6-8: INDIRECT ADDRESSING 000h Bank 0 100h Bank 1 200h Bank 2 Using an instruction with one of the Indirect Addressing registers as the operand.... ADDWF, INDF1, 1 ...uses the 12-bit address stored in the FSR pair associated with that register.... FSR1H:FSR1L 7 0 7 0 300h xxxx1111 11001100 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory 2011 Microchip Technology Inc. Preliminary DS39977C-page 129 PIC18F66K80 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. These operands are: * POSTDEC - Accesses the FSR value, then automatically decrements it by `1' afterwards * POSTINC - Accesses the FSR value, then automatically increments it by `1' afterwards * PREINC - Increments the FSR value by `1', then uses it in the operation * PLUSW - Adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value, offset by the value in the W register, with neither value actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair. Rollovers of the FSRnL register, from FFh to 00h, carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (for example, Z, N and OV bits). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. DS39977C-page 130 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that the FSR0H:FSR0L registers contain FE7h, the address of INDF1. Attempts to read the value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair, but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, however, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution, so that they do not inadvertently change settings that might affect the operation of the device. 6.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 "Two-Word Instructions". 2011 Microchip Technology Inc. Preliminary DS39977C-page 131 PIC18F66K80 FAMILY 6.6 Data Memory and the Extended Instruction Set continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is shown in Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 29.2.1 "Extended Instruction Syntax". Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Using the Access Bank for many of the core PIC18 instructions introduces a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode. Inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 6.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or the Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * Use of the Access Bank (`a' = 0) * A file address argument that is less than or equal to 5Fh Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 6.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit = 1), or include a file address of 60h or above. Instructions meeting these criteria will DS39977C-page 132 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations, F60h to FFFh, (Bank 15) of data memory. 000h 060h Bank 0 100h 00h Bank 1 through Bank 14 60h Valid range for `f' FFh Access RAM Bank 15 F40h SFRs FFFh Data Memory Locations below 060h are not available in this addressing mode. F00h When a = 0 and f5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. 000h Bank 0 060h 100h Bank 1 through Bank 14 FSR2H F00h Bank 15 F40h SFRs FFFh Data Memory FSR2L 001001da ffffffff Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'. When a = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 000h Bank 0 060h 100h Bank 1 through Bank 14 BSR 00000000 001001da ffffffff F00h Bank 15 F40h SFRs FFFh Data Memory 2011 Microchip Technology Inc. Preliminary DS39977C-page 133 PIC18F66K80 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described. (See Section 6.3.2 "Access Bank".) An example of Access Bank remapping in this addressing mode is shown in Figure 6-10. Remapping the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit = 1) will continue to use Direct Addressing as before. Any Indirect or Indexed Addressing operation that explicitly uses any of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register address of greater than 05Fh, will use Direct Addressing and the normal Access Bank map. 6.6.4 BSR IN INDEXED LITERAL OFFSET MODE Although the Access Bank is remapped when the extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING 000h 05Fh Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Special Function Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 0 addresses below 5Fh are not available in this mode. They can still be addressed by using the BSR. Not Accessible Bank 0 100h 120h 17Fh 200h Window Bank 1 Bank 1 "Window" 00h 5Fh 60h Bank 2 through Bank 14 SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory DS39977C-page 134 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 7-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 7.5 "Writing to Flash Program Memory". Figure 7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Program Memory Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2011 Microchip Technology Inc. Preliminary DS39977C-page 135 PIC18F66K80 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 "Writing to Flash Program Memory". 7.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers The FREE bit, when set, allows a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, allows a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: 7.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register, not a physical register, is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The EEPGD control bit determines if the access is a program or data EEPROM memory access. When clear, any subsequent operations operate on the data EEPROM memory. When set, any subsequent operations operate on the program memory. The CFGS control bit determines if the access is to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations operate on Configuration registers regardless of EEPGD (see Section 28.0 "Special Features of the CPU"). When clear, memory selection access is determined by EEPGD. During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR4<6>) is set when the write is complete. It must be cleared in software. DS39977C-page 136 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 7-1: R/W-x EEPGD bit 7 Legend: EECON1: EEPROM CONTROL REGISTER 1 R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR(1) R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or, a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2011 Microchip Technology Inc. Preliminary DS39977C-page 137 PIC18F66K80 FAMILY 7.2.2 TABLAT - TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an eight-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 16 MSbs of the TBLPTR (TBLPTR<21:6>) determine which program memory block of 64 bytes is written to. For more detail, see Section 7.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. 7.2.3 TBLPTR - TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID, the User ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways, based on the table operation. These operations are shown in Table 7-1 and only affect the low-order 21 bits. TABLE 7-1: Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write FIGURE 7-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TBLPTR<21:6> TABLE WRITE TBLPTR<5:0> TABLE READ - TBLPTR<21:0> DS39977C-page 138 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 7.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register (IR) FETCH TBLRD TABLAT Read Register EXAMPLE 7-1: MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD READING A FLASH PROGRAM MEMORY WORD CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data 2011 Microchip Technology Inc. Preliminary DS39977C-page 139 PIC18F66K80 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 The erase blocks are 32 words or 64 bytes. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. 2. Load the Table Pointer register with the address of row to be erased. Set the EECON1 register for the erase operation: * Set the EEPGD bit to point to program memory * Clear the CFGS bit to access program memory * Set the WREN bit to enable writes * Set the FREE bit to enable the erase Disable the interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This begins the row erase cycle. The CPU will stall for the duration of the erase for TIW. (See Parameter D133A.) Re-enable interrupts. 3. 4. 5. 6. 7. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EEPGD CFGS WREN FREE GIE ; load TBLPTR with the base ; address of the memory block ERASE_ROW BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts Required Sequence ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts WR GIE DS39977C-page 140 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 7.5 Writing to Flash Program Memory The programming blocks are 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers for programming by the table writes. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 or 128 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 8 TBLPTR = xxxxx2 8 TBLPTR = xxxx3F 8 Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read the 64 bytes into RAM. Update the data values in RAM as necessary. Load Table Pointer register with the address being erased. Execute the row erase procedure. Load Table Pointer register with the address of the first byte being written. Write the 64 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * Set the EEPGD bit to point to program memory * Clear the CFGS bit to access program memory * Set the WREN to enable byte writes Disable the interrupts. 9. Write 55h to EECON2. 10. Write 0AAh to EECON2. 11. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write for TIW (see Parameter D133A). 12. Re-enable the interrupts. 13. Verify the memory (table read). An example of the required code is shown in Example 7-3 on the following page. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. 8. 2011 Microchip Technology Inc. Preliminary DS39977C-page 141 PIC18F66K80 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVF MOVWF DECFSZ BRA MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF WRITE_BUFFER_BACK MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVFF MOVWF TBLWT+* CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L SIZE_OF_BLOCK COUNTER POSTINC0, WREG TABLAT ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT, W POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat SIZE_OF_BLOCK COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; update buffer word ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer ; number of bytes in holding register DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full DS39977C-page 142 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 7-3: PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EEPGD CFGS WREN GIE ; ; ; ; point to Flash program memory access Flash program memory enable write to memory disable interrupts WRITING TO FLASH PROGRAM MEMORY (CONTINUED) Required Sequence ; write 55h ; ; ; ; write 0AAh start program (CPU stall) re-enable interrupts disable write to memory WR GIE WREN 7.5.2 WRITE VERIFY 7.5.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 28.0 "Special Features of the CPU" for more detail. 7.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION 7.6 If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. Flash Program Operation During Code Protection See Section 28.6 "Program Verification and Code Protection" for details on code protection of Flash program memory. TABLE 7-2: Name REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBLPTRU TBPLTRH TBLPTRL TABLAT INTCON EECON2 EECON1 IPR4 PIR4 PIE4 -- -- bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch GIE/GIEH EEPGD TMR4IP TMR4IF TMR4IE PEIE/GIEL CFGS EEIP EEIF EEIE TMR0IE -- CMP2IP CMP2IF CMP2IE INT0IE FREE CMP1IP CMP1IF CMP1IE RBIE WRERR -- -- -- TMR0IF WREN CCP5IP CCP5IF CCP5IE INT0IF WR CCP4IP CCP4IF CCP4IE RBIF RD CCP3IP CCP3IF CCP3IE EEPROM Control Register 2 (not a physical register) Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. 2011 Microchip Technology Inc. Preliminary DS39977C-page 143 PIC18F66K80 FAMILY NOTES: DS39977C-page 144 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 8.0 DATA EEPROM MEMORY 8.2 EECON1 and EECON2 Registers The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space, but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range. Five SFRs are used to read and write to the data EEPROM, as well as the program memory. They are: * * * * * EECON1 EECON2 EEDATA EEADR EEADRH Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit, EEPGD, determines if the access will be to program memory or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set and cleared, when the internal programming timer expires and the write operation is complete. Note: The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and the EEADRH:EEADR register pair holds the address of the EEPROM location being accessed. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature, as well as from chipto-chip. Please refer to Parameter D122 (Table 31-1 in Section 31.0 "Electrical Characteristics") for exact limits. During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. 8.1 EEADR and EEADRH Registers The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The EEADRH:EEADR register pair is used to address the data EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). The EEIF interrupt flag bit (PIR4<6>) is set when the write is complete. It must be cleared in software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 7.1 "Table Reads and Table Writes" regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. 2011 Microchip Technology Inc. Preliminary DS39977C-page 145 PIC18F66K80 FAMILY REGISTER 8-1: R/W-x EEPGD bit 7 Legend: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR(1) R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39977C-page 146 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 8.3 Reading the Data EEPROM Memory After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit; EEIF must be cleared by software. To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available after one instruction cycle, in the EEDATA register. It can be read after one NOP instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation). The basic process is shown in Example 8-1. 8.5 Write Verify 8.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADRH:EEADR register pair and the data written to the EEDATA register. The sequence in Example 8-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Note: Self-write execution to Flash and EEPROM memory cannot be done while running in LP Oscillator (low-power) mode. Executing a self-write will put the device into High-Power mode. 2011 Microchip Technology Inc. Preliminary DS39977C-page 147 PIC18F66K80 FAMILY EXAMPLE 8-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF NOP MOVF DATA EEPROM READ DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W ; ; ; ; ; ; ; Upper bits of Data Memory Address to read Lower bits of Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read ; W = EEDATA EXAMPLE 8-2: DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BSF DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, 55h EECON2 0AAh EECON2 EECON1, EECON1, INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Upper bits of Data Memory Address to write Lower bits of Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete GOTO $-2 Enable Interrupts Required Sequence WR WR GIE BCF EECON1, WREN ; User code execution ; Disable writes on write complete (EEIF set) DS39977C-page 148 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 8.6 Operation During Code-Protect 8.8 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect Configuration bit. Refer to Section 28.0 "Special Features of the CPU" for additional information. The data EEPROM is a high-endurance, byteaddressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 8-3. Note: 8.7 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT, Parameter 33). The write initiate sequence, and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. If data EEPROM is only used to store constants and/or data that changes often, an array refresh is likely not required. See specification D124. EXAMPLE 8-3: CLRF CLRF BCF BCF BCF BSF LOOP BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA INCFSZ BRA BCF BSF DATA EEPROM REFRESH ROUTINE EEADR EEADRH EECON1, EECON1, INTCON, EECON1, ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete Increment Not zero, Increment Not zero, address do it again the high address do it again CFGS EEPGD GIE WREN EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP EEADRH, F LOOP EECON1, WREN INTCON, GIE ; Disable writes ; Enable interrupts 2011 Microchip Technology Inc. Preliminary DS39977C-page 149 PIC18F66K80 FAMILY TABLE 8-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON EEADRH EEADR EEDATA EECON2 EECON1 IPR4 PIR4 PIE4 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EEPROM Address Register High Byte EEPROM Address Register Low Byte EEPROM Data Register EEPROM Control Register 2 (not a physical register) EEPGD TMR4IP TMR4IF TMR4IE CFGS EEIP EEIF EEIE -- CMP2IP CMP2IF CMP2IE FREE CMP1IP CMP1IF CMP1IE WRERR -- -- -- WREN CCP5IP CCP5IF CCP5IE WR CCP4IP CCP4IF CCP4IE RD CCP3IP CCP3IF CCP3IE Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. DS39977C-page 150 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 9.0 9.1 8 x 8 HARDWARE MULTIPLIER Introduction EXAMPLE 9-1: MOVF MULWF ARG1, W ARG2 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows PIC18 devices to be used in many applications previously reserved for digital-signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 9-1. EXAMPLE 9-2: MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 9.2 Operation Example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: Routine PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Multiply Method Program Cycles Memory (Max) (Words) Time @ 64 MHz @ 48 MHz @ 10 MHz @ 4 MHz 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply 13 1 33 6 21 28 52 35 69 1 91 6 242 28 254 40 4.3 s 62.5 ns 5.6 s 375 ns 15.1 s 1.7 s 15.8 s 2.5 s 5.7 s 83.3 ns 7.5 s 500 ns 20.1 s 2.3 s 21.2 s 3.3 s 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 101.6 s 16.0 s 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s 2011 Microchip Technology Inc. Preliminary DS39977C-page 151 PIC18F66K80 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM RES3:RES0= = EQUATION 9-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) RES3:RES0 = = ARG1H:ARG1L ARG2H:ARG2L (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) + (-1 ARG2H<7> ARG1H:ARG1L 216) + (-1 ARG1H<7> ARG2H:ARG2L 216) EXAMPLE 9-4: MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF 16 x 16 SIGNED MULTIPLY ROUTINE EXAMPLE 9-3: MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC 16 x 16 UNSIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L, W ARG2L ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; ARG1H, W ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS ARG2H, 7 BRA SIGN_ARG1 MOVF ARG1L, W SUBWF RES2 MOVF ARG1H, W SUBWFB RES3 SIGN_ARG1 BTFSS ARG1H, 7 BRA CONT_CODE MOVF ARG2L, W SUBWF RES2 MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. DS39977C-page 152 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 10.0 INTERRUPTS Members of the PIC18F66K80 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. The registers for controlling interrupt operation are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3, PIR4 and PIR5 PIE1, PIE2, PIE3, PIE4 and PIE5 IPR1, IPR2, IPR3, IPR4 and IPR5 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit that enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit that enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low-priority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine (ISR), the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) that re-enables interrupts. For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit - Indicating that an interrupt event occurred * Enable bit - Enabling program execution to branch to the interrupt vector address when the flag bit is set * Priority bit - Specifying high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. Do not use the MOVFF instruction to modify any of the Interrupt Control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. 2011 Microchip Technology Inc. Preliminary DS39977C-page 153 PIC18F66K80 FAMILY FIGURE 10-1: PIC18F66K80 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7,5:0> PIR3<7,5> PIE3<7,5> IPR3<7,5> PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Wake-up if in Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7, 5:0> PIE2<7, 5:0> IPR2<7, 5:0> PIR3<7, 5:0> PIE3<7, 5:0> IPR3<7, 5:0> PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP IPEN Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL DS39977C-page 154 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers that contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: R/W-0 GIE/GIEH bit 7 Legend: INTCON: INTERRUPT CONTROL REGISTER R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE(2) R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(1) bit 0 R/W-0 PEIE/GIEL R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit(2) 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register has not overflowed INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: A mismatch condition will continue to set this bit. To end the mismatch condition and allow the bit to be cleared, read PORTB and wait one additional instruction cycle. Each pin on PORTB for interrupt-on-change is individually enabled and disabled in the IOCB register. By default, all pins are enabled. 2011 Microchip Technology Inc. Preliminary DS39977C-page 155 PIC18F66K80 FAMILY REGISTER 10-2: R/W-1 RBPU bit 7 Legend: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 INTEDG1 R/W-1 INTEDG2 R/W-x INTEDG3 R/W-1 TMR0IP R/W-x INT3IP R/W-1 RBIP bit 0 R/W-1 INTEDG0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39977C-page 156 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-3: R/W-1 INT2IP bit 7 Legend: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-0 INT3IE R/W-0 INT2IE R/W-0 INT1IE R/W-x INT3IF R/W-0 INT2IF R/W-0 INT1IF bit 0 R/W-1 INT1IP R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2011 Microchip Technology Inc. Preliminary DS39977C-page 157 PIC18F66K80 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR5). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: R/W-0 PSPIF bit 7 Legend: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R-0 RC1IF R-0 TX1IF R/W-0 SSPIF R/W-0 TMR1GIF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 ADIF R/W-0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or write operation has taken place (must be cleared in software) 0 = No read or write operation has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RC1IF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART receive buffer is empty TX1IF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART transmit buffer is full SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) 0 = No timer gate interrupt occurred TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 158 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-5: R/W-0 OSCFIF bit 7 Legend: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 -- U-0 -- U-0 -- R/W-0 BCLIF R/W-0 HLVDIF R/W-0 TMR3IF R/W-0 TMR3GIF bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (bit must be cleared in software) 0 = Device clock operating Unimplemented: Read as `0' BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (bit must be cleared in software) 0 = No bus collision occurred HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (bit must be cleared in software) 0 = The device voltage is above the regulator's low-voltage trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (bit must be cleared in software) 0 = TMR3 register did not overflow TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (bit must be cleared in software) 0 = No timer gate interrupt occurred bit 6-4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 159 PIC18F66K80 FAMILY REGISTER 10-6: U-0 -- bit 7 Legend: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 -- R-0 RC2IF R-0 TX2IF R/W-0 CTMUIF R/W-0 CCP2IF R/W-0 CCP1IF U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RC2IF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART receive buffer is empty TX2IF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART transmit buffer is full CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Unimplemented: Read as `0' bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 160 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-7: R/W-0 TMR4IF bit 7 Legend: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 R/W-0 EEIF R/W-0 CMP2IF R/W-0 CMP1IF U-0 -- R/W-0 CCP5IF R/W-0 CCP4IF R/W-0 CCP3IF bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR4IF: TMR4 Overflow Interrupt Flag bit 1 = TMR4 register overflowed (must be cleared in software) 0 = TMR4 register did not overflow EEIF: Data EEDATA/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started CMP2IF: CMP2 Interrupt Flag bit 1 = CMP2 interrupt occurred (must be cleared in software) 0 = CMP2 interrupt did not occur CMP1IF: CMP1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software) 0 = CMP1 interrupt did not occur Unimplemented: Read as `0' CCP5IF: CCP5 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Not used in PWM mode. CCP4IF: CCP4 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Not used in PWM mode. CCP3IF: CCP3 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Not used in PWM mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 161 PIC18F66K80 FAMILY REGISTER 10-8: R/W-0 IRXIF bit 7 Legend: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXB2IF R/W-0 TXB1IF R/W-0 TXB0IF R/W-0 RXB1IF R/W-0 RXB0IF/ FIFOFIF bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IRXIF: Invalid Message Received Interrupt Flag bits 1 = An invalid message occurred on the CAN bus 0 = No invalid message occurred on the CAN bus WAKIF: Bus Wake Up Activity Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus ERRIF: Error Interrupt Flag bit (Multiple sources in COMSTAT register) 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN Module errors TXB2IF: Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message TXB1IF: Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message RXB1IF: Receive Buffer 1 Interrupt Flag bit Mode 0: 1 = CAN Receive Buffer 1 has received a new message 0 = CAN Receive Buffer 1 has not received a new message Modes 1 and 2: 1 = A CAN Receive Buffer/FIFO has received a new message 0 = A CAN Receive Buffer/FIFO has not received a new message bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Bit operation is dependent on selected mode: Mode 0: RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = CAN Receive Buffer 0 has received a new message 0 = CAN Receive Buffer 0 has not received a new message Mode 1: Unimplemented: Read as `0' Mode 2: FIFOFIF: FIFO Full Interrupt Flag bit 1 = FIFO has reached full status as defined by the FIFO_HF bit 0 = FIFO has not reached full status as defined by the FIFO_HF bit DS39977C-page 162 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7>) = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-9: R/W-0 PSPIE bit 7 Legend: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 RC1IE R/W-0 TX1IE R/W-0 SSPIE R/W-0 TMR1GIE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 ADIE R/W-0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RC1IE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt TX1IE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enables the gate 0 = Disabled the gate TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 163 PIC18F66K80 FAMILY REGISTER 10-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 OSCFIE bit 7 Legend: U-0 -- U-0 -- U-0 -- R/W-0 BCLIE R/W-0 HLVDIE R/W-0 TMR3IE R/W-0 TMR3GIE bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 164 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-11: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 -- bit 7 Legend: U-0 -- R-0 RC2IE R-0 TX2IE R/W-0 CTMUIE R/W-0 CCP2IE R/W-0 CCP1IE U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RC2IE: EUSART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled TX2IE: EUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 165 PIC18F66K80 FAMILY REGISTER 10-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0 TMR4IE bit 7 Legend: R/W-0 EEIE R/W-0 CMP2IE R/W-0 CMP1IE U-0 -- R/W-0 CCP5IE R/W-0 CCP4IE R/W-0 CCP3IE bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR4IE: TMR4 Overflow Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled EEIE: Data EEDATA/Flash Write Operation Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled CMP2IE: CMP2 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled CMP1IE: CMP1 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled Unimplemented: Read as `0' CCP5IE: CCP5 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled CCP4IE: CCP4 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled CCP3IE: CCP3 Interrupt Flag bits 1 = Interrupt enabled 0 = Interrupt disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 166 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0 IRXIE bit 7 Legend: R/W-0 WAKIE R/W-0 ERRIE R/W-0 TXB2IE R/W-0 TXB1IE R/W-0 TXB0IE R/W-0 RXB1IE R/W-0 RXB0IE/ FIFOFIE bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IRXIE: Invalid Message Received Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled WAKIE: Bus Wake Up Activity Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled ERRIE: Error Interrupt Flag bit (multiple sources in the COMSTAT register) 1 = Interrupt enabled 0 = Interrupt disabled TXB2IE: Transmit Buffer 2 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled TXB1IE: Transmit Buffer 1 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled TXB0IE: Transmit Buffer 0 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled RXB1IE: Receive Buffer 1 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Bit operation is dependent on selected mode: Mode 0: RXB0IE: Receive Buffer 0 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled Mode 1: Unimplemented: Read as `0' Mode 2: FIFOFIE: FIFO Full Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled 2011 Microchip Technology Inc. Preliminary DS39977C-page 167 PIC18F66K80 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Priority registers (IPR1 through IPR6). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit (RCON<7>) be set. REGISTER 10-14: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 PSPIP bit 7 Legend: R/W-1 ADIP R/W-1 RC1IP R/W-1 TX1IP R/W-1 SSPIP R/W-1 TMR1GIP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RC1IP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TX1IP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority TMR1GIP: Timer1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 bit 1 bit 0 DS39977C-page 168 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 OSCFIP bit 7 Legend: U-0 -- U-0 -- U-0 -- R/W-1 BCLIP R/W-1 HLVDIP R/W-1 TMR3IP R/W-1 TMR3GIP bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 169 PIC18F66K80 FAMILY REGISTER 10-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 -- bit 7 Legend: U-0 -- R/W-1 RC2IP R/W-1 TX2IP R/W-1 CTMUIP R/W-1 CCP2IP R/W-1 CCP1IP U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RC2IP: EUSART Receive Priority Flag bit 1 = High priority 0 = Low priority TX2IP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 170 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 10-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 R/W-1 TMR4IP bit 7 Legend: R/W-1 EEIP R/W-1 CMP2IP R/W-1 CMP1IP U-0 -- R/W-1 CCP5IP R/W-1 CCP4IP R/W-1 CCP3IP bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR4IP: TMR4 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority EEIP: EE Interrupt Priority bit 1 = High priority 0 = Low priority CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority CCP3IP: CCP3 Interrupt Priority bits 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 2011 Microchip Technology Inc. Preliminary DS39977C-page 171 PIC18F66K80 FAMILY REGISTER 10-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 IRXIP bit 7 Legend: R/W-1 WAKIP R/W-1 ERRIP R/W-1 TXB2IP R/W-1 TXB1IP R/W-1 TXB0IP R/W-1 RXB1IP R/W-1 RXB0IP/ FIFOFIE bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IRXIP: Invalid Message Received Interrupt Priority bits 1 = High priority 0 = Low priority WAKIP: Bus Wake Up Activity Interrupt Priority bit 1 = High priority 0 = Low priority ERRIP: CAN Bus Error Interrupt Priority bit 1 = High priority 0 = Low priority TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority RXB1IP: Receive Buffer 1 Interrupt Priority bit Mode 0: 1 = High priority for Receive Buffer 1 0 = Low priority for Receive Buffer 1 Modes 1 and 2: 1 = High priority for received messages 0 = Low priority for received messages RXB0IP/FIFOFIP: Receive Buffer 0 Interrupt Priority bit Mode 0: 1 = High priority for Receive Buffer 0 0 = Low priority for Receive Buffer 0 Mode 1: Unimplemented: Read as `0' Mode 2: FIFOFIE: FIFO Full Interrupt Flag bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 172 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-19: RCON: RESET CONTROL REGISTER R/W-0 IPEN bit 7 Legend: R/W-1 SBOREN R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) SBOREN: Software BOR Enable bit For details of bit operation, see Register 5-1. CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be subsequently set in software) RI: RESET Instruction Flag bit For details of bit operation, see Register 5-1. TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register 5-1. PD: Power-Down Detection Flag bit For details of bit operation, see Register 5-1. POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 173 PIC18F66K80 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If that bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Before re-enabling the interrupt, the flag bit (INTxIF) must be cleared in software in the Interrupt Service Routine. All external interrupts (INT0, INT1, INT2 and INT3) can wake up the processor from the power-managed modes, if bit, INTxIE, was set prior to going into the power-managed modes. If the Global Interrupt Enable bit (GIE) is set, the processor will branch to the interrupt vector following wake-up. The interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. In 8-bit mode (the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). For further details on the Timer0 module, see Section 13.0 "Timer0 Module". 10.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>), and each individual pin can be enabled/disabled by its corresponding bit in the IOCB register. Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). REGISTER 10-20: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-0 IOCB7(1) bit 7 Legend: R/W-0 IOCB6(1) R/W-0 IOCB5(1) R/W-0 IOCB4(1) U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IOCB<7:4>: Interrupt-on-Change PORTB Control bits(1) 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Unimplemented: Read as `0' bit 3-0 Note 1: Interrupt-on-change also requires that the RBIE bit of the INTCON register be set. DS39977C-page 174 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 10.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section 6.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine (ISR). Depending on the user's application, other registers also may need to be saved. Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS ; Restore BSR ; Restore WREG ; Restore STATUS TABLE 10-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON INTCON2 INTCON3 PIR1 PIR2 PIR3 PIR4 PIR5 PIE1 PIE2 PIE3 PIE4 PIE5 IPR1 IPR2 IPR3 IPR4 IPR5 RCON GIE/GIEH RBPU INT2IP PSPIP OSCFIF -- TMR4IF IRXIF PSPIE OSCFIE -- TMR4IE IRXIE PSPIP OSCFIP -- TMR4IP IRXIP IPEN PEIE/GIEL INTEDG0 INT1IP ADIF -- -- EEIF WAKIF ADIE -- -- EEIE WAKIE ADIP -- -- EEIP WAKIP SBOREN TMR0IE INTEDG1 INT3IE RC1IF -- RC2IF CMP2IF ERRIF RC1IE -- RC2IE CCP2IE ERRIE RC1IP -- RC2IP CMP2IP ERRIP CM INT0IE INTEDG2 INT2IE TX1IF -- TX2IF CMP1IF TXB2IF TX1IE -- TX2IE CMP1IE TXB2IE TX1IP -- TX2IP CMP1IP TXB2IP RI RBIE INTEDG3 INT1IE SSPIF BCLIF CTMUIF -- TXB1IF SSPIE BCLIE CTMUIE -- TXB1IE SSPIP BCLIP CTMUIP -- TXB1IP TO TMR0IF TMR0IP INT3IF TMR1GIF HLVDIF CCP2IF CCP5IF TXB0IF TMR1GIE HLVDIE CCP2IE CCP5IE TXB0IE TMR1GIP HLVDIP CCP2IP CCP5IP TXB0IP PD INT0IF INT3IP INT2IF TMR2IF TMR3IF CCP1IF CCP4IF RXB1IF TMR2IE TMR3IE CCP1IE CCP4IE RXB1IE TMR2IP TMR3IP CCP1IP CCP4IP RXB1IP POR RBIF RBIP INT1IF TMR1IF TMR3GIF -- CCP3IF RXB0IF TMR1IE TMR3GIE -- CCP3IE RXB0IE TMR1IP TMR3GIP -- CCP3IP RXB0IP BOR Legend: Shaded cells are not used by the interrupts. 2011 Microchip Technology Inc. Preliminary DS39977C-page 175 PIC18F66K80 FAMILY NOTES: DS39977C-page 176 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to seven ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three memory mapped registers for its operation: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Output Latch register) Reading the PORT register reads the current status of the pins, whereas writing to the PORT register, writes to the Output Latch (LAT) register. Setting a TRIS bit (= 1) makes the corresponding port pin an input (putting the corresponding output driver in a High-Impedance mode). Clearing a TRIS bit (= 0) makes the corresponding port pin an output (i.e., put the contents of the corresponding LAT bit on the selected pin). The Output Latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. Read-modify-write operations on the LAT register read and write the latched output value for the PORT register. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than VDD input levels. All of the digital ports are 5.5V input tolerant. The analog ports have the same tolerance, having clamping diodes implemented internally. 11.1.1 PIN OUTPUT DRIVE When used as digital I/O, the output pin drive strengths vary, according to the pins' grouping to meet the needs for a variety of applications. In general, there are two classes of output pins, in terms of drive capability: * Outputs designed to drive higher current loads such as LEDs: - PORTA - PORTB - PORTC * Outputs with lower drive levels, but capable of driving normal digital circuit loads with a high input impedance. Able to drive LEDs, but only those with smaller current requirements: - PORTD(1) - PORTE(1) (2) - PORTG(2) - PORTF Note 1: These ports are not available on 28-pin devices. 2: These ports are not available on 28-pin or 40/44-pin devices FIGURE 11-1: GENERIC I/O PORT OPERATION For more details, see "Absolute Maximum Ratings" in Section 31.0 "Electrical Characteristics". 11.1.2 PULL-UP CONFIGURATION RD LAT Data Bus WR LAT or PORT D CKx Q I/O Pin(1) Five of the I/O ports (PORTB, PORTD, PORTE, PORTF and PORTG) implement configurable weak pull-ups on all pins. These are internal pull-ups that allow floating digital input signals to be pulled to a consistent level without the use of external resistors. The pull-ups are enabled with a single bit for each of the ports: RBPU (INTCON2<7>) for PORTB, and RDPU, REPU, RFPU and RGPU (PADCFG1<7:4>) for the other ports. Additionally, the PORTB pull-up resistors can be enabled individually using the WPUB register. Each bit in the register corresponds to a bit on PORTB. Data Latch D WR TRIS CKx TRIS Latch RD TRIS Input Buffer Q Q D EN EN RD PORT Note 1: I/O pins have diode protection to VDD and VSS. 2011 Microchip Technology Inc. Preliminary DS39977C-page 177 PIC18F66K80 FAMILY REGISTER 11-1: R/W-0 RDPU(1) bit 7 Legend: PADCFG1: PAD CONFIGURATION REGISTER R/W-0 R/W-0 RFPU (2) R/W-0 RGPU (2) U-0 -- U-0 -- U-0 -- R/W-0 CTMUDS bit 0 REPU (1) R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RDPU: PORTD Pull-up Enable bit(1) 1 = PORTD pull-up resistors are enabled by individual port latch values 0 = All PORTD pull-up resistors are disabled REPU: PORTE Pull-up Enable bit(1) 1 = PORTE pull-up resistors are enabled by individual port latch values 0 = All PORTE pull-up resistors are disabled RFPU: PORTF Pull-up Enable bit(2) 1 = PORTF pull-up resistors are enabled by individual port latch values 0 = All PORTF pull-up resistors are disabled RGPU: PORTG Pull-up Enable bit(2) 1 = PORTG pull-up resistors are enabled by individual port latch values 0 = All PORTG pull-up resistors are disabled Unimplemented: Read as `0' CTMUDS: CTMU Comparator Data Select bit 1 = External comparator (with output on pin CTDIN) is used for CTMU compares 0 = Internal comparator (CMP2) is used for CTMU compares bit 6 bit 5 bit 4 bit 3-1 bit 0 Note 1: 2: Unimplemented on 28-pin devices. Unimplemented on 40-pin devices. REGISTER 11-2: R/W-1 WPUB7 bit 7 Legend: WPUB: WEAK PULL-UP PORTB ENABLE REGISTER R/W-1 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0 bit 0 WPUB6 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WPUB<7:0>: Weak Pull-Up Enable Register bits 1 = Pull-up enabled on corresponding PORTB pin when RBPU = 0 and the pin is an input 0 = Pull-up disabled on corresponding PORTB pin DS39977C-page 178 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.1.3 OPEN-DRAIN OUTPUTS FIGURE 11-2: The output pins for several peripherals are also equipped with a configurable, open-drain output option. This allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. The open-drain option is implemented on port pins specifically associated with the data and clock outputs of the USARTs, the MSSP module (in SPI mode) and the CCP modules. This option is selectively enabled by setting the open-drain control bits in the ODCON register. When the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5V (Figure 11-2). When a digital logic high signal is output, it is pulled up to the higher voltage level. USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) +5V 3.3V PIC18F66K80 VDD TXX (at logic `1') 3.3V 5V REGISTER 11-3: R/W-0 SSPOD bit 7 Legend: ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER R/W-0 R/W-0 CCP4OD R/W-0 CCP3OD R/W-0 CCP2OD R/W-0 CCP1OD R/W-0 U2OD R/W-0 U1OD bit 0 CCP5OD R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SSPOD: SPI Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled CCP5OD: CCP5 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled CCP4OD: CCP4 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled CCP3OD: CCP3 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled CCP2OD: CCP2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled CCP1OD: CCP1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled U2OD: UART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled U1OD: UART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 179 PIC18F66K80 FAMILY 11.1.4 ANALOG AND DIGITAL PORTS 11.1.5 PORT SLEW RATE Many of the ports multiplex analog and digital functionality, providing a lot of flexibility for hardware designers. PIC18F66K80 family devices can make any analog pin analog or digital, depending on an application's needs. The ports' analog/digital functionality is controlled by the registers: ANCON0 and ANCON1. Setting these registers makes the corresponding pins analog and clearing the registers makes the ports digital. For details on these registers, see Section 23.0 "12-Bit Analog-to-Digital Converter (A/D) Module" The output slew rate of each port is programmable to select either the standard transition rate, or a reduced transition rate of ten percent of the standard transition time, to minimize EMI. The reduced transition time is the default slew rate for all ports. REGISTER 11-4: U-0 -- bit 7 Legend: SLRCON: SLEW RATE CONTROL REGISTER R/W-0 R/W-0 SLRF(1) R/W-0 SLRE(2) R/W-0 SLRD(2) R/W-0 SLRC(2) R/W-0 SLRB R/W-0 SLRA bit 0 SLRG(1) R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' SLRG: PORTG Slew Rate Control bit(1) 1 = All output pins on PORTG slew at 0.1 the standard rate 0 = All output pins on PORTG slew at standard rate SLRF: PORTF Slew Rate Control bit(1) 1 = All output pins on PORTF slew at 0.1 the standard rate 0 = RAll output pins on PORTF slew at standard rate SLRE: PORTE Slew Rate Control bit(2) 1 = All output pins on PORTE slew at 0.1 the standard rate 0 = All output pins on PORTE slew at standard rate SLRD: PORTD Slew Rate Control bit(2) 1 = All output pins on PORTD slew at 0.1 the standard rate 0 = All output pins on PORTD slew at standard rate SLRC: PORTC Slew Rate Control bit(2) 1 = All output pins on PORTC slew at 0.1 the standard rate 0 = All output pins on PORTC slew at standard rate SLRB: PORTB Slew Rate Control bit 1 = All output pins on PORTB slew at 0.1 the standard rate 0 = All output pins on PORTB slew at standard rate SLRA: PORTA Slew Rate Control bit 1 = All output pins on PORTA slew at 0.1 the standard rate 0 = All output pins on PORTA slew at standard rate bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: Unimplemented and read back as `0' on 28-pin and 40/44-pin devices. Unimplemented and read back as `0' on 28-pin devices. DS39977C-page 180 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.2 PORTA, TRISA and LATA Registers OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally serve as the external circuit connections for the external (primary) oscillator circuit (HS Oscillator modes) or the external clock input and output (EC Oscillator modes). In these cases, RA6 and RA7 are not available as digital I/O and their corresponding TRIS and LAT bits are read as `0'. When the device is configured to use HF-INTOSC, MF-INTOSC or LF-INTOSC as the default oscillator mode, RA6 and RA7 are automatically configured as digital I/O; the oscillator and clock in/clock out functions are disabled. RA5 has additional functionality for Timer1 and Timer3. It can be configured as the Timer1 clock input or the Timer3 external clock gate input. PORTA is a seven-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISA and LATA. RA5 and RA<3:0> are multiplexed with analog inputs for the A/D Converter. The operation of the analog inputs as A/D Converter inputs is selected by clearing or setting the ANSEL control bits in the ANCON1 register. The corresponding TRISA bits control the direction of these pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Note: RA5 and RA<3:0> are configured as analog inputs on any Reset and are read as `0'. EXAMPLE 11-1: CLRF CLRF MOVLW MOVWF MOVLW MOVWF ; ; LATA ; ; 00h ; ANCON1 ; 0BFh ; ; TRISA ; ; PORTA INITIALIZING PORTA Initialize PORTA by clearing output latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<7, 5:0> as inputs, RA<6> as output 2011 Microchip Technology Inc. Preliminary DS39977C-page 181 PIC18F66K80 FAMILY TABLE 11-1: Pin Name RA0/CVREF/AN0/ ULPWU PORTA FUNCTIONS Function RA0 CVREF AN0 ULPWU TRIS Setting 0 1 x 1 1 0 1 AN1 C1INC(1) 1 x 0 1 VREFAN2 C2INC(1) 1 1 x 0 1 VREF+ AN3 1 1 0 1 AN4 C2INB(2) HLVDIN T1CKI SS CTMUI(2) 1 1 1 x 1 x 0 1 OSC2 CLKOUT x x 0 1 OSC1 CLKIN x x I/O O I O I O O I I I O I I I I O I I I O I I I I I I O O I O O O I I I I/O Type DIG ST ANA ANA DIG DIG ST ANA ANA DIG ST ANA ANA ANA DIG ST ANA ANA DIG ST ANA ANA ANA ST ST -- DIG ST ANA DIG DIG ST ANA ANA Description LATA<0> data output; not affected by analog input. PORTA<0> data input; disabled when analog input is enabled. Comparator voltage reference output. Enabling this feature disables digital I/O. A/D Input Channel 0. Default input configuration on POR; does not affect digital output. Ultra low-power wake-up input. LATA<1> data output; not affected by analog input. PORTA<1> data input; disabled when analog input is enabled. A/D Input Channel 1. Default input configuration on POR; does not affect digital output. Comparator 1 Input C. LATA<2> data output; not affected by analog input. PORTA<2> data input; disabled when analog functions are enabled. A/D and comparator low reference voltage input. A/D Input Channel 2. Default input configuration on POR. Comparator 2 Input C. LATA<3> data output; not affected by analog input. PORTA<3> data input; disabled when analog input is enabled. A/D Input Channel 3. Default input configuration on POR. A/D and comparator high reference voltage input. LATA<5> data output; not affected by analog input. PORTA<5> data input; disabled when analog input is enabled. A/D Input Channel 4. Default configuration on POR. Comparator 2 Input B. High/Low-Voltage Detect external trip point input. Timer1 clock input. Slave select input for MSSP module. CTMU pulse generator charger for the C2INB comparator input. LATA<6> data output; disabled when FOSC2 Configuration bit is set. PORTA<6> data input; disabled when FOSC2 Configuration bit is set. Main oscillator feedback output connection (HS, XT and LP modes). System cycle clock output (FOSC/4) (EC and INTOSC modes). LATA<7> data output; disabled when FOSC2 Configuration bit is set. PORTA<7> data input; disabled when FOSC2 Configuration bit is set. Main oscillator input connection (HS, XT, and LP modes). Main external clock source input (EC modes). RA1/AN1/C1INC RA1 RA2/VREF-/AN2/ C2INC RA2 RA3/VREF+/AN3 RA3 RA5/AN4/C2INB/ HLVDIN/T1CKI/SS/ CTMUI RA5 RA6/OSC2/ CLKOUT RA6 RA7/OSC1/CLKIN RA7 Legend: Note 1: 2: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment unavailable for 28-pin devices (PIC18F2XK80). Pin assignment only available for 28-pin devices (PIC18F2XK80). DS39977C-page 182 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 11-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTA LATA TRISA ANCON0 RA7(1) LATA7(1) TRISA7(1) ANSEL7 RA6(1) LATA6 (1) (1) RA5 LATA5 TRISA5 ANSEL5 -- -- -- ANSEL4 RA3 LATA3 TRISA3 ANSEL3 RA2 LATA2 TRISA2 ANSEL2 RA1 LATA1 TRISA1 ANSEL1 RA0 LATA0 TRISA0 ANSEL0 TRISA6 ANSEL6 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as `x'. 2011 Microchip Technology Inc. Preliminary DS39977C-page 183 PIC18F66K80 FAMILY 11.3 PORTB, TRISB and LATB Registers Four of the PORTB pins (RB<7:4>) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur. Any RB<7:4> pins that are configured as outputs are excluded from the interrupt-on-change comparison. Comparisons with the input pins (of RB<7:4>) are made with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from power-managed modes. To clear the interrupt in the Interrupt Service Routine: 1. 2. Perform any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). Wait one instruction cycle (such as executing a NOP instruction). This ends the mismatch condition. 3. Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared after a one TCY delay. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB<3:2> pins are multiplexed as CTMU edge inputs. RB5 has an additional function for Timer3 and Timer1. It can be configured for Timer3 clock input or Timer1 external clock gate input. PORTB is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only. EXAMPLE 11-2: CLRF PORTB ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTB Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs CLRF LATB MOVLW 0CFh MOVWF TRISB Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. DS39977C-page 184 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 11-3: Pin Name RB0/AN10/C1INA FLT0/INT0 PORTB FUNCTIONS Function RB0 AN10 C1INA(1) FLT0 INT0 TRIS Setting 0 1 1 1 x 1 0 1 AN8 C1INB(1) P1B (1) I/O O I I I I I O I I I O I I O I O O O I I O I I I O I I O I I I O I O I/O Type DIG ST ANA ANA ST ST DIG ST ANA ANA DIG ST ST DIG ST DIG DIG DIG ST ST DIG ST ST ST DIG ST ST DIG ST ANA ANA DIG ST DIG LATB<0> data output. Description PORTB<0> data input; weak pull-up when RBPU bit is cleared. A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. Comparator 1 Input A. Enhanced PWM Fault input for ECCPx. External Interrupt 0 input. LATB<1> data output. PORTB<1> data input; weak pull-up when RBPU bit is cleared. A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. Comparator 1 Input B. ECCP1 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. CTMU pulse delay input. External Interrupt 1 input. LATB<2> data output. PORTB<2> data input; weak pull-up when RBPU bit is cleared. CAN bus TX. Comparator 1 output; takes priority over port data. ECCP1 PWM Output C. May be configured for tri-state during Enhanced PWM. CTMU Edge 1 input. External Interrupt 2. LATB<3> data output. PORTB<3> data input; weak pull-up when RBPU bit is cleared. CAN bus RX. CTMU Edge 2 input. ECCP1 PWM Output D. May be configured for tri-state during Enhanced PWM. CTMU Edge 2 input. External Interrupt 3 input. LATB<4> data output. PORTB<4> data input; weak pull-up when RBPU bit is cleared. A/D Input Channel 9 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. Comparator 2 Input A. ECCP1 compare output and ECCP1 PWM output. Takes priority over port data. ECCP1 capture input. ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. CTMU pulse generator output. Interrupt-on-pin change. RB1/AN8/C1INB/ P1B/CTDIN/INT1 RB1 1 1 0 1 1 0 1 CTDIN INT1 RB2/CANTX/C1OUT/ P1C/CTED1/INT2 RB2 CANTX(2) C1OUT(1) P1C(1) CTED1 INT2 RB3/CANRX/ C2OUT/P1D/ CTED2/INT3 RB3 CANRX(2) C2OUT(1) P1D (1) 0 0 0 x 1 0 1 1 x 0 x 1 0 1 1 2 0 1 CTED2 INT3 RB4/AN9/C2INA/ ECCP1/P1A/CTPLS/ KBI0 RB4 AN9 C2INA(1) ECCP1(1) P1A (1) 0 CTPLS KBI0 Legend: Note 1: 2: 3: 4: x 1 O I DIG ST O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment only available for 28-pin devices (PIC18F2XK80). Default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set. Default pin assignment for T0CKI when the T0CKMX Configuration bit is set. Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices when T3CKMX is cleared. 2011 Microchip Technology Inc. Preliminary DS39977C-page 185 PIC18F66K80 FAMILY TABLE 11-3: Pin Name RB5/T0CKI/T3CKI/ CCP5/KBI1 PORTB FUNCTIONS (CONTINUED) Function RB5 T0CKI(3) T3CKI(4) CCP5 KBI1 TRIS Setting 0 1 x x 0 1 1 0 1 PGC TX2(1) CK2(1) x 0 0 1 KBI2 1 0 1 PGD T3G RX2(1) DT2(1) x x x 1 1 1 KBI3 1 I/O O I I I O I I O I I O O I I O I O I I I O I I I/O Type DIG ST ST ST DIG ST ST DIG ST ST DIG DIG ST ST DIG ST DIG ST ST ST DIG ST ST LATB<5> data output. PORTB<5> data input; weak pull-up when RBPU bit is cleared. Timer0 clock input. Timer3 clock input. CCP5 compare/PWM output. Takes priority over port data. CCP5 capture input. Interrupt-on-pin change. LATB<6> data output. PORTB<6> data input; weak pull-up when RBPU bit is cleared. Serial execution (ICSPTM) clock input for ICSP and ICD operation. Asynchronous serial data output (EUSART module); takes priority over port data. Synchronous serial clock output (EUSART module); user must configure as an input. Synchronous serial clock input (EUSART module); user must configure as an input. Interrupt-on-pin change. LATB<7> data output. PORTB<7> data input; weak pull-up when RBPU bit is cleared. Serial execution data output for ICSP and ICD operation. Serial execution data input for ICSP and ICD operation. Timer3 external clock gate input. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (AUSART module); takes priority over port data. Synchronous serial data input (AUSART module); user must configure as an input. Interrupt-on-pin change. Description RB6/PGC/TX2/CK2/ KBI2 RB6 RB7/PGD/T3G/RX2/ DT2/KBI3 RB7 Legend: Note 1: 2: 3: 4: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment only available for 28-pin devices (PIC18F2XK80). Default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set. Default pin assignment for T0CKI when the T0CKMX Configuration bit is set. Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices when T3CKMX is cleared. TABLE 11-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTB LATB TRISB INTCON INTCON2 INTCON3 ODCON ANCON1 RB7 LATB7 TRISB7 GIE/GIEH RBPU INT2IP SSPOD -- RB6 LATB6 TRISB6 PEIE/GIEL INTEDG0 INT1IP CCP5OD ANSEL14 RB5 LATB5 TRISB5 TMR0IE INTEDG1 INT3IE CCP4OD ANSEL13 RB4 LATB4 TRISB4 INT0IE INTEDG2 INT2IE CCP3OD ANSEL12 RB3 LATB3 TRISB3 RBIE INTEDG3 INT1IE CCP2OD ANSEL11 RB2 LATB2 TRISB2 TMR0IF TMR0IP INT3IF CCP1OD ANSEL10 RB1 LATB1 TRISB1 INT0IF INT3IP INT2IF U2OD ANSEL9 RB0 LATB0 TRISB0 RBIF RBIP INT1IF U1OD ANSEL8 Legend: Shaded cells are not used by PORTB. DS39977C-page 186 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.4 PORTC, TRISC and LATC Registers When enabling peripheral functions, use care in defining TRIS bits for each PORTC pin. Some peripherals can override the TRIS bit to make a pin an output or input. Consult the corresponding peripheral section for the correct TRIS bit settings. Note: PORTC is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISC and LATC. Only PORTC pins, RC2 through RC7, are digital only pins. PORTC is multiplexed with CCP, MSSP and EUSART peripheral functions (Table 11-5). The pins have Schmitt Trigger input buffers. The pins for CCP, SPI and EUSART are also configurable for open-drain output whenever these functions are active. Open-drain configuration is selected by setting the SSPOD, CCPxOD and U1OD control bits in the ODCON register. RC1 is configurable for open-drain output when CCP2 is active on this pin. Open-drain configuration is selected by setting the CCP2OD control bit (ODCON<3>). These pins are configured as digital inputs on any device Reset. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 11-3: CLRF PORTC ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTC Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs CLRF LATC MOVLW 0CFh MOVWF TRISC 2011 Microchip Technology Inc. Preliminary DS39977C-page 187 PIC18F66K80 FAMILY TABLE 11-5: Pin Name RC0/SOSCO/ SCLKI PORTC FUNCTIONS Function RC0 SOSCO SCLKI TRIS Setting 0 1 1 1 0 1 SOSCI x 0 1 T1G CCP2 x 0 1 I/O O I I I O I I O I I O I O I O O I O I O I O I I O I O O I O O O I O I I2C I/O Type DIG ST ST ST DIG ST DIG ST ST DIG ST DIG ST DIG DIG I2C DIG ST DIG ST DIG I2C ST DIG ST DIG DIG ST DIG DIG DIG ST DIG ST LATC<0> data output. PORTC<0> data input. SOSC oscillator output. Digital clock input; enabled when SOSC oscillator is disabled. LATC<1> data output. PORTC<1> data input. LATC<2> data output. PORTC<2> data input. Timer1 external clock gate input. CCP2 compare/PWM output. Takes priority over port data. CCP2 capture input. LATC<3> data output. PORTC<3> data input. Reference output clock. I2CTM clock output (MSSP module); takes priority over port data. I2C clock input (MSSP module); input type depends on module setting. SPI clock output (MSSP module); takes priority over port data. SPI clock input (MSSP module). LATC<4> data output. PORTC<4> data input. I2C data output (MSSP module); takes priority over port data. I2C data input (MSSP module); input type depends on module setting. SPI data input (MSSP module). LATC<5> data output. PORTC<5> data input. SPI data output (MSSP module). LATC<6> data output. PORTC<6> data input. CAN bus TX. Asynchronous serial data output (EUSART module); takes priority over port data. Synchronous serial clock output (EUSART module); user must configure as an input. Synchronous serial clock input (EUSART module); user must configure as an input. CCP3 compare/PWM output. Takes priority over port data. CCP3 capture input. Description RC1/SOSCI RC1 ANA SOSC oscillator input. RC2/T1G/ CCP2 RC2 RC3/REFO/ SCL/SCK RC3 REFO SCL SCK 0 1 x 0 1 0 1 0 1 RC4/SDA/SDI RC4 SDA SDI 1 1 1 0 1 RC5/SDO RC5 SDO 0 0 1 RC6/CANTX/ TX1/CK1/ CCP3 RC6 CANTX(1) TX1(1) CK1(1) 0 0 0 1 CCP3 Legend: Note 1: 2: 0 1 = ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, O = Output, I = Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80). Alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX Configuration bit is set. I2C/SMBus, DS39977C-page 188 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 11-5: Pin Name RC7/CANRX/ RX1/DT1/ CCP4 PORTC FUNCTIONS (CONTINUED) Function RC7 CANRX(1) RX1(1) DT1(1) TRIS Setting 0 1 1 1 1 1 CCP4 0 1 I/O O I I I O I O I I/O Type DIG ST ST ST DIG ST DIG ST LATC<7> data output. PORTC<7> data input. CAN bus RX. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (EUSART module); takes priority over port data. Synchronous serial data input (EUSART module); user must configure as an input. CCP4 compare/PWM output. Takes priority over port data. CCP4 capture input. Description Legend: Note 1: 2: O = Output, I = Input, I2C = I2C/SMBus, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80). Alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX Configuration bit is set. TABLE 11-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTC LATC TRISC ODCON RC7 LATC7 TRISC7 SSPOD RC6 LATBC6 TRISC6 CCP5OD RC5 LATC5 TRISC5 CCP4OD RC4 LATCB4 TRISC4 CCP3OD RC3 LATC3 TRISC3 CCP2OD RC2 LATC2 TRISC2 CCP1OD RC1 LATC1 TRISC1 U2OD RC0 LATC0 TRISC0 U1OD Legend: Shaded cells are not used by PORTC. 2011 Microchip Technology Inc. Preliminary DS39977C-page 189 PIC18F66K80 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (PSPCON<4>). In this mode, the input buffers are ST. For additional information, see Section 11.9 "Parallel Slave Port". RD3 has a CTMU functionality. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. Note: PORTD is unavailable on 28-pin devices. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: EXAMPLE 11-4: CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTD Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs These pins are configured as digital inputs on any device Reset. CLRF LATD Each of the PORTD pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is performed by setting bit, RDPU (PADCFG1<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. MOVLW 0CFh MOVWF TRISD DS39977C-page 190 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 11-7: Pin Name RD0/C1INA/ PSP0 PORTD FUNCTIONS Function RD0 C1INA PSP0 TRIS Setting 0 1 1 x 0 1 C1INB(1) PSP1(1) 1 x 0 1 C2INA PSP2 1 x 0 1 C2INB CTMUI PSP3 1 x x 0 1 ECCP1 0 1 P1A 0 I/O O I I I/O O I I I/O O I I I/O O I I I I/O O I O I O I/O Type DIG ST ANA ST DIG ST ANA ST DIG ST ANA ST DIG ST ANA -- ST DIG ST DIG ST DIG LATD<0> data output. PORTD<0> data input. Comparator 1 Input A. Parallel Slave Port data. LATD<1> data output. PORTD<1> data input. Comparator 1 Input B. Parallel Slave Port data. LATD<2> data output. PORTD<2> data input. Comparator 2 Input A. Parallel Slave Port data. LATD<3> data output. PORTD<3> data input. Comparator 2 Input B. CTMU pulse generator charger for the C2INB comparator input. Parallel Slave Port data. LATD<4> data output. PORTD<4> data input. ECCP1 compare output and ECCP1 PWM output. Takes priority over port data. ECCP1 capture input. ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. Parallel Slave Port data. LATD<5> data output. PORTD<5> data input. ECCP1 Enhanced PWM output, Channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. Parallel Slave Port data. LATD<6> data output. PORTD<6> data input. Asynchronous serial data output (EUSART module); takes priority over port data. Synchronous serial clock output (EUSART module); user must configure as an input. Synchronous serial clock input (EUSART module); user must configure as an input. ECCP1 Enhanced PWM output, Channel C. May be configured for tri-state during Enhanced PWM. Parallel Slave Port data. Description RD1/C1INB/ PSP1 RD1 (1) RD2/C2INA/ PSP2 RD2 RD3/C2INB/ CTMUI/PSP3 RD3 RD4/ECCP1/ P1A/PSP4 RD4 PSP4 RD5/P1B/PSP5 RD5 P1B x 0 1 0 I/O O I O ST DIG ST DIG PSP5 RD6/TX2/CK2 P1C/PSP6 RD6 TX2(1) CK2(1) x 0 1 0 0 1 I/O O I O O I O I/O ST DIG ST DIG DIG ST DIG ST P1C PSP6 Legend: Note 1: 0 x O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment for 40 and 44-pin devices (PIC18F4XK80). 2011 Microchip Technology Inc. Preliminary DS39977C-page 191 PIC18F66K80 FAMILY TABLE 11-7: Pin Name RD7/RX2/DT2/ P1D/PSP7 PORTD FUNCTIONS (CONTINUED) Function RD7 RX2(1) DT2(1) TRIS Setting 0 1 1 1 1 P1D PSP7 0 x I/O O I I O I O I/O I/O Type DIG ST ST DIG ST DIG ST LATD<7> data output. PORTD<7> data input. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (EUSART module); takes priority over port data. Synchronous serial data input (EUSART module); user must configure as an input. ECCP1 Enhanced PWM output, Channel D. May be configured for tri-state during Enhanced PWM. Parallel Slave Port data. Description Legend: Note 1: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment for 40 and 44-pin devices (PIC18F4XK80). TABLE 11-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD LATD TRISD PADCFG1 ODCON ANCON1 RD7 LATD7 TRISD7 RDPU(1) SSPOD -- RD6 LATD6 TRISD6 REPU(1) CCP5OD ANSEL14 RD5 LATD5 TRISD5 RFPU(2) CCP4OD ANSEL13 RD4 LATD4 TRISD4 RGPU(2) CCP3OD ANSEL12 RD3 LATD3 TRISD3 -- CCP2OD ANSEL11 RD2 LATD2 TRISD2 -- CCP1OD ANSEL10 RD1 LATD1 TRISD1 -- U2OD ANSEL9 RD0 LATD0 TRISD0 CTMUDS U1OD ANSEL8 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 28-pin devices, read as `0'. 2: Unimplemented on 28/40/44-pin devices, read as `0'. DS39977C-page 192 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.6 PORTE, TRISE and LATE Registers weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. PORTE is also multiplexed with the Parallel Slave Port address lines. RE1 and RE0 are multiplexed with the Parallel Slave Port (PSP) control signals, WR and RD. PORTE is a seven-bit-wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. Note: PORTE is unavailable on 28-pin devices. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: EXAMPLE 11-5: CLRF PORTE ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTE Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE<1:0> as inputs RE<7:2> as outputs These pins are configured as digital inputs on any device Reset. CLRF LATE Each of the PORTE pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, REPU (PADCFG1<6>). The MOVLW 03h MOVWF TRISE TABLE 11-9: Pin Name RE0/AN5/RD PORTE FUNCTIONS Function RE0 AN5 RD TRIS Setting 0 1 1 x x 0 1 AN6 C1OUT WR 1 0 x x I/O O I I O I O I I O O I O I I O I I O I I I/O Type DIG ST ANA DIG ST DIG ST ANA DIG DIG ST DIG ST ANA DIG ST ST DIG ST ST LATE<0> data output. PORTE<0> data input. A/D Input Channel 5. Default input configuration on POR; does not affect digital output. Parallel Slave Port read strobe pin. Parallel Slave Port read pin. LATE<1> data output. PORTE<1> data input. A/D Input Channel 5. Default input configuration on POR; does not affect digital output. Comparator 1 output; takes priority over port data. Parallel Slave Port write strobe pin. Parallel Slave Port write pin. LATE<2> data output. PORTE<2> data input. A/D Input Channel 7. Default input configuration on POR; does not affect digital output. Comparator 2 output; takes priority over port data. Parallel Slave Port chip select. PORT<3> data input. LATE<4> data output. PORTE<4> data input. CAN bus RX. Description RE1/AN6/ C1OUT/WR RE1 RE2/AN7/ C2OUT/CS RE2 AN7 C2OUT CS 0 1 1 0 x 1 0 1 RE3 RE4/CANRX RE3 RE4(1) CANRX (1,2) 1 Legend: Note 1: 2: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Unavailable for 40 and 44-pin devices (PIC18F4XK0). Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration bit is cleared. 2011 Microchip Technology Inc. Preliminary DS39977C-page 193 PIC18F66K80 FAMILY TABLE 11-9: Pin Name RE5/CANTX PORTE FUNCTIONS (CONTINUED) Function RE5(1) CANTX(1,2) TRIS Setting 0 1 0 0 1 RX2(1) DT2(1) 1 1 1 I/O O I O O I I O I O I O O I I/O Type DIG ST DIG DIG ST ST DIG ST DIG ST DIG DIG ST LATE<5> data output. PORTE<5> data input. CAN bus TX. LATE<6> data output. PORTE<6> data input. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (EUSART module); takes priority over port data. Synchronous serial data input (EUSART module); user must configure as an input. LATE<7> data output. PORTE<7> data input. Asynchronous serial data output (EUSART module); takes priority over port data. Synchronous serial clock output (EUSART module); user must configure as an input. Synchronous serial clock input (EUSART module); user must configure as an input. Description RE6/RX2/DT2 RE6(1) RE7/TX2/CK2 RE7(1) TX2(1) CK2(1) 0 1 0 0 1 Legend: Note 1: 2: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Unavailable for 40 and 44-pin devices (PIC18F4XK0). Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration bit is cleared. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTE LATE TRISE PADCFG1 ANCON0 RE7(1) LATE7 TRISE7 RDPU ANSEL7 RE6(1) LATE6 TRISE6 REPU ANSEL6 RE5(1) LATE5 TRISE5 RFPU(1) ANSEL5 RE4(1) LATE4 TRISE4 RGPU(1) ANSEL4 RE3 -- -- -- ANSEL3 RE2 LATE2 TRISE2 -- ANSEL2 RE1 LATE1 TRISE1 -- ANSEL1 RE0 LATE0 TRISE0 CTMUDS ANSEL0 Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 44-pin devices, read as `0'. DS39977C-page 194 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.7 PORTF, LATF and TRISF Registers Note: PORTF is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On device Resets, pins, RF<7:1>, are configured as analog inputs and are read as `0'. EXAMPLE 11-6: CLRF PORTF ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTF Initialize PORTF by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RF3:RF1 as inputs RF5:RF4 as outputs RF7:RF6 as inputs PORTF is only available on 64-pin devices. CLRF LATF Each of the PORTF pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is done by clearing bit, RFPU (PADCFG1<5>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. MOVLW 0CEh MOVWF TRISF TABLE 11-11: Pin Name RF0/MDMIN PORTF FUNCTIONS(LEGEND:) Function RF0 MDMIN TRIS Setting 0 1 1 0 1 I/O O I I O I O I I O I O I I O I O I O O I I/O Type DIG ST ST DIG ST DIG ST ST DIG ST DIG ST ST DIG ST DIG ST DIG DIG ST LATF<0> data output. PORTF<0> data input. Modulator source input. LATF<1> data output. PORTF<1> data input. LATF<2> data output. PORTF<2> data input. Modulator Carrier Input 1. LATF<3> data output. PORTF<3> data input. LATF<4> data output. PORTF<4> data input. Modulator Carrier Input 2. LATF<5> data output. PORTF<5> data input. LATF<6> data output. PORTF<6> data input. Modulator output. LATF<7> data output. PORTF<7> data input. Description RF1 RF2/MDCIN1 RF1 RF2 MDCIN1 0 1 1 0 1 0 1 RF3 RF4/MDCIN2 RF3 RF4 MDCIN2 1 0 1 RF5 RF6/MDOUT RF5 RF6 MDOUT 0 1 0 0 1 RF7 Legend: RF7 O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTF LATF TRISF PADCFG1 RF7 LATF7 TRISF7 RDPU RF6 LATF6 TRISF6 REPU RF5 LATF5 TRISF5 RFPU(1) RF4 LATF4 TRISF4 RGPU(1) RF3 -- TRISF3 -- RF2 LATF2 TRISF2 -- RF1 LATF1 TRISF1 -- RF0 LATF0 TRISF0 CTMUDS Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTF. Note 1: Unimplemented on 28-pin devices; read as `0'. 2011 Microchip Technology Inc. Preliminary DS39977C-page 195 PIC18F66K80 FAMILY 11.8 PORTG, TRISG and LATG Registers put, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISG and LATG. Note: PORTG is only available on 64-pin devices. PORTG is multiplexed with EUSART and CCP, ECCP, Analog, Comparator and Timer input functions (Table 11-13). When operating as I/O, all PORTG pins have Schmitt Trigger input buffers. The open-drain functionality for the UART can be configured using ODCON. Each of the PORTG pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, RGPU (PADCFG1<4>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an out- EXAMPLE 11-7: CLRF PORTG INITIALIZING PORTG ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as inputs CLRF LATG MOVLW 04h MOVWF TRISG TABLE 11-13: PORTG FUNCTIONS Pin Name RG0/RX1/DT1 Function RG0 RX1 DT1 TRIS Setting 0 1 1 0 1 RG1/CANTX RG1 CANTX RG2/T3CKI RG2 T3CKI(2) RG3/TX1/CK1 RG3 TX1 CK1 0 1 0 0 1 x 0 1 0 0 1 Legend: Note 1: 2: I/O O I I O I O I O O I I O I O O I I/O Type DIG ST ST DIG ST DIG ST DIG DIG ST ST DIG ST DIG DIG ST LATG<0> data output. PORTG<0> data input. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (EUSART module); takes priority over port data. Synchronous serial data input (EUSART module); user must configure as an input. LATG<1> data output. PORTG<1> data input. CAN bus TX. LATG<2> data output. PORTG<2> data input. Timer3 clock input. LATG<3> data output. PORTG<3> data input. Asynchronous serial data output (EUSART module); takes priority over port data. Synchronous serial clock output (EUSART module); user must configure as an input. Synchronous serial clock input (EUSART module); user must configure as an input. Description O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared. Default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set. DS39977C-page 196 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 11-13: PORTG FUNCTIONS (CONTINUED) Pin Name RG4/T0CKI Function RG4 T0CKI(1) Legend: Note 1: 2: TRIS Setting 0 1 x I/O O I I I/O Type DIG ST ST LATG<4> data output. PORTG<4> data input. Timer0 clock input. Description O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared. Default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set. TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTG TRISG PADCFG1 -- -- RDPU -- -- REPU -- -- RFPU(1) RG4 TRISG4 RGPU(1) RG3 TRISG3 -- RG2 TRISG2 -- RG1 TRISG1 -- RG0 TRISG0 CTMUDS Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTG. Note 1: Unimplemented on 28-pin devices. Read as `0'. 2011 Microchip Technology Inc. Preliminary DS39977C-page 197 PIC18F66K80 FAMILY 11.9 Parallel Slave Port FIGURE 11-3: PORTD can function as an 8-bit-wide Parallel Slave Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. The port is asynchronously readable and writable by the external world through the RD control input pin (RE0/AN5/RD) and WR control input pin (RE1/AN6/C1OUT/WR). Note: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus D CK Q The Parallel Slave Port is available only on 40/44-pin and 64-pin devices. WR LATD or PORTD RDx Pin ST Data Latch Q D EN EN TRIS Latch The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an eight-bit latch. Setting bit, PSPMODE, enables port pin, RE0/AN5/RD, to be the RD input, RE1/AN6/C1OUT/WR to be the WR input and RE2/AN7/C2OUT/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (= 111). A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits (PIR1<7> and PSPCON<7>, respectively) are set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit (PSPCON<6>) is set. If the user writes new data to PORTD to set OBF, the data is immediately read out, but the OBF bit is not set. When either the CS or RD line is detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 11-4 and Figure 11-5, respectively. RD PORTD RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read ST ST RD CS WR Chip Select Write ST Note: The I/O pin has protection diodes to VDD and VSS. DS39977C-page 198 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 11-5: R-0 IBF bit 7 Legend: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word had not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as `0' bit 6 bit 5 bit 4 bit 3-0 FIGURE 11-4: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF 2011 Microchip Technology Inc. Preliminary DS39977C-page 199 PIC18F66K80 FAMILY FIGURE 11-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-15: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD LATD TRISD PORTE LATE TRISE PSPCON INTCON PIR1 PIE1 IPR1 PMD1 RD7 LATD7 TRISD7 RE7 LATE7 TRISE7 IBF GIE/GIEH PSPIF PSPIE PSPIP PSPMD RD6 LATD6 TRISD6 RE6 LATE6 TRISE6 OBF PEIE/GIEL ADIF ADIE ADIP CTMUMD RD5 LATD5 TRISD5 RE5 LATE5 TRISE5 IBOV TMR0IE RC1IF RC1IE RC1IP ADCMD RD4 LATD4 TRISD4 RE4 LATE4 TRISE4 PSPMODE INT0IE TX1IF TX1IE TX1IP TMR4MD RD3 LATD3 TRISD3 RE3 -- -- -- RBIE SSPIF SSPIE SSPIP TMR3MD RD2 LATD2 TRISD2 RE2 LATE2 TRISE2 -- TMR0IF TMR1GIF TMR1GIE TMR1GIP TMR2MD RD1 LATD1 TRISD1 RE1 LATE1 TRISE1 -- INT0IF TMR2IF TMR2IE TMR2IP TMR1MD RD0 LATD0 TRISD0 RE0 LATE0 TRISE0 -- RBIF TMR1IF TMR1IE TMR1IP TMR0MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. DS39977C-page 200 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 12.0 Note: DATA SIGNAL MODULATOR The Data Signal Modulator is only available on 64-pin devices (PIC18F6XK80). Using this method, the DSM can generate the following types of key modulation schemes: * Frequency-Shift Keying (FSK) * Phase-Shift Keying (PSK) * On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: * * * * * * * Carrier Synchronization Carrier Source Polarity Select Carrier Source Pin Disable Programmable Modulator Data Modulator Source Pin Disable Modulated Output Polarity Select Slew Rate Control The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module, either internally from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical "AND" operation of both the carrier and modulator signals and then it is provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals: a carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Figure 12-1 shows a simplified block diagram of the Data Signal Modulator peripheral. 2011 Microchip Technology Inc. Preliminary DS39977C-page 201 PIC18F66K80 FAMILY FIGURE 12-1: MDCH<3:0> VSS MDCIN1 MDCIN2 REFO Clock ECCP1 CCP2 CCP3 CCP4 CCP5 Reserved No Channel Selected MDMS<3:0> MDBIT MDMIN SSP (SDO) EUSART1 (TX) EUSART2 (TX) ECCP1 CCP2 CCP3 CCP4 CCP5 Reserved No Channel Selected 0000 0001 0010 0011 0100 0101 0110 MOD 0111 1000 1001 1010 * * 1111 D MDCL<3:0> VSS MDCIN1 MDCIN2 REFO Clock ECCP1 CCP2 CCP3 CCP4 CCP5 Reserved No Channel Selected 0000 0001 0010 0011 0100 0101 CARL 0110 0111 1000 1001 ** 1111 SYNC Q 1 MDEN 0000 0001 0010 0011 0100 0101 CARH 0110 0111 1000 1001 ** 1111 EN Data Signal Modulator SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCHPOL D SYNC Q 1 0 MDCHSYNC MDOUT MDOPOL MDOE 0 MDCLSYNC MDCLPOL DS39977C-page 202 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 12.1 DSM Operation 12.3 Carrier Signal Sources The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. The values used to select the carrier high, carrier low and modulator sources held by the Modulation Source, Modulation High Carrier and Modulation Low Carrier Control registers are not affected when the MDEN bit is cleared, and the DSM module is disabled. The values inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be selected when the MDEN bit is set and the DSM module is again enabled and active. The modulated output signal can be disabled without shutting down the DSM module. The DSM module will remain active and continue to mix signals, but the output value will not be sent to the MDOUT pin. During the time that the output is disabled, the MDOUT pin will remain low. The modulated output can be disabled by clearing the MDOE bit in the MDCON register. The carrier high signal and carrier low signal can be supplied from the following sources: * * * * * * * * CCP1 Signal CCP2 Signal CCP3 Signal CCP4 Signal Reference Clock Module Signal External Signal on MDCIN1 Pin (RF2/MDCIN1) External Signal on MDCIN2 Pin (RF4/MDCIN2) VSS The carrier high signal is selected by configuring the MDCH<3:0> bits in the MDCARH register. The carrier low signal is selected by configuring the MDCL<3:0> bits in the MDCARL register. 12.4 Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 12-1 through Figure 12-5 show timing diagrams of using various synchronization methods. 12.2 Modulator Signal Sources The modulator signal can be supplied from the following sources: * * * * * * * * * * ECCP1 Signal CCP2 Signal CCP3 Signal CCP4 Signal CCP5 Signal MSSP SDO Signal (SPI mode only) EUSART1 TX1 Signal EUSART2 TX2 Signal External Signal on MDMIN Pin (RF0/MDMIN) MDBIT bit in the MDCON Register The modulator signal is selected by configuring the MDSRC<3:0> bits in the MDSRC register. 2011 Microchip Technology Inc. Preliminary DS39977C-page 203 PIC18F66K80 FAMILY FIGURE 12-2: Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 ON-OFF KEYING (OOK) SYNCHRONIZATION EXAMPLE 12-1: Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0) CARH CARL CARH CARL FIGURE 12-3: Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) CARH both CARL CARH both CARL DS39977C-page 204 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 12-4: Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State CARH CARL CARH CARL CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1) FIGURE 12-5: Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1) Falling edges used to sync CARH CARL CARH CARL 2011 Microchip Technology Inc. Preliminary DS39977C-page 205 PIC18F66K80 FAMILY 12.5 Carrier Source Polarity Select 12.8 Modulator Source Pin Disable The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register. The modulator source default connection to a pin can be disabled by setting the MDSODIS bit in the MDSRC register. 12.9 Modulated Output Polarity 12.6 Carrier Source Pin Disable The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the MDCON register. Some peripherals assert control over their corresponding output pin when they are enabled. For example, when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. This default connection to a pin can be disabled by setting the MDCHODIS bit in the MDCARH register for the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source. 12.10 Slew Rate Control When modulated data streams of 20 MHz or greater are required, the slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. 12.7 Programmable Modulator Data 12.11 Operation In Sleep Mode The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep if the Carrier and Modulator input sources are also still operable during Sleep. The MDBIT of the MDCON register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation. 12.12 Effects of a Reset Upon any device Reset, the data signal modulator module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. DS39977C-page 206 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 12-1: R/W-0 MDEN bit 7 Legend: MDCON: MODULATION CONTROL REGISTER R/W-0 MDOE R/W-1 MDSLR R/W-0 MDOPOL R/W-0 MDO U-0 -- U-0 -- R/W-0 MDBIT bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted MDO: Modulator Output bit Displays the current output value of the modulator module.(2) Unimplemented: Read as `0' MDBIT: Modulator Source Input bit Allows software to manually set modulation source input to module.(1) bit 6 bit 5 bit 4 bit 3 bit 2-1 bit 0 Note 1: 2: The MDBIT must be selected as the modulation source in the MDSRC register for this operation. The modulated output frequency can be greater and asynchronous from the clock that updates this register bit. The bit value may not be valid for higher speed modulator or carrier signals. 2011 Microchip Technology Inc. Preliminary DS39977C-page 207 PIC18F66K80 FAMILY REGISTER 12-2: R/W-x MDSODIS bit 7 Legend: MDSRC: MODULATION SOURCE CONTROL REGISTER U-0 -- U-0 -- U-0 -- R/W-x MDSRC3 R/W-x MDSRC2 R/W-x MDSRC1 R/W-x MDSRC0 bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MDSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled Unimplemented: Read as `0' MDSRC<3:0> Modulation Source Selection bits 1111-1010 = Reserved; no channel connected 1001 = CCP5 output (PWM Output mode only) 1000 = CCP4 output (PWM Output mode only) 0111 = CCP3 output (PWM Output mode only) 0110 = CCP2 output (PWM Output mode only) 0101 = ECCP1 output (PWM Output mode only) 0100 = EUSART2 TX output 0011 = EUSART1 TX output 0010 = MSSP SDO output 0001 = MDMIN port pin 0000 = MDBIT bit of the MDCON register is the modulation source bit 6-4 bit 3-0 DS39977C-page 208 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 12-3: R/W-x MDCHODIS bit 7 Legend: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x R/W-x MDCHSYNC U-0 -- R/W-x MDCH3(1) R/W-x MDCH2(1) R/W-x MDCH1(1) R/W-x MDCH0(1) bit 0 MDCHPOL R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator output is not synchronized to the high time carrier signal(1) Unimplemented: Read as `0' MDCH<3:0> Modulator Data High Carrier Selection bits(1) 1111-1001 = Reserved 1000 = CCP5 output (PWM Output mode only) 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = ECCP1 output (PWM Output mode only) 0011 = Reference clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS bit 6 bit 5 bit 4 bit 3-0 Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. 2011 Microchip Technology Inc. Preliminary DS39977C-page 209 PIC18F66K80 FAMILY REGISTER 12-4: R/W-0 MDCLODIS bit 7 Legend: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x R/W-x MDCLSYNC U-0 -- R/W-x MDCL3(1) R/W-x MDCL2(1) R/W-x MDCL1(1) R/W-x MDCL0(1) bit 0 MDCLPOL R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator output is not synchronized to the low time carrier signal(1) Unimplemented: Read as `0' MDCL<3:0> Modulator Data High Carrier Selection bits(1) 1111-1001 = Reserved 1000 = CCP5 output (PWM Output mode only) 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = ECCP1 output (PWM Output mode only) 0011 = Reference clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS bit 6 bit 5 bit 4 bit 3-0 Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. TABLE 12-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MDCARH MDCHODIS MDCARL MDCON MDSRC PMD2 MDCLODIS MDEN MDSODIS -- MDCHPOL MDCLPOL MDOE -- -- MDCHSYNC MDCLSYNC MDSLR -- -- -- -- MDOPOL -- -- MDCH3 MDCL3 MDO MDSRC3 MODMD MDCH2 MDCL2 -- MDSRC2 ECANMD MDCH1 MDCL1 -- MDSRC1 CMP2MD MDCH0 MDCL0 MDBIT MDSRC0 CMP1MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used in the Data Signal Modulator mode. DS39977C-page 210 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 13.0 TIMER0 MODULE The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-bit or 16-bit modes * Readable and writable registers * Dedicated 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt-on-overflow The T0CON register (Register 13-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. Figure 13-1 provides a simplified block diagram of the Timer0 module in 8-bit mode. Figure 13-2 provides a simplified block diagram of the Timer0 module in 16-bit mode. REGISTER 13-1: R/W-1 TMR0ON bit 7 Legend: T0CON: TIMER0 CONTROL REGISTER R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0 R/W-1 T08BIT R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is not assigned. Timer0 clock input bypasses prescaler 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value bit 6 bit 5 bit 4 bit 3 bit 2-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 211 PIC18F66K80 FAMILY 13.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 13.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising edge or falling edge of the T0CKI pin. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 13.2 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0, which is not directly readable nor writable. (See Figure 13-2.) TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. FIGURE 13-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Sync with Internal Clocks (2 TCY Delay) 8 8 Internal Data Bus TMR0L Set TMR0IF on Overflow T0CKI Pin T0SE T0CS T0PS<2:0> PSA Programmable Prescaler 3 0 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 13-2: FOSC/4 TIMER0 BLOCK DIAGRAM (16-BIT MODE) 0 1 1 Sync with Internal Clocks (2 TCY Delay) Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus TMR0L TMR0 High Byte 8 Set TMR0IF on Overflow T0CKI Pin T0SE T0CS T0PS<2:0> PSA Programmable Prescaler 3 0 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39977C-page 212 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 13.3 Prescaler 13.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256, in power-of-two increments, are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (for example, CLRF TMR0, MOVWF TMR0, BSF TMR0) clear the prescaler count. Note: SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution. 13.4 Timer0 Interrupt Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before reenabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine (ISR). Since Timer0 is shutdown in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. TABLE 13-1: Name REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0L TMR0H INTCON T0CON PMD1 Timer0 Register Low Byte Timer0 Register High Byte GIE/GIEH TMR0ON PSPMD PEIE/GIEL T08BIT CTMUMD TMR0IE T0CS ADCMD INT0IE T0SE TMR4MD RBIE PSA TMR3MD TMR0IF T0PS2 TMR2MD INT0IF T0PS1 TMR1MD RBIF T0PS0 TMR0MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Timer0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 213 PIC18F66K80 FAMILY NOTES: DS39977C-page 214 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 14.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR1H and TMR1L) * Selectable clock source (internal or external) with device clock or SOSC oscillator internal options * Interrupt-on-overflow * Reset on ECCP Special Event Trigger * Timer with gated control Figure 14-1 displays a simplified block diagram of the Timer1 module. The module derives its clocking source from either the secondary oscillator or from an external digital source. If using the secondary oscillator, there are the additional options for low-power, high-power and external, digital clock source. Timer1 is controlled through the T1CON Control register (Register 14-1). It also contains the Timer1 Oscillator Enable bit (SOSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). The FOSC clock source should not be used with the ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 14-1: R/W-0 TMR1CS1 bit 7 Legend: T1CON: TIMER1 CONTROL REGISTER R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 SOSCEN R/W-0 TMR1CS0 R/W-0 T1SYNC R/W-0 RD16 R/W-0 TMR1ON bit 0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR1CS<1:0>: Timer1 Clock Source Select bits 10 = Timer1 clock source is either from pin or oscillator, depending on the SOSCEN bit: SOSCEN = 0: External clock is from the T1CKI pin (on the rising edge). SOSCEN = 1: Depending on the SOSCSEL Configuration bit, the clock source is either a crystal oscillator on SOSCI/SOSCO or an internal digital clock from the SCLKI pin. 01 = Timer1 clock source is system clock (FOSC)(1) 00 = Timer1 clock source is instruction clock (FOSC/4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value SOSCEN: SOSC Oscillator Enable bit 1 = SOSC enabled and available for Timer1 0 = SOSC disabled for Timer1 The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit TMR1CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS<1:0> = 0x: This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1x. bit 5-4 bit 3 bit 2 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. 2011 Microchip Technology Inc. Preliminary DS39977C-page 215 PIC18F66K80 FAMILY REGISTER 14-1: bit 1 T1CON: TIMER1 CONTROL REGISTER (CONTINUED) RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 bit 0 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. DS39977C-page 216 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 14.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register 14-2, is used to control the Timer1 gate. REGISTER 14-2: R/W-0 TMR1GE bit 7 Legend: T1GCON: TIMER1 GATE CONTROL REGISTER(1) R/W-0 T1GTM R/W-0 T1GSPM R/W-0 T1GGO/T1DONE R-x T1GVAL R/W-0 T1GSS1 R/W-0 T1GSS0 bit 0 R/W-0 T1GPOL R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single Pulse mode is disabled T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit 1 = Timer1 gate single pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by Timer1 Gate Enable (TMR1GE) bit. T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR2 to match PR2 output 00 = Timer1 gate pin bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: Programming the T1GCON prior to T1CON is recommended. 2011 Microchip Technology Inc. Preliminary DS39977C-page 217 PIC18F66K80 FAMILY 14.2 Timer1 Operation 14.3.2 EXTERNAL CLOCK SOURCE The Timer1 module is an 8 or 16-bit incrementing counter that is accessed through the TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter. It increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. When SOSC is selected as Crystal mode (by SOSCSEL), the RC1/SOSCI and RC0/SOSCO/SCLKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external, 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: 14.3 Clock Source Selection The TMR1CS<1:0> and SOSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 14-1 displays the clock source selections. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * Timer1 is enabled after POR Reset * Write to TMR1H or TMR1L * Timer1 is disabled * Timer1 is disabled (TMR1ON = 0) When T1CKI is high, Timer1 is enabled (TMR1ON = 1) when T1CKI is low. 14.3.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. TABLE 14-1: TMR1CS1 0 0 1 1 TIMER1 CLOCK SOURCE SELECTION TMR1CS0 1 0 0 0 SOSCEN x x 0 1 Clock Source Clock Source (FOSC) Instruction Clock (FOSC/4) External Clock on T1CKI Pin Oscillator Circuit on SOSCI/SOSCO Pins DS39977C-page 218 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 14-1: T1GSS<1:0> T1G From TMR2 Match PR2 From Comparator 1 Output From Comparator 2 Output T1GSPM T1G_IN 0 10 D 11 TMR1ON T1GPOL Set Flag bit, TMR1IF, on Overflow T1GTM TMR1GE TMR1ON TMR1(2) TMR1H TMR1L Q EN D T1CLK 0 Synchronized Clock Input CK R Q Q 1 Single Pulse Acq. Control T1GGO/T1DONE 1 0 T1GVAL Q1 D EN Interrupt det Q TIMER1 BLOCK DIAGRAM 00 01 Data Bus RD T1GCON Set TMR1GIF 1 TMR1CS<1:0> SOSCO/SCLKI OUT(4) SOSC SOSCI EN 0 T1CON.SOSCEN T3CON.SOSCEN SOSCGO SCS<1:0> = 01 (1) T1SYNC 10 Synchronize(3) det 1 FOSC Internal Clock FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 2 T1CKPS<1:0> FOSC/2 Internal Clock 01 00 Sleep Input T1CKI Note 1: 2: 3: 4: ST Buffer is high-speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits. 2011 Microchip Technology Inc. Preliminary DS39977C-page 219 PIC18F66K80 FAMILY 14.4 Timer1 16-Bit Read/Write Mode FIGURE 14-2: Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits at once to both the high and low bytes of Timer1. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. EXTERNAL COMPONENTS FOR THE SOSC OSCILLATOR PIC18F66K80 SOSCI XTAL 32.768 kHz SOSCO C1 12 pF C2 12 pF Note: See the Notes with Table 14-2 for additional information about capacitor selection. TABLE 14-2: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4,5) Freq. C1 C2 Oscillator Type 14.5 SOSC Oscillator LP Note 1: 2: 32 kHz 12 pF(1) 12 pF(1) An on-chip crystal oscillator circuit is incorporated between pins, SOSCI (input) and SOSCO (amplifier output). It can be enabled one of these ways: * Setting the SOSCEN bit in either the T1CON or T3CON register (TxCON<3>) * Setting the SOSCGO bit in the OSCCON2 register (OSCCON2<3>) * Setting the SCS bits to secondary clock source in the OSCCON register (OSCCON<1:0> = 01) The SOSCGO bit is used to warm up the SOSC so that it is ready before any peripheral requests it. The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all powermanaged modes. The circuit for a typical low-power oscillator is depicted in Figure 14-2. Table 14-2 provides the capacitor selection for the SOSC oscillator. The user must provide a software time delay to ensure proper start-up of the SOSC oscillator. Microchip suggests these values as a starting point in validating the oscillator circuit. Higher capacitance increases the stability of the oscillator, but also increases the start-up time. Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. Capacitor values are for design guidance only. Values listed would be typical of a CL = 10 pF rated crystal, when SOSCSEL = 11. Incorrect capacitance value may result in a frequency not meeting the crystal manufacturer's tolerance specification. 3: 4: 5: The SOSC crystal oscillator drive level is determined based on the SOSCSEL (CONFIG1L<4:3>) Configuration bits. The Higher Drive Level mode, SOSCSEL<1:0> = 11, is intended to drive a wide variety of 32.768 kHz crystals with a variety of load capacitance (CL) ratings. The Lower Drive Level mode is highly optimized for extremely low-power consumption. It is not intended to drive all types of 32.768 kHz crystals. In the Low Drive Level mode, the crystal oscillator circuit may not work correctly if excessively large discrete capacitors are placed on the SOSCO and SOSCI pins. This mode is designed to work only with discrete capacitances of approximately 3 pF-10 pF on each pin. Crystal manufacturers usually specify a CL (load capacitance) rating for their crystals. This value is related to, but not necessarily the same as, the values that should be used for C1 and C2 in Figure 14-2. DS39977C-page 220 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY For more details on selecting the optimum C1 and C2 for a given crystal, see the crystal manufacture's applications information. The optimum value depends in part on the amount of parasitic capacitance in the circuit, which is often unknown. For that reason, it is highly recommended that thorough testing and validation of the oscillator be performed after values have been selected. FIGURE 14-3: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 14.5.1 USING SOSC AS A CLOCK SOURCE The SOSC oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS<1:0> (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode and both the CPU and peripherals are clocked from the SOSC oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 4.0 "Power-Managed Modes". Whenever the SOSC oscillator is providing the clock source, the SOSC System Clock Status flag, SOSCRUN (OSCCON2<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source currently being used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the SOSC oscillator fails while providing the clock, polling the SOCSRUN bit will indicate whether the clock is being provided by the SOSC oscillator or another source. RC0 RC1 RC2 Note: Not drawn to scale. In the Low Drive Level mode, SOSCSEL<1:0> = 01, it is critical that RC2 I/O pin signals be kept away from the oscillator circuit. Configuring RC2 as a digital output, and toggling it, can potentially disturb the oscillator circuit, even with a relatively good PCB layout. If possible, either leave RC2 unused or use it as an input pin with a slew rate limited signal source. If RC2 must be used as a digital output, it may be necessary to use the Higher Drive Level Oscillator mode (SOSCSEL<1:0> = 11) with many PCB layouts. Even in the Higher Drive Level mode, careful layout procedures should still be followed when designing the oscillator circuit. In addition to dV/dt induced noise considerations, it is important to ensure that the circuit board is clean. Even a very small amount of conductive, soldering flux residue can cause PCB leakage currents that can overwhelm the oscillator circuit. 14.5.2 SOSC OSCILLATOR LAYOUT CONSIDERATIONS The SOSC oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. This is especially true when the oscillator is configured for extremely Low-Power mode, SOSCSEL<1:0> (CONFIG1L<4:3>) = 01. The oscillator circuit, displayed in Figure 14-2, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator, it may help to have a grounded guard ring around the oscillator circuit. The guard, as displayed in Figure 14-3, could be used on a single-sided PCB or in addition to a ground plane. (Examples of a high-speed circuit include the ECCP1 pin, in Output Compare or PWM mode, or the primary oscillator, using the OSC2 pin.) 14.6 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 2011 Microchip Technology Inc. Preliminary DS39977C-page 221 PIC18F66K80 FAMILY 14.7 Resetting Timer1 Using the ECCP Special Event Trigger 14.8 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using the Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. Timer1 gate can also be driven by multiple selectable sources. If ECCP modules are configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCP1M<3:0> = 1011), this signal will reset Timer1. The trigger from ECCP will also start an A/D conversion if the A/D module is enabled. (For more information, see Section 20.3.4 "Special Event Trigger".) To take advantage of this feature, the module must be configured as either a timer or a synchronous counter. When used this way, the CCPR1H:CCPR1L register pair effectively becomes a Period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: 14.8.1 TIMER1 GATE COUNT ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit (T1GCON<6>). When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 14-4 for timing details. The Special Event Trigger from the ECCP module will only clear the TMR1 register's content, but not set the TMR1IF interrupt flag bit (PIR1<0>). TABLE 14-3: T1CLK() TIMER1 GATE ENABLE SELECTIONS Timer1 Operation T1GPOL T1G Pin (T1GCON<6>) 0 0 1 1 0 1 0 1 Counts Holds Count Holds Count Counts The clock on which TMR1 is running. For more information, see Figure 14-1. Note: The CCP and ECCP modules use Timers, 1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRS register. For more details, see Register 20-2 and Register 19-2. DS39977C-page 222 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 14-4: TMR1GE T1GPOL T1G_IN TIMER1 GATE COUNT ENABLE MODE T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 14.8.2 TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four sources. Source selection is controlled by the T1GSSx (T1GCON<1:0>) bits (see Table 14-4). Depending on T1GPOL, Timer1 increments differently when TMR2 matches PR2. When T1GPOL = 1, Timer1 increments for a single instruction cycle following a TMR2 match with PR2. When T1GPOL = 0, Timer1 increments continuously except for the cycle following the match when the gate signal goes from low-to-high. TABLE 14-4: T1GSS<1:0> 00 01 10 11 TIMER1 GATE SOURCES Timer1 Gate Source 14.8.2.3 Comparator 1 Output Gate Operation Timer1 Gate Pin TMR2 to Match PR2 (TMR2 increments to match PR2) Comparator 1 Output (comparator logic high output) Comparator 2 Output (comparator logic high output) The output of Comparator 1 can be internally supplied to the Timer1 gate circuitry. After setting up Comparator 1 with the CM1CON register, Timer1 will increment depending on the transitions of the CMP1OUT (CMSTAT<6>) bit. 14.8.2.4 Comparator 2 Output Gate Operation The polarity for each available source is also selectable, controlled by the T1GPOL bit (T1GCON<6>). 14.8.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. The output of Comparator 2 can be internally supplied to the Timer1 gate circuitry. After setting up Comparator 2 with the CM2CON register, Timer1 will increment depending on the transitions of the CMP2OUT (CMSTAT<7>) bit. 14.8.2.2 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. The pulse will remain high for one instruction cycle and will return back to a low state until the next match. 2011 Microchip Technology Inc. Preliminary DS39977C-page 223 PIC18F66K80 FAMILY 14.8.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure 14-5.) The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting. The Timer1 Gate Toggle mode is enabled by setting the T1GTM bit (T1GCON<5>). When T1GTM is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. FIGURE 14-5: TMR1GE T1GPOL TIMER1 GATE TOGGLE MODE T1GTM T1G_IN T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS39977C-page 224 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 14.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is enabled by setting the T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE bit (T1GCON<3>). The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/ T1DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/T1DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/T1DONE bit. (For timing details, see Figure 14-6.) Simultaneously enabling the Toggle and Single Pulse modes will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. (For timing details, see Figure 14-7.) 14.8.5 TIMER1 GATE VALUE STATUS When the Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit (T1GCON<2>). This bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). FIGURE 14-6: TMR1GE T1GPOL T1GSPM T1GGO/ T1DONE T1G_IN TIMER1 GATE SINGLE PULSE MODE Set by Software Counting Enabled on Rising Edge of T1G Cleared by Hardware on Falling Edge of T1GVAL T1CKI T1GVAL Timer1 N N+1 N+2 2011 Microchip Technology Inc. Preliminary DS39977C-page 225 PIC18F66K80 FAMILY FIGURE 14-7: TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ T1DONE T1G_IN Set by Software Counting Enabled on Rising Edge of T1G Cleared by Hardware on Falling Edge of T1GVAL TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 TABLE 14-5: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON T1GCON OSCCON2 PMD1 GIE/GIEH PSPIF PSPIE PSPIP PEIE/GIEL ADIF ADIE ADIP TMR0IE RC1IF RC1IE RC1IP INT0IE TX1IF TX1IE TX1IP RBIE SSPIF SSPIE SSPIP TMR0IF TMR1GIF TMR1GIE TMR1GIP INT0IF TMR2IF TMR2IE TMR2IP RBIF TMR1IF TMR1IE TMR1IP Timer1 Register Low Byte Timer1 Register High Byte TMR1CS1 TMR1GE -- PSPMD TMR1CS0 T1CKPS1 T1GPOL SOSCRUN CTMUMD T1GTM -- ADCMD T1CKPS0 T1GSPM SOSCDRV TMR4MD SOSCEN T1GGO/ T1DONE SOSCGO TMR3MD T1SYNC T1GVAL -- TMR2MD RD16 T1GSS1 MFIOFS TMR1MD TMR1ON T1GSS0 MFIOSEL TMR0MD Legend: Shaded cells are not used by the Timer1 module. DS39977C-page 226 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 15.0 TIMER2 MODULE The Timer2 module incorporates the following features: * Eight-bit Timer and Period registers (TMR2 and PR2, respectively) * Both registers are readable and writable * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2 to PR2 match * Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register (Register 15-1) that enables or disables the timer, and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 15-1. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler. (See Section 15.2 "Timer2 Interrupt".) The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: * A write to the TMR2 register * A write to the T2CON register * Any device Reset - Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR) TMR2 is not cleared when T2CON is written. Note: 15.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A four-bit counter/prescaler on the clock input gives the prescale options of direct input, divide-by-4 or divide-by-16. These are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>). The CCP and ECCP modules use Timers, 1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRS register. For more details, see Register 20-2 and Register 19-2. REGISTER 15-1: U-0 -- bit 7 Legend: T2CON: TIMER2 CONTROL REGISTER R/W-0 T2OUTPS2 R/W-0 T2OUTPS1 R/W-0 T2OUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0 R/W-0 T2OUTPS3 R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 2 bit 1-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 227 PIC18F66K80 FAMILY 15.2 Timer2 Interrupt 15.3 Timer2 Output Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the four-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag, which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscaler options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). The unscaled output of TMR2 is available primarily to the ECCP modules, where it is used as a time base for operations in PWM mode. Timer2 can optionally be used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 21.0 "Master Synchronous Serial Port (MSSP) Module". FIGURE 15-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T2OUTPS<3:0> T2CKPS<1:0> 2 Set TMR2IF TMR2 Output (to PWM or MSSP) FOSC/4 1:1, 1:4, 1:16 Prescaler Reset TMR2 8 TMR2/PR2 Match Comparator PR2 8 8 Internal Data Bus TABLE 15-1: Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 TMR2 T2CON PR2 PMD1 GIE/GIEH PSPIF PSPIE PSPIP PEIE/GIEL ADIF ADIE ADIP T2OUTPS3 CTMUMD TMR0IE RC1IF RC1IE RC1IP INT0IE TX1IF TX1IE TX1IP RBIE SSPIF SSPIE SSPIP T2OUTPS0 TMR3MD TMR0IF TMR1GIF TMR1GIE TMR1GIP TMR2ON TMR2MD INT0IF TMR2IF TMR2IE TMR2IP T2CKPS1 TMR1MD RBIF TMR1IF TMR1IE TMR1IP T2CKPS0 TMR0MD Timer2 Register -- PSPMD T2OUTPS2 T2OUTPS1 ADCMD TMR4MD Timer2 Period Register Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. DS39977C-page 228 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 16.0 TIMER3 MODULE The Timer3 timer/counter modules incorporate these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable eight-bit registers (TMR3H and TMR3L) * Selectable clock source (internal or external) with device clock or SOSC oscillator internal options * Interrupt-on-overflow * Module Reset on ECCP Special Event Trigger A simplified block diagram of the Timer3 module is shown in Figure 16-1. The Timer3 module is controlled through the T3CON register (Register 16-1). It also selects the clock source options for the ECCP modules. (For more information, see Section 20.1.1 "ECCP Module and Timer Resources".) The FOSC clock source should not be used with the ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 16-1: R/W-0 TMR3CS1 bit 7 T3CON: TIMER3 CONTROL REGISTER R/W-0 T3CKPS1 R/W-0 T3CKPS0 R/W-0 SOSCEN R/W-0 T3SYNC R/W-0 RD16 R/W-0 TMR3ON bit 0 R/W-0 TMR3CS0 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-6 bit 5-4 bit 3 bit 2 bit 1 bit 0 TMR3CS<1:0>: Timer3 Clock Source Select bits 10 = Timer3 clock source is either from pin or oscillator, depending on the SOSCEN bit: SOSCEN = 0: External clock is from T3CKI pin (on the rising edge). SOSCEN = 1: Depending on the SOSCSEL Configuration bit, the clock source is either a crystal oscillator on SOSCI/SOSCO or an internal digital clock from the SCLKI pin. 01 = Timerx clock source is system clock (FOSC)(1) 00 = Timerx clock source is instruction clock (FOSC/4) T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value SOSCEN: SOSC Oscillator Enable bit 1 = SOSC enabled and available for Timer3 0 = SOSC disabled and available for Timer3 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS<1:0> = 0x: This bit is ignored; Timer3 uses the internal clock. RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two eight-bit operations TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. 2011 Microchip Technology Inc. Preliminary DS39977C-page 229 PIC18F66K80 FAMILY 16.1 Timer3 Gate Control Register The Timer3 Gate Control register (T3GCON), provided in Register 14-2, is used to control the Timer3 gate. REGISTER 16-2: R/W-0 TMR3GE bit 7 Legend: T3GCON: TIMER3 GATE CONTROL REGISTER(1) R/W-0 T3GTM R/W-0 T3GSPM R/W-0 T3GGO/T3DONE R-x T3GVAL R/W-0 T3GSS1 R/W-0 T3GSS0 bit 0 R/W-0 T3GPOL R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR3GE: Timer3 Gate Enable bit If TMR3ON = 0: This bit is ignored. If TMR3ON = 1: 1 = Timer3 counting is controlled by the Timer3 gate function 0 = Timer3 counts regardless of Timer3 gate function T3GPOL: Timer3 Gate Polarity bit 1 = Timer3 gate is active-high (Timer3 counts when gate is high) 0 = Timer3 gate is active-low (Timer3 counts when gate is low) T3GTM: Timer3 Gate Toggle Mode bit 1 = Timer3 Gate Toggle mode is enabled. 0 = Timer3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer3 gate flip-flop toggles on every rising edge. T3GSPM: Timerx Gate Single Pulse Mode bit 1 = Timer3 Gate Single Pulse mode is enabled and is controlling Timer3 gate 0 = Timer3 Gate Single Pulse mode is disabled T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit 1 = Timer3 gate single pulse acquisition is ready, waiting for an edge 0 = Timer3 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T3GSPM is cleared. T3GVAL: Timer3 Gate Current State bit Indicates the current state of the Timerx gate that could be provided to TMR3H:TMR3L. Unaffected by Timerx Gate Enable (TMR3GE) bit. T3GSS<1:0>: Timer3 Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR4 to match PR4 output 00 = Timer3 gate pin Watchdog Timer oscillator is turned on if TMR3GE = 1, regardless of the state of TMR3ON. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: Programming the T3GCON prior to T3CON is recommended. DS39977C-page 230 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 16-3: U-0 -- bit 7 Legend: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0 U-0 -- RW-0 SOSCDRV(1) R/W-0 SOSCGO U-0 -- R-0 MFIOFS R/W-0 MFIOSEL bit 0 SOSCRUN R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC Unimplemented: Read as `0' SOSCDRV: Secondary Oscillator Drive Control bit(1) 1 = High-power SOSC circuit selected 0 = Low/high-power select is done via the SOSCSEL<1:0> Configuration bits SOSCGO: Oscillator Start Control bit 1 = Oscillator is running even if no other sources are requesting it 0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.) Unimplemented: Read as `0' MFIOFS: MF-INTOSC Frequency Stable bit 1 = MF-INTOSC is stable 0 = MF-INTOSC is not stable MFIOSEL: MF-INTOSC Select bit 1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MF-INTOSC is not used bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect. 2011 Microchip Technology Inc. Preliminary DS39977C-page 231 PIC18F66K80 FAMILY 16.2 * * * * Timer3 Operation Timer3 can operate in these modes: Timer Synchronous Counter Asynchronous Counter Timer with Gated Control The operating mode is determined by the clock select bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits are cleared (= 00), Timer3 increments on every internal instruction cycle (FOSC/4). When TMR3CSx = 01, the Timer3 clock source is the system clock (FOSC), and when it is `10', Timer3 works as a counter from the external clock from the T3CKI pin (on the rising edge after the first falling edge) or the SOSC oscillator. FIGURE 16-1: T3GSS<1:0> T3G From TMR4 Match PR4 From Comparator 1 Output From Comparator 2 Output TIMER3 BLOCK DIAGRAM 00 01 10 D 11 TMR3ON T3GPOL Set Flag bit, TMR3IF, on Overflow T3GTM CK R Q Q 1 T3G_IN 0 T3GSPM 0 T3GVAL Single Pulse Acq. Control T3GGO/T3DONE 1 Q1 D EN Q RD T3GCON Set TMR3GIF Data Bus Interrupt det TMR3GE TMR3ON TMR3(2) TMR3H TMR3L Q EN D T3CLK 0 Synchronized Clock Input 1 TMR3CS<1:0> SOSCO/SCLKI OUT(4) SOSC SOSCI EN 0 T1CON.SOSCEN T3CON.SOSCEN SOSCGO SCS<1:0> = 01 (1) T3SYNC Prescaler 1, 2, 4, 8 10 2 T3CKPS<1:0> 01 FOSC/2 Internal Clock Sleep Input Synchronize(3) det 1 FOSC Internal Clock FOSC/4 Internal Clock 00 T3CKI Note 1: 2: 3: 4: ST Buffer is high-speed type when using T3CKI. Timer3 registers increment on rising edge. Synchronization does not operate while in Sleep. The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits. DS39977C-page 232 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 16.3 Timer3 16-Bit Read/Write Mode 16.4 Timer3 can be configured for 16-bit reads and writes (see Figure 16.3). When the RD16 control bit (T3CON<1>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register. This provides users with the ability to accurately read all 16 bits of Timer3 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L. This allows users to write all 16 bits to both the high and low bytes of Timer3 at once. The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. Using the SOSC Oscillator as the Timer3 Clock Source The SOSC internal oscillator may be used as the clock source for Timer3. It can be enabled in one of these ways: * Setting the SOSCEN bit in either the T1CON or T3CON register (TxCON<3>) * Setting the SOSCGO bit in the OSCCON2 register (OSCCON2<3>) * Setting the SCS bits to secondary clock source in the OSCCON register (OSCCON<1:0> = 01) The SOSCGO bit is used to warm up the SOSC so that it is ready before any peripheral requests it. To use it as the Timer3 clock source, the TMR3CSx bits must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The SOSC oscillator is described in Section 14.5 "SOSC Oscillator". 2011 Microchip Technology Inc. Preliminary DS39977C-page 233 PIC18F66K80 FAMILY 16.5 Timer3 Gates TABLE 16-1: T3CLK() Timer3 can be configured to count freely or the count can be enabled and disabled using the Timer3 gate circuitry. This is also referred to as the Timer3 gate count enable. The Timer3 gate can also be driven by multiple selectable sources. TIMER3 GATE ENABLE SELECTIONS Timer3 Operation T3GPOL T3G Pin (T3GCON<6>) 0 0 1 1 0 1 0 1 Counts Holds Count Holds Count Counts 16.5.1 TIMER3 GATE COUNT ENABLE The Timer3 Gate Enable mode is enabled by setting the TMR3GE bit (TxGCON<7>). The polarity of the Timer3 Gate Enable mode is configured using the T3GPOL bit (T3GCON<6>). When Timer3 Gate Enable mode is enabled, Timer3 will increment on the rising edge of the Timer3 clock source. When Timer3 Gate Enable mode is disabled, no incrementing will occur and Timer3 will hold the current count. See Figure 16-2 for timing details. The clock on which TMR3 is running. For more information, see T3CLK in Figure 16-1. FIGURE 16-2: TMR3GE TIMER3 GATE COUNT ENABLE MODE T3GPOL T3G_IN T3CKI T3GVAL Timer3 N N+1 N+2 N+3 N+4 DS39977C-page 234 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 16.5.2 TIMER3 GATE SOURCE SELECTION The Timer3 gate source can be selected from one of four different sources. Source selection is controlled by the T3GSS<1:0> bits (T3GCON<1:0>). The polarity for each available source is also selectable and is controlled by the T3GPOL bit (T3GCON<6>). TMR4 match with PR4. When T3GPOL = 0, Timer3 increments continuously, except for the cycle following the match, when the gate signal goes from low-to-high. 16.5.2.3 Comparator 1 Output Gate Operation TABLE 16-2: T3GSS<1:0> 00 01 10 11 TIMER3 GATE SOURCES Timer3 Gate Source The output of Comparator 1 can be internally supplied to the Timer3 gate circuitry. After setting up Comparator 1 with the CM1CON register, Timer3 will increment depending on the transitions of the CMP1OUT (CMSTAT<6>) bit. Timerx Gate Pin TMR4 to Match PR4 (TMR4 increments to match PR4) Comparator 1 Output (comparator logic high output) Comparator 2 Output (comparator logic high output) 16.5.2.4 Comparator 2 Output Gate Operation The output of Comparator 2 can be internally supplied to the Timer3 gate circuitry. After setting up Comparator 2 with the CM2CON register, Timer3 will increment depending on the transitions of the CMP2OUT (CMSTAT<7>) bit. 16.5.2.1 T3G Pin Gate Operation 16.5.3 TIMER3 GATE TOGGLE MODE The T3G pin is one source for Timer3 gate control. It can be used to supply an external source to the Timerx gate circuitry. 16.5.2.2 Timer4 Match Gate Operation When Timer3 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer3 gate signal, as opposed to the duration of a single level pulse. The Timer3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure 16-3.) The T3GVAL bit will indicate when the Toggled mode is active and the timer is counting. Timer3 Gate Toggle mode is enabled by setting the T3GTM bit (T3GCON<5>). When the T3GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. The TMR4 register will increment until it matches the value in the PR4 register. On the very next increment cycle, TMR4 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timerx gate circuitry. The pulse will remain high for one instruction cycle and will return back to a low state until the next match. Depending on T3GPOL, Timerx increments differently when TMR4 matches PR4. When T3GPOL = 1, Timer3 increments for a single instruction cycle following a FIGURE 16-3: TMR3GE T3GPOL T3GTM T3G_IN TIMER3 GATE TOGGLE MODE T3CKI T3GVAL Timer3 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2011 Microchip Technology Inc. Preliminary DS39977C-page 235 PIC18F66K80 FAMILY 16.5.4 TIMER3 GATE SINGLE PULSE MODE When Timer3 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3 Gate Single Pulse mode is first enabled by setting the T3GSPM bit (T3GCON<4>). Next, the T3GGO/ T3DONE bit (T3GCON<3>) must be set. The Timer3 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T3GGO/T3DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer3 until the T3GGO/T3DONE bit is once again set in software. Clearing the T3GSPM bit will also clear the T3GGO/ T3DONE bit. (For timing details, see Figure 16-4.) Simultaneously enabling the Toggle mode and the Single Pulse mode will permit both sections to work together. This allows the cycle times on the Timer3 gate source to be measured. (For timing details, see Figure 16-5.) FIGURE 16-4: TMR3GE TIMER3 GATE SINGLE PULSE MODE T3GPOL T3GSPM Set by Software Counting Enabled on Rising Edge of T3G T3G_IN Cleared by Hardware on Falling Edge of T3GVAL T3GGO/ T3DONE T3CKI T3GVAL Timer3 N N+1 N+2 TMR3GIF Cleared by Software Set by Hardware on Falling Edge of T3GVAL Cleared by Software DS39977C-page 236 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 16-5: TMR3GE TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE T3GPOL T3GSPM T3GTM Cleared by Hardware on Falling Edge of T3GVAL T3GGO/ T3DONE Set by Software Counting Enabled on Rising Edge of T3G T3G_IN T3CKI T3GVAL Timer3 N N+1 N+2 N+3 N+4 Cleared by Software TMR3GIF Cleared by Software Set by Hardware on Falling Edge of T3GVAL 16.5.5 TIMER3 GATE VALUE STATUS 16.5.6 TIMER3 GATE EVENT INTERRUPT When Timer3 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T3GVAL bit (T3GCON<2>). The T3GVAL bit is valid even when the Timer3 gate is not enabled (TMR3GE bit is cleared). When the Timer3 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T3GVAL occurs, the TMR3GIF flag bit in the PIR2 register will be set. If the TMR3GIE bit in the PIE2 register is set, then an interrupt will be recognized. The TMR3GIF flag bit operates even when the Timer3 gate is not enabled (TMR3GE bit is cleared). 2011 Microchip Technology Inc. Preliminary DS39977C-page 237 PIC18F66K80 FAMILY 16.6 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMR3IF. Table 16-3 gives each module's flag bit. This interrupt can be enabled or disabled by setting or clearing the TMR3IE bit. Table 16-3 displays each module's enable bit. The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPR3H:CCPR3L register pair effectively becomes a Period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from an ECCP module, the write will take precedence. Note: 16.7 Resetting Timer3 Using the ECCP Special Event Trigger Note: The Special Event Triggers from the ECCPx module will only clear the TMR3 register's content, but not set the TMR3IF interrupt flag bit (PIR2<1>). If the ECCP modules are configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCP3M<3:0> = 1011), this signal will reset Timer3. The trigger from ECCP will also start an A/D conversion if the A/D module is enabled (For more information, see Section 20.3.4 "Special Event Trigger".) The CCP and ECCP modules use Timers, 1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRS register. For more details, see Register 20-2 and Register 19-2. TABLE 16-3: Name REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR5 PIE5 PIR2 PIE2 TMR3H TMR3L T3GCON T3CON OSCCON2 PMD1 GIE/GIEH IRXIF IRXIE OSCFIF OSCFIE PEIE/GIEL WAKIF WAKIE -- -- TMR0IE ERRIF ERRIE -- -- INT0IE TXB2IF TX2BIE -- -- RBIE TXB1IF TXB1IE BCLIF BCLIE TMR0IF TXB0IF TXB0IE HLVDIF HLVDIE INT0IF RXB1IF RXB1IE TMR3IF TMR3IE RBIF RXB0IF RXB0IE TMR3GIF TMR3GIE Timer3 Register High Byte Timer3 Register Low Byte TMR3GE TMR3CS1 -- PSPMD T3GPOL TMR3CS0 SOSCRUN CTMUMD T3GTM T3CKPS1 -- ADCMD T3GSPM T3CKPS0 SOSCDRV TMR4MD T3GGO/ T3DONE SOSCEN SOSCGO TMR3MD T3GVAL T3SYNC -- TMR2MD T3GSS1 RD16 MFIOFS TMR1MD T3GSS0 TMR3ON MFIOSEL TMR0MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module. DS39977C-page 238 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 17.0 * * * * * * TIMER4 MODULES The Timer4 timer modules have the following features: Eight-bit Timer register (TMR4) Eight-bit Period register (PR4) Readable and writable (all registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 TMR4 goes through a four-bit postscaler (that gives a 1:1 to 1:16 inclusive scaling) to generate a TMR4 interrupt, latched in the flag bit, TMR4IF. Table 17-1 gives each module's flag bit. The interrupt can be enabled or disabled by setting or clearing the Timer4 Interrupt Enable bit (TMR4IE), shown in Table 17-1. The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR4 register * A write to the T4CON register * Any device Reset - Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR) A TMR4 is not cleared when a T4CON is written. Note: The Timer4 modules have a control register shown in Register 17-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 also are controlled by this register. Figure 17-1 is a simplified block diagram of the Timer4 modules. 17.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the ECCP modules. The TMR4 registers are readable and writable, and are cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T4CKPS<1:0> (T4CON<1:0>). The match output of The CCP and ECCP modules use Timers, 1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRS register. For more details, see Register 20-2 and Register 19-2. REGISTER 17-1: U-0 -- bit 7 Legend: T4CON: TIMER4 CONTROL REGISTER R/W-0 T4OUTPS2 R/W-0 T4OUTPS1 R/W-0 T4OUTPS0 R/W-0 TMR4ON R/W-0 T4CKPS1 R/W-0 T4CKPS0 bit 0 R/W-0 T4OUTPS3 R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 2 bit 1-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 239 PIC18F66K80 FAMILY 17.2 Timer4 Interrupt 17.3 Output of TMR4 The Timer4 module has an eight-bit Period register, PR4, that is both readable and writable. Timer4 increment from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. The outputs of TMR4 (before the postscaler) are used only as a PWM time base for the ECCP modules. They are not used as baud rate clocks for the MSSP module as is the Timer2 output. FIGURE 17-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T4OUTPS<3:0> T4CKPS<1:0> 2 Set TMR4IF TMR4 Output (to PWM) Reset FOSC/4 1:1, 1:4, 1:16 Prescaler TMR4 8 Internal Data Bus TMRx/PRx Match Comparator PR4 8 8 TABLE 17-1: Name REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON IPR4 PIR4 PIE4 TMR4 T4CON PR4 PMD1 GIE/GIEH TMR4IP TMR4IF TMR4IE PEIE/GIEL EEIP EEIF EEIE TMR0IE CMP2IP CMP2IF CMP2IE INT0IE CMP1IP CMP1IF CMP1IE RBIE -- -- -- TMR0IF CCP5IP CCP5IF CCP5IE TMR4ON TMR2MD INT0IF CCP4IP CCP4IF CCP4IE T4CKPS1 TMR1MD RBIF CCP3IP CCP3IF CCP3IE T4CKPS0 TMR0MD Timer4 Register -- PSPMD T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 CTMUMD ADCMD TMR4MD TMR3MD Timer4 Period Register Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer4 module. DS39977C-page 240 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 18.0 CHARGE TIME MEASUREMENT UNIT (CTMU) * * * * * Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond High-precision time measurement Time delay of external or internal signal asynchronous to system clock * Accurate current source suitable for capacitive measurement The CTMU works in conjunction with the A/D Converter to provide up to 11 channels for time or charge measurement, depending on the specific device and the number of A/D channels available. When configured for time delay, the CTMU is connected to one of the analog comparators. The level-sensitive input edge sources can be selected from four sources: two external inputs or the ECCP1/CCP2 Special Event Triggers. The CTMU special event can trigger the Analog-to-Digital Converter module. Figure 18-1 provides a block diagram of the CTMU. The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. By working with other on-chip analog modules, the CTMU can precisely measure time, capacitance and relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. The module includes these key features: * Up to 11 channels available for capacitive or time measurement input * Low-cost temperature measurement using on-chip diode channel * On-chip precision current source * Four-edge input trigger sources * Polarity control for each edge source FIGURE 18-1: CTMU BLOCK DIAGRAM CTMUCONH:CTMUCONL EDGEN EDGSEQEN EDG1SEL<1:0> EDG1POL EDG2SEL<1:0> EDG2POL CTMUICON ITRIM<5:0> IRNG<1:0> EDG1STAT EDG2STAT TGEN IDISSEN CTTRIG Current Source CTED1 CTED2 Edge Control Logic Current Control CTMU Control Logic A/D Trigger CCP2 ECCP1 A/D Converter Comparator 2 Input Pulse Generator CTPLS Comparator 2 Output 2011 Microchip Technology Inc. Preliminary DS39977C-page 241 PIC18F66K80 FAMILY 18.1 CTMU Registers The control registers for the CTMU are: * CTMUCONH * CTMUCONL * CTMUICON The CTMUCONH and CTMUCONL registers (Register 18-1 and Register 18-2) contain control bits for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing, A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register 18-3) has bits for selecting the current source range and current source trim. REGISTER 18-1: R/W-0 CTMUEN bit 7 Legend: CTMUCONH: CTMU CONTROL HIGH REGISTER U-0 -- R/W-0 CTMUSIDL R/W-0 TGEN R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as `0' CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked ESGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: CTMU Special Event Trigger bit 1 = CTMU Special Event Trigger is enabled 0 = CTMU Special Event Trigger is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 242 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 18-2: R/W-0 EDG2POL bit 7 Legend: CTMUCONL: CTMU CONTROL LOW REGISTER R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT R/W-0 EDG1STAT bit 0 R/W-0 EDG2SEL1 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = CCP2 Special Event Trigger EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = CCP2 Special Event Trigger EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred bit 6-5 bit 4 bit 3-2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 243 PIC18F66K80 FAMILY REGISTER 18-3: R/W-0 ITRIM5 bit 7 Legend: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 0 R/W-0 ITRIM4 R = Readable bit -n = Value at POR bit 7-2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change (+62% typ.) from nominal current 011110 . . . 000001 = Minimum positive change (+2% typ.) from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change (-2% typ.) from nominal current . . . 100010 100001 = Maximum negative change (-62% typ.) from nominal current IRNG<1:0>: Current Source Range Select bits 11 = 100 x Base Current 10 = 10 x Base Current 01 = Base Current Level (0.55 A nominal) 00 = Current Source Disabled bit 1-0 DS39977C-page 244 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 18.2 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D becomes a measurement of the circuit's capacitance. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed. In this case, the voltage read by the A/D is representative of the amount of time elapsed from the time the current source starts and stops charging the circuit. If the CTMU is being used as a time delay, both capacitance and current source are fixed, as well as the voltage supplied to the comparator circuit. The delay of a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. Current trim is provided by the ITRIM<5:0> bits (CTMUICON<7:2>). These six bits allow trimming of the current source in steps of approximately 2% per step. Half of the range adjusts the current source positively and the other half reduces the current source. A value of `000000' is the neutral position (no change). A value of `100001' is the maximum negative adjustment (approximately -62%) and `011111' is the maximum positive adjustment (approximately +62%). 18.2.3 EDGE SELECTION AND CONTROL 18.2.1 THEORY OF OPERATION CTMU measurements are controlled by edge events occurring on the module's two input channels. Each channel, referred to as Edge 1 and Edge 2, can be configured to receive input pulses from one of the edge input pins (CTED1 and CTED2) or CCPx Special Event Triggers (ECCP1 and CCP2). The input channels are level-sensitive, responding to the instantaneous level on the channel rather than a transition between levels. The inputs are selected using the EDG1SEL and EDG2SEL bit pairs (CTMUCONL<3:2>, 6:5>). In addition to source, each channel can be configured for event polarity using the EDGE2POL and EDGE1POL bits (CTMUCONL<7,4>). The input channels can also be filtered for an edge event sequence (Edge 1 occurring before Edge 2) by setting the EDGSEQEN bit (CTMUCONH<2>). The operation of the CTMU is based on the equation for charge: I=C* dV dT More simply, the amount of charge measured in coulombs in a circuit is defined as current in amperes (I) multiplied by the amount of time in seconds that the current flows (t). Charge is also defined as the capacitance in farads (C) multiplied by the voltage of the circuit (V). It follows that: I*t=C*V 18.2.4 EDGE STATUS The CTMU module provides a constant, known current source. The A/D Converter is used to measure (V) in the equation, leaving two unknowns: capacitance (C) and time (t). The above equation can be used to calculate capacitance or time, by either the relationship using the known fixed capacitance of the circuit: t = (C * V)/I The CTMUCONL register also contains two status bits, EDG2STAT and EDG1STAT (CTMUCONL<1:0>). Their primary function is to show if an edge response has occurred on the corresponding channel. The CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive nature of the input channels also means that the status bits become set immediately if the channel's configuration is changed and matches the channel's current state. The module uses the edge status bits to control the current source output to external analog modules (such as the A/D Converter). Current is only supplied to external modules when only one (not both) of the status bits is set. Current is shut off when both bits are either set or cleared. This allows the CTMU to measure current only during the interval between edges. After both status bits are set, it is necessary to clear them before another measurement is taken. Both bits should be cleared simultaneously, if possible, to avoid re-enabling the CTMU current source. In addition to being set by the CTMU hardware, the edge status bits can also be set by software. This permits a user application to manually enable or disable the current source. Setting either (but not both) of the bits enables the current source. Setting or clearing both bits at once disables the source. or by: C = (I * t)/V using a fixed time that the current source is applied to the circuit. 18.2.2 CURRENT SOURCE At the heart of the CTMU is a precision current source, designed to provide a constant reference for measurements. The level of current is user-selectable across three ranges, or a total of two orders of magnitude, with the ability to trim the output in 2% increments (nominal). The current range is selected by the IRNG<1:0> bits (CTMUICON<1:0>), with a value of `01' representing the lowest range. 2011 Microchip Technology Inc. Preliminary DS39977C-page 245 PIC18F66K80 FAMILY 18.2.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3<3>) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3<3>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. Depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the CTMU module: * Edge Source Generation: In addition to the external edge input pins, ECCP1/CCP2 Special Event Triggers can be used as edge sources for the CTMU. * Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the voltage across a capacitor that is connected to one of the analog input channels. * Pulse Generation: When generating system clock independent, output pulses, the CTMU module uses Comparator 2 and the associated comparator voltage reference. 18.3 CTMU Module Initialization The following sequence is a general guideline used to initialize the CTMU module: 1. 2. 3. Select the current source range using the IRNGx bits (CTMUICON<1:0>). Adjust the current source trim using the ITRIMx bits (CTMUICON<7:2>). Configure the edge input sources for Edge 1 and Edge 2 by setting the EDG1SEL and EDG2SEL bits (CTMUCONL<3:2> and <6:5>, respectively). Configure the input polarities for the edge inputs using the EDG1POL and EDG2POL bits (CTMUCONL<4,7>). The default configuration is for negative edge polarity (high-to-low transitions). 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH<2>). By default, edge sequencing is disabled. 6. Select the operating mode (Measurement or Time Delay) with the TGEN bit (CTMUCONH<4>). The default mode Measurement. 7. is Time/Capacitance 18.4 Calibrating the CTMU Module 4. The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary. An example of a less precise application is a capacitive touch switch, in which the touch circuit has a baseline capacitance and the added capacitance of the human body changes the overall capacitance of a circuit. If actual capacitance or time measurement is required, two hardware calibrations must take place: * The current source needs calibration to set it to a precise current. * The circuit being measured needs calibration to measure or nullify any capacitance other than that to be measured. Configure the module to automatically trigger an A/D conversion when the second edge event has occurred using the CTTRIG bit (CTMUCONH<0>). The conversion trigger is disabled by default. 18.4.1 CURRENT SOURCE CALIBRATION 8. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH<1>). 9. After waiting a sufficient time for the circuit to discharge, clear the IDISSEN bit. 10. Disable the module by clearing the CTMUEN bit (CTMUCONH<7>). 11. Clear the Edge Status bits, EDG2STAT and EDG1STAT (CTMUCONL<1:0>). Both bits should be cleared simultaneously, if possible, to avoid re-enabling the CTMU current source. 12. Enable both edge inputs by setting the EDGEN bit (CTMUCONH<3>). 13. Enable the module by setting the CTMUEN bit. The current source on board the CTMU module has a range of 62% nominal for each of three current ranges. For precise measurements, it is possible to measure and adjust this current source by placing a high-precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure 18-2. To measure the current source: 1. 2. 3. 4. Initialize the A/D Converter. Initialize the CTMU. Enable the current source by setting EDG1STAT (CTMUCONL<0>). Issue time delay for voltage across RCAL to stabilize and ADC sample/hold capacitor to charge. Perform the A/D conversion. Calculate the current source current using I = V / RCAL, where RCAL is a high-precision resistance and V is measured by performing an A/D conversion. 5. 6. DS39977C-page 246 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY The CTMU current source may be trimmed with the trim bits in CTMUICON, using an iterative process to get the exact current desired. Alternatively, the nominal value without adjustment may be used. That value may be stored by software, for use in all subsequent capacitive or time measurements. To calculate the optimal value for RCAL, the nominal current must be chosen. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale (or 2.31V) as the desired approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is calculated as RCAL = 2.31V/0.55 A, for a value of 4.2 M. Similarly, if the current source is chosen to be 5.5 A, RCAL would be 420,000, and 42,000 if the current source is set to 55 A. A value of 70% of full-scale voltage is chosen to make sure that the A/D Converter is in a range that is well above the noise floor. If an exact current is chosen to incorporate the trimming bits from CTMUICON, the resistor value of RCAL may need to be adjusted accordingly. RCAL also may be adjusted to allow for available resistor values. RCAL should be of the highest precision available, in light of the precision needed for the circuit that the CTMU will be measuring. A recommended minimum would be 0.1% tolerance. The following examples show a typical method for performing a CTMU current calibration. * Example 18-1 demonstrates how to initialize the A/D Converter and the CTMU. This routine is typical for applications using both modules. * Example 18-2 demonstrates one method for the actual calibration routine. This method manually triggers the A/D Converter to demonstrate the entire step-wise process. It is also possible to automatically trigger the conversion by setting the CTMU's CTTRIG bit (CTMUCONH<0>). FIGURE 18-2: CTMU CURRENT SOURCE CALIBRATION CIRCUIT PIC18F66K80 Current Source CTMU A/D Trigger A/D Converter ANx RCAL A/D MUX 2011 Microchip Technology Inc. Preliminary DS39977C-page 247 PIC18F66K80 FAMILY EXAMPLE 18-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Setup CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCON - CTMU Control register CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, // Set Edge status bits to zero //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Setup AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configured AN2 as an analog channel // ANCON1 ANCON1 = 0x04; // ADCON1 ADCON2bits.ADFM=1; ADCON2bits.ACQT=1; ADCON2bits.ADCS=2; // ADCON1 ADCON1bits.VCFG0 =0; ADCON1bits.VCFG1 =0; ADCON1bits.VNCFG = 0; ADCON1bits.CHS=2; ADCON0bits.ADON=1; } // Result format 1= Right justified // Acquisition time 7 = 20TAD 2 = 4TAD 1=2TAD // Clock conversion bits 6= FOSC/64 2=FOSC/32 // // // // Vref+ = AVdd Vref+ = AVdd Vref- = AVss Select ADC channel // Turn on ADC DS39977C-page 248 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 18-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i //float values stored for calcs //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; DELAY; CTMUCONHbits.IDISSEN = 0; CTMUCONLbits.EDG1STAT = 1; DELAY; CTMUCONLbits.EDG1STAT = 0; PIR1bits.ADIF = 0; ADCON0bits.GO=1; while(!PIR1bits.ADIF); Vread = ADRES; PIR1bits.ADIF = 0; VTot += Vread; } Vavg = (float)(VTot/10.000); Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; } //Average of 10 readings //CTMUISrc is in 1/100ths of uA //Enable the CTMU //drain charge on the circuit //wait 125us //end drain of circuit //Begin charging the circuit //using CTMU current source //wait for 125us //Stop charging circuit //make sure A/D Int not set //and begin A/D conv. //Wait for A/D convert complete //Get the value from the A/D //Clear A/D Interrupt Flag //Add the reading to the total 2011 Microchip Technology Inc. Preliminary DS39977C-page 249 PIC18F66K80 FAMILY 18.4.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. After removing the capacitance to be measured: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU. Set EDG1STAT (= 1). Wait for a fixed delay of time, t. Clear EDG1STAT. Perform an A/D conversion. Calculate the stray and A/D sample capacitances: COFFSET = CSTRAY + CAD = (I * t)/V This measured value is then stored and used for calculations of time measurement or subtracted for capacitance measurement. For calibration, it is expected that the capacitance of CSTRAY + CAD is approximately known; CAD is approximately 4 pF. An iterative process may be required to adjust the time, t, that the circuit is charged to obtain a reasonable voltage reading from the A/D Converter. The value of t may be determined by setting COFFSET to a theoretical value and solving for t. For example, if CSTRAY is theoretically calculated to be 11 pF, and V is expected to be 70% of VDD or 2.31V, t would be: (4 pF + 11 pF) * 2.31V/0.55 A or 63 s. See Example 18-3 for a typical routine for CTMU capacitance calibration. Where: * I is known from the current source measurement step * t is a fixed delay * V is measured by performing an A/D conversion DS39977C-page 250 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 18-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i //drain charge on the circuit //wait 125us //end drain of circuit //Begin charging the circuit //using CTMU current source //wait for 125us //Stop charging circuit //make sure A/D Int not set //and begin A/D conv. //Wait for A/D convert complete Vread = ADRES; PIR1bits.ADIF = 0; VTot += Vread; } //Get the value from the A/D //Clear A/D Interrupt Flag //Add the reading to the total Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA CTMUCap = (CTMUISrc*ETIME/Vcal)/100; } 2011 Microchip Technology Inc. Preliminary DS39977C-page 251 PIC18F66K80 FAMILY 18.5 Measuring Capacitance with the CTMU 18.5.2 CAPACITIVE TOUCH SENSE USING RELATIVE CHARGE MEASUREMENT There are two ways to measure capacitance with the CTMU. The absolute method measures the actual capacitance value. The relative method only measures for any change in the capacitance. Not all applications require precise capacitance measurements. When detecting a valid press of a capacitance-based switch, only a relative change of capacitance needs to be detected. In such an application, when the switch is open (or not touched), the total capacitance is the capacitance of the combination of the board traces, the A/D Converter and other elements. A larger voltage will be measured by the A/D Converter. When the switch is closed (or touched), the total capacitance is larger due to the addition of the capacitance of the human body to the above listed capacitances and a smaller voltage will be measured by the A/D Converter. To detect capacitance changes simply: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Wait for a fixed delay. Clear EDG1STAT. Perform an A/D conversion. 18.5.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 18.4 "Calibrating the CTMU Module" should be followed. To perform these measurements: 1. 2. 3. 4. 5. 6. 7. Initialize the A/D Converter. Initialize the CTMU. Set EDG1STAT. Wait for a fixed delay, T. Clear EDG1STAT. Perform an A/D conversion. Calculate the total capacitance, CTOTAL = (I * T)/V, where: * I is known from the current source measurement step (Section 18.4.1 "Current Source Calibration") * T is a fixed delay * V is measured by performing an A/D conversion Subtract the stray and A/D capacitance (COFFSET from Section 18.4.2 "Capacitance Calibration") from CTOTAL to determine the measured capacitance. The voltage measured by performing the A/D conversion is an indication of the relative capacitance. In this case, no calibration of the current source or circuit capacitance measurement is needed. (For a sample software routine for a capacitive touch switch, see Example 18-4.) 8. DS39977C-page 252 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 18-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i //storage for reading //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; CTMUCONHbits.IDISSEN = 1; DELAY; CTMUCONHbits.IDISSEN = 0; CTMUCONLbits.EDG1STAT = 1; DELAY; CTMUCONLbits.EDG1STAT = 0; PIR1bits.ADIF = 0; ADCON0bits.GO=1; while(!PIR1bits.ADIF); Vread = ADRES; if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } } //Enable the CTMU //drain charge on the circuit //wait 125us //end drain of circuit //Begin charging the circuit //using CTMU current source //wait for 125us //Stop charging circuit //make sure A/D Int not set //and begin A/D conv. //Wait for A/D convert complete //Get the value from the A/D 2011 Microchip Technology Inc. Preliminary DS39977C-page 253 PIC18F66K80 FAMILY 18.6 Measuring Time with the CTMU Module It is assumed that the time measured is small enough that the capacitance, CAD + CEXT, provides a valid voltage to the A/D Converter. For the smallest time measurement, always set the A/D Channel Select bits CHS<4:0> (ADCON0<6:2>) to an unused A/D channel, the corresponding pin for which is not connected to any circuit board trace. This minimizes added stray capacitance, keeping the total circuit capacitance close to that of the A/D Converter itself (25 pF). To measure longer time intervals, an external capacitor may be connected to an A/D channel and that channel selected whenever making a time measurement. Time can be precisely measured after the ratio (C/I) is measured from the current and capacitance calibration step. To do that: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Set EDG2STAT. Perform an A/D conversion. Calculate the time between edges as T = (C/I) * V, where: * I is calculated in the current calibration step (Section 18.4.1 "Current Source Calibration") * C is calculated in the capacitance calibration step (Section 18.4.2 "Capacitance Calibration") * V is measured by performing the A/D conversion FIGURE 18-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18F66K80 CTMU CTED1 CTED2 EDG1 EDG2 A/D Voltage A/D Converter CAD CEXT Current Source ANX DS39977C-page 254 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 18.7 Measuring Temperature with the CTMU To perform a measurement, the multiplexer is configured to select the pin connected to the diode. The CTMU current source is then turned on and an A/D conversion is performed on the channel. As shown in the equivalent circuit diagram, the diode is driven by the CTMU at IF. The resulting VF across the diode is measured by the ADC. A code snippet is shown in Example 18-5. The constant current source provided by the CTMU module can be used for low-cost temperature measurement by exploiting a basic property of common and inexpensive diodes. An on-chip temperature sense diode is provided on ADC Channel 29 to further simplify design and cost. 18.7.1 BASIC PRINCIPAL FIGURE 18-4: CTMU TEMPERATURE MEASUREMENT CIRCUIT PIC(R) Microcontroller Current Source We can show that the forward voltage (VF) of a P-N junction, such as a diode, is an extension of the equation for the junction's thermal voltage: VF = kT I 1n 1 - F IS q Simplified Block Diagram ( ) CTMU where k is the Boltzmann constant (1.38 x 10-23 J K-1), T is the absolute junction temperature in kelvin, q is the electron charge (1.6 x 10-19 C), IF is the forward current applied to the diode and IS is the diode's characteristic saturation current, which varies between devices. Since k and q are physical constants, and IS is a constant for the device, this only leaves T and IF as independent variables. If IF is held constant, it follows from the equation that VF will vary as a function of T. As the natural log term of the equation will always be negative, the temperature will be negatively proportional to VF. In other words, as temperature increases, VF decreases. By using the CTMU's current source to provide a constant IF, it becomes possible to calculate the temperature by measuring the VF across the diode. Equivalent Circuit A/D Converter MUX A/D VF CTMU 18.7.2 IMPLEMENTATION IF VF ADC To implement this theory, all that is needed is to connect a regular junction diode to one of the microcontroller's A/D pins (Figure 18-2). The A/D channel multiplexer is shared by the CTMU and the ADC. EXAMPLE 18-5: ROUTINE FOR TEMPERATURE MEASUREMENT USING INTERNAL DIODE // Initialize CTMU CTMUICON = 0x03; CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 1; // Initialize ADC ADCON0 = 0xE5; ADCON1 = 0x00; ADCON2 = 0xBE; ADCON0bits.GO = 1; while(ADCON0bits.G0); Temp = ADRES; Note: // Enable ADC and connect to Internal diode //Right Justified // Start conversion // Read ADC results (inversely proportional to temperature) The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application. 2011 Microchip Technology Inc. Preliminary DS39977C-page 255 PIC18F66K80 FAMILY 18.8 Creating a Delay with the CTMU Module An example use of the external capacitor feature is interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse-width output on CTPLS will vary. An example use of the CTDIN feature is interfacing with a digital sensor. The CTPLS output pin can be connected to an input capture pin and the varying pulse width measured to determine the sensor's output in the application. To use this feature: 1. 2. 3. 4. If CTMUDS is cleared, initialize Comparator 2. If CTMUDS is cleared, initialize the comparator voltage reference. Initialize the CTMU and enable time delay generation by setting the TGEN bit. Set EDG1STAT. A unique feature on board the CTMU module is its ability to generate system clock independent output pulses based on either an external voltage or an external capacitor value. When using an external voltage, this is accomplished using the CTDIN input pin as a trigger for the pulse delay. When using an external capacitor value, this is accomplished using the internal comparator voltage reference module and Comparator 2 input pin.The pulse is output onto the CTPLS pin. To enable this mode, set the TGEN bit. See Figure 18-5 for an example circuit. When CTMUDS (PADCFG1<0>) is cleared, the pulse delay is determined by the output of Comparator 2, and when it is set, the pulse delay is determined by the input of CTDIN. CDELAY is chosen by the user to determine the output pulse width on CTPLS. The pulse width is calculated by T = (CDELAY/I)*V, where I is known from the current source measurement step (Section 18.4.1 "Current Source Calibration") and V is the internal reference voltage (CVREF). When CTMUDS is cleared, as soon as CDELAY charges to the value of the voltage reference trip point, an output pulse is generated on CTPLS. When CTMUDS is set, as soon as CTDIN is set, an output pulse is generated on CTPLS. FIGURE 18-5: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18F66K80 CTED1 EDG1 CTMU CTPLS Current Source Comparator CTMUI C2 CTMUDS CTDIN CDELAY CVREF C1 External Reference External Comparator DS39977C-page 256 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 18.9 Measuring Temperature with the CTMU Module source the current to the diode. The ADC reading will reflect the temperature. With the increase, the ADC readings will go low. This can be used for low-cost temperature measurement applications. The CTMU, along with an internal diode, can be used to measure the temperature. The ADC can be connected to the internal diode and the CTMU module can EXAMPLE 18-6: ROUTINE FOR TEMPERATURE MEASUREMENT USING INTERNAL DIODE // Initialize CTMU CTMUICON = 0x03; CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 1; // Initialize ADC ADCON0 = 0xE5; ADCON1 = 0x00; ADCON2 = 0xBE; ADCON0bits.GO = 1; while(ADCON0bits.G0); Temp = ADRES; // Enable ADC and connect to Internal diode //Right Justified // Start conversion // Read ADC results (inversely proportional to temperature) Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application. 2011 Microchip Technology Inc. Preliminary DS39977C-page 257 PIC18F66K80 FAMILY 18.10 Operation During Sleep/Idle Modes 18.10.1 SLEEP MODE When the device enters any Sleep mode, the CTMU module current source is always disabled. If the CTMU is performing an operation that depends on the current source when Sleep mode is invoked, the operation may not terminate correctly. Capacitance and time measurements may return erroneous values. case, if the module is performing an operation when Idle mode is invoked, the results will be similar to those with Sleep mode. 18.11 Effects of a Reset on CTMU Upon Reset, all registers of the CTMU are cleared. This disables the CTMU module, turns off its current source and returns all configuration options to their default settings. The module needs to be re-initialized following any Reset. If the CTMU is in the process of taking a measurement at the time of Reset, the measurement will be lost. A partial charge may exist on the circuit that was being measured, which should be properly discharged before the CTMU makes subsequent attempts to make a measurement. The circuit is discharged by setting and clearing the IDISSEN bit (CTMUCONH<1>) while the A/D Converter is connected to the appropriate channel. 18.10.2 IDLE MODE The behavior of the CTMU in Idle mode is determined by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL is cleared, the module will continue to operate in Idle mode. If CTMUSIDL is set, the module's current source is disabled when the device enters Idle mode. In this TABLE 18-1: Name REGISTERS ASSOCIATED WITH CTMU MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CTMUCONH CTMUEN CTMUICON PIR3 PIE3 IPR3 PADCFG1 Legend: -- ITRIM4 -- -- -- REPU CTMUSIDL ITRIM3 RC2IF RC2IE RC2IP RFPU TGEN ITRIM2 TX2IF TX2IE TX2IP RGPU EDGEN ITRIM1 CTMUIF CTMUIE CTMUIP -- EDGSEQEN ITRIM0 CCP2IF CCP2IE CCP2IP -- IDISSEN IRNG1 CCP1IF CCP1IE CCP1IP -- CTTRIG IRNG0 -- -- -- CTMUDS CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT ITRIM5 -- -- -- RDPU -- = unimplemented, read as `0'. Shaded cells are not used during ECCP operation. DS39977C-page 258 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 19.0 CAPTURE/COMPARE/PWM (CCP) MODULES Each CCP module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. For the sake of clarity, all CCP module operation in the following sections is described with respect to CCP2, but is equally applicable to CCP3 through CCP5. PIC18F66K80 family devices have four CCP (Capture/Compare/PWM) modules, designated CCP2 through CCP5. All the modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Throughout this section, generic references are used for register and bit names that are the same, except for an `x' variable that indicates the item's association with the specific CCP module. For example, the control register is named CCPxCON and refers to CCP2CON through CCP5CON. REGISTER 19-1: U-0 -- bit 7 Legend: CCPxCON: CCPx CONTROL REGISTER (CCP2-CCP5 MODULES)(1) U-0 -- R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3(1) R/W-0 CCPxM2(1) R/W-0 CCPxM1(1) R/W-0 CCPxM0(1) bit 0 R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL. CCPxM<3:0>: CCPx Module Mode Select bits(1) 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge or CAN message received (time-stamp)(2) 0101 = Capture mode: every rising edge or CAN message received (time-stamp)(2) 0110 = Capture mode: every 4th rising edge or on every fourth CAN message received (time-stamp)(2 0111 = Capture mode: every 16th rising edge or on every 16th CAN message received (time-stamp)(2) 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set) 11xx = PWM mode bit 3-0 Note 1: 2: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCPx match. Available only on CCP2. Selected by the CANCAP (CIOCON<4>) bit. Overrides the CCP2 input pin source. 2011 Microchip Technology Inc. Preliminary DS39977C-page 259 PIC18F66K80 FAMILY REGISTER 19-2: U-0 -- bit 7 Legend: CCPTMRS: CCP TIMER SELECT REGISTER U-0 -- U-0 -- R/W-0 C5TSEL R/W-0 C4TSEL R/W-0 C3TSEL R/W-0 C2TSEL R/W-0 C1TSEL bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' C5TSEL: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR3/TMR4 C4TSEL: CCP4 Timer Selection bit 0 = CCP4 is based off of TMR1/TMR2 1 = CCP4 is based off of TMR3/TMR4 C3TSEL: CCP3 Timer Selection bit 0 = CCP3 is based off of TMR1/TMR2 1 = CCP3 is based off of TMR3/TMR4 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 is based off of TMR1/TMR2 1 = CCP2 is based off of TMR3/TMR4 C1TSEL: CCP1 Timer Selection bit 0 = ECCP1 is based off of TMR1/TMR2 1 = ECCP1 is based off of TMR3/TMR4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 260 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 19-3: R/W-x CCPRxL7 bit 7 Legend: CCPRxL: CCPx PERIOD LOW BYTE REGISTER R/W-x R/W-x CCPRxL5 R/W-x CCPRxL4 R/W-x CCPRxL3 R/W-x CCPRxL2 R/W-x CCPRxL1 R/W-x CCPRxL0 bit 0 CCPRxL6 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CCPRxL<7:0>: CCPx Period Register Low Byte bits Capture Mode: Capture register low byte Compare Mode: Compare register low byte PWM Mode: Duty Cycle register REGISTER 19-4: R/W-x CCPRxH7 bit 7 Legend: CCPRxH: CCPx PERIOD HIGH BYTE REGISTER R/W-x R/W-x CCPRxH5 R/W-x CCPRxH4 R/W-x CCPRxH3 R/W-x CCPRxH2 R/W-x CCPRxH1 R/W-x CCPRxH0 bit 0 CCPRxH6 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CCPRxH<7:0>: CCPx Period Register High Byte bits Capture Mode: Capture register high byte Compare Mode: Compare register high byte PWM Mode: Duty Cycle Buffer register 2011 Microchip Technology Inc. Preliminary DS39977C-page 261 PIC18F66K80 FAMILY 19.1 CCP Module Configuration TABLE 19-1: CCP Mode Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. CCP MODE - TIMER RESOURCE Timer Resource Capture Compare PWM Timer1 or Timer3 Timer2 or Timer4 19.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers, 1 through 4, varying with the selected mode. Various timers are available to the CCP modules in Capture, Compare or PWM modes, as shown in Table 19-1. The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the CCPTMRS register (see Register 19-2). All of the modules may be active at once and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. The CCPTMRS register selects the timers for CCP modules, 2, 3, 4 and 5. The possible configurations are shown in Table 19-2. TABLE 19-2: TIMER ASSIGNMENTS FOR CCP MODULES 2, 3, 4 AND 5 CCPTMRS Register CCP2 Capture/ PWM C2TSEL Compare Mode Mode 0 1 TMR1 TMR3 TMR2 TMR4 CCP3 Capture/ PWM C3TSEL Compare Mode Mode 0 1 TMR1 TMR3 TMR2 TMR4 CCP4 Capture/ C4TSEL Compare Mode 0 1 TMR1 TMR3 CCP5 Capture/ PWM PWM C5TSEL Compare Mode Mode Mode TMR2 TMR4 00 01 TMR1 TMR3 TMR2 TMR4 19.1.2 OPEN-DRAIN OUTPUT OPTION When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the CCPxOD bits (ODCON<6:2>). Setting the appropriate bit configures the pin for the corresponding module for open-drain operation. DS39977C-page 262 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 19.2 Capture Mode 19.2.1 CCP PIN CONFIGURATION In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the Timer register selected in the CCPTMRS when an event occurs on the CCPx pin. An event is defined as one of the following: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Note: In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. 19.2.2 TIMER1/3 MODE SELECTION For the available timers (1/3) to be used for the capture feature, the used timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the CCPTMRS register. (See Section 19.1.1 "CCP Modules and Timer Resources".) Details of the timer assignments for the CCP modules are given in Table 19-2. For CCP2 only, the Capture mode can use the CCP2 input pin as the capture trigger for CCP2 or the input can function as a time-stamp through the CAN module. The CAN module provides the necessary control and trigger signals. The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF (PIR4 FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP3IF C3TSEL TMR3H TMR3 Enable CCPR3H TMR1 Enable TMR1H Set CCP4IF TMR1L CCPR3L TMR3L CCP3 Pin Prescaler 1, 4, 16 and Edge Detect C3TSEL CCP3CON<3:0> Q1:Q4 CCP4CON<3:0> 4 4 4 C4TSEL TMR3H TMR3 Enable TMR3L CCP4 Pin Prescaler 1, 4, 16 and Edge Detect CCPR4H TMR1 Enable C4TSEL TMR1H CCPR4L TMR1L Note: This block diagram uses CCP3 and CCP4, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table 19-2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 263 PIC18F66K80 FAMILY 19.2.3 SOFTWARE INTERRUPT 19.2.5 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE bit (PIE4 CAN MESSAGE TIME-STAMP (CCP2 ONLY) 19.2.4 CCP PRESCALER For CCP2, only the CAN capture event occurs when a message is received in any of the receive buffers. When configured, the CAN module provides the trigger to the CCP2 module to cause a capture event. This feature is provided to "time-stamp" the received CAN messages. This feature is enabled by setting the CANCAP bit of the CAN I/O Control register (CIOCON<4>). The message receive signal from the CAN module then takes the place of the events on RC2/CCP2. If this feature is selected, then four different capture options for CCP2M<3:0> are available: * 0100 - Every time a CAN message is received * 0101 - Every time a CAN message is received * 0110 - Every 4th time a CAN message is received * 0111 - Capture mode, every 16th time a CAN message is received There are four prescaler settings in Capture mode. They are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Doing that also will not clear the prescaler counter - meaning the first capture may be from a non-zero prescaler. Example 19-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 19-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF CCPxCON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON MOVWF CCPxCON ; Load CCPxCON with ; this value DS39977C-page 264 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 19.3 Compare Mode 19.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPRx register value is constantly compared against the Timer register pair value selected in the CCPTMR register. When a match occurs, the CCPx pin can be: * * * * Driven high Driven low Toggled (high-to-low or low-to-high) Unchanged (that is, reflecting the state of the I/O latch) When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCPxIE bit is set. 19.3.4 SPECIAL EVENT TRIGGER The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. Figure 19-2 gives the Compare mode block diagram All CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode bits (CCPxM<3:0> = 1011). For either CCPx module, the Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module's time base. This allows the CCPRx registers to serve as a programmable Period register for either timer. 19.3.1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. Note: Clearing the CCPxCON register will force the corresponding CCPx compare output latch (depending on device configuration) to the default low level. This is not the PORTx data latch. 19.3.2 TIMER1/3 MODE SELECTION If the CCPx module is using the compare feature in conjunction with any of the Timer1/3 timers, the timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the compare operation may not work. Note: Details of the timer assignments for the CCPx modules are given in Table 19-2. 2011 Microchip Technology Inc. Preliminary DS39977C-page 265 PIC18F66K80 FAMILY FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM Set CCP5IF Special Event Trigger (Timer1/3 Reset) CCP5 Pin Comparator Compare Match Output Logic 4 CCP5CON<3:0> TMR1H TMR1L 0 S R TRIS Output Enable Q CCPR5H CCPR5L TMR3H TMR3L 1 C5TSEL 0 TMR1H TMR1L 1 TMR3H C4TSEL TMR3L Special Event Trigger (Timer1/Timer3 Reset) Set CCP4IF Comparator Compare Match Output Logic 4 CCP4CON<3:0> S R Q CCP4 Pin CCPR4H CCPR4L TRIS Output Enable Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table 19-2. DS39977C-page 266 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 19-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON RCON PIR3 PIE3 IPR3 PIR4 PIE4 IPR4 TRISB TRISC TMR1L TMR1H TMR3L TMR3H T1CON T3CON CCPR2L CCPR2H CCPR3L CCPR3H CCPR4L CCPR4H CCPR5L CCPR5H CCP2CON CCP3CON CCP4CON CCP5CON CCPTMRS PMD0 GIE/GIEH PEIE/GIEL IPEN -- -- -- TMR4IF TMR4IE TMR4IP TRISB7 TRISC7 SBOREN -- -- -- EEIF EEIE EEIP TRISB6 TRISC6 TMR0IE CM RC2IF RC2IE RC2IP CMP2IF CMP2IE CMP2IP TRISB5 TRISC5 INT0IE RI TX2IF TX2IE TX2IP CMP1IF CMP1IE CMP1IP TRISB4 TRISC4 RBIE TO CTMUIF CTMUIE CTMUIP -- -- -- TRISB3 TRISC3 TMR0IF PD CCP2IF CCP2IE CCP2IP CCP5IF CCP5IE CCP5IP TRISB2 TRISC2 INT0IF POR CCP1IF CCP1IE CCP1IP CCP4IF CCP4IE CCP4IP TRISB1 TRISC1 RBIF BOR -- -- -- CCP3IF CCP3IE CCP3IP TRISB0 TRISC0 Timer1 Register Low Byte Timer1 Register High Byte Timer3 Register Low Byte Timer3 Register High Byte TMR1CS1 TMR1CS0 TMR3CS1 TMR3CS0 T1CKPS1 T3CKPS1 T1CKPS0 T3CKPS0 SOSCEN SOSCEN T1SYNC T3SYNC RD16 RD16 TMR1ON TMR3ON Capture/Compare/PWM Register 2 Low Byte Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 3 Low Byte Capture/Compare/PWM Register 3 High Byte Capture/Compare/PWM Register 4 Low Byte Capture/Compare/PWM Register 4 High Byte Capture/Compare/PWM Register 5 Low Byte Capture/Compare/PWM Register 5 High Byte -- -- -- -- -- CCP5MD -- -- -- -- -- CCP4MD DC2B1 DC3B1 DC4B1 DC5B1 -- CCP3MD DC2B0 DC3B0 DC4B0 DC5B0 C5TSEL CCP2MD CCP2M3 CCP3M3 CCP4M3 CCP5M3 C4TSEL CCP1MD CCP2M2 CCP3M2 CCP4M2 CCP5M2 C3TSEL CCP2M1 CCP3M1 CCP4M1 CCP5M1 C2TSEL CCP2M0 CCP3M0 CCP4M0 CCP5M0 C1TSEL SSPMD UART2MD UART1MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Capture/Compare or Timer1/3. 2011 Microchip Technology Inc. Preliminary DS39977C-page 267 PIC18F66K80 FAMILY 19.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCPx pin is multiplexed with a PORTC or PORTB data latch, the appropriate TRIS bit must be cleared to make the CCPx pin an output. Note: A PWM output (Figure 19-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 19-4: Period PWM OUTPUT Clearing the CCPxCON register will force the corresponding CCPx output latch (depending on device configuration) to the default low level. This is not the PORTx I/O data latch. Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 Figure 19-3 shows a simplified block diagram of the CCPx module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 19.4.3 "Setup for PWM Operation". 19.4.1 PWM PERIOD FIGURE 19-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP4CON<5:4> The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: Duty Cycle Registers CCPR4L EQUATION 19-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) CCPR4H (Slave) R Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Clear Timer, CCP1 Pin and Latch D.C. PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP4 pin is set (An exception: If PWM duty cycle = 0%, the CCP4 pin will not be set) * The PWM duty cycle is latched from CCPR4L into CCPR4H Note: Comparator Comparator PR2 Note 1: 2: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCP4 and its appropriate timers are used as an example. For details on all of the CCP modules and their timer assignments, see Table 19-2. The Timer2 postscalers (see Section 15.0 "Timer2 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. DS39977C-page 268 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 19.4.2 PWM DUTY CYCLE The PWM duty cycle is specified, to use CCP4 as an example, by writing to the CCPR4L register and to the CCP4CON<5:4> bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: The CCPR4H register and a two-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR4H and two-bit latch match TMR2, concatenated with an internal two-bit Q clock or two bits of the TMR2 prescaler, the CCP4 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 19-2: PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) * TOSC * (TMR2 Prescale Value) EQUATION 19-3: FOSC log --------------- FPWM PWM Resolution (max) = -----------------------------bits log 2 Note: CCPR4L and CCP4CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR4H until after a match between PR2 and TMR2 occurs (that is, the period is complete). In PWM mode, CCPR4H is a read-only register. If the PWM duty cycle value is longer than the PWM period, the CCP4 pin will not be cleared. TABLE 19-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 16 FFh 10 4 FFh 10 1 FFh 10 1 3Fh 8 1 1Fh 7 1 17h 6.58 19.4.3 SETUP FOR PWM OPERATION 3. 4. 5. To configure the CCP module for PWM operation, using CCP4 as an example: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR4L register and CCP4CON<5:4> bits. Make the CCP4 pin an output by clearing the appropriate TRIS bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCP4 module for PWM operation. 2011 Microchip Technology Inc. Preliminary DS39977C-page 269 PIC18F66K80 FAMILY TABLE 19-5: Name REGISTERS ASSOCIATED WITH PWM AND TIMERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON RCON PIR3 PIE3 IPR3 PIR4 PIE4 IPR4 TRISB TRISC TMR2 TMR4 PR2 PR4 T2CON T4CON CCPR2L CCPR2H CCPR3L CCPR3H CCPR4L CCPR4H CCPR5L CCPR5H CCP2CON CCP3CON CCP4CON CCP5CON CCPTMRS PMD0 GIE/GIEH PEIE/GIEL IPEN -- -- -- TMR4IF TMR4IE TMR4IP TRISB7 TRISC7 SBOREN -- -- -- EEIF EEIE EEIP TRISB6 TRISC6 TMR0IE CM RC2IF RC2IE RC2IP CMP2IF CMP2IE CMP2IP TRISB5 TRISC5 INT0IE RI TX2IF TX2IE TX2IP CMP1IF CMP1IE CMP1IP TRISB4 TRISC4 RBIE TO CTMUIF CTMUIE CTMUIP -- -- -- TRISB3 TRISC3 TMR0IF PD CCP2IF CCP2IE CCP2IP CCP5IF CCP5IE CCP5IP TRISB2 TRISC2 INT0IF POR CCP1IF CCP1IE CCP1IP CCP4IF CCP4IE CCP4IP TRISB1 TRISC1 RBIF BOR -- -- -- CCP3IF CCP3IE CCP3IP TRISB0 TRISC0 Timer2 Register Timer4 Register Timer2 Period Register Timer4 Period Register -- -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR2ON TMR4ON T2CKPS1 T4CKPS1 T2CKPS0 T4CKPS0 Capture/Compare/PWM Register 2 Low Byte Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 3 Low Byte Capture/Compare/PWM Register 3 High Byte Capture/Compare/PWM Register 4 Low Byte Capture/Compare/PWM Register 4 High Byte Capture/Compare/PWM Register 5 Low Byte Capture/Compare/PWM Register 5 High Byte -- -- -- -- -- CCP5MD -- -- -- -- -- CCP4MD DC2B1 DC3B1 DC4B1 DC5B1 -- CCP3MD DC2B0 DC3B0 DC4B0 DC5B0 C5TSEL CCP2MD CCP2M3 CCP3M3 CCP4M3 CCP5M3 C4TSEL CCP1MD CCP2M2 CCP3M2 CCP4M2 CCP5M2 C3TSEL CCP2M1 CCP3M1 CCP4M1 CCP5M1 C2TSEL CCP2M0 CCP3M0 CCP4M0 CCP5M0 C1TSEL SSPMD UART2MD UART1MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PWM or Timer2/4. DS39977C-page 270 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE * * * * * Provision for two or four output channels Output Steering modes Programmable polarity Programmable dead-band control Automatic shutdown and restart PIC18F66K80 family devices have one Enhanced Capture/Compare/PWM (ECCP) module: ECCP1. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. These ECCP modules are upward compatible with CCP ECCP1 is implemented as standard CCP modules with enhanced PWM capabilities. These include: The enhanced features are discussed in detail in Section 20.4 "PWM (Enhanced Mode)". The ECCP1 module uses the control register, CCP1CON. The control registers, CCP2CON through CCP5CON, are for the modules, CCP2 through CCP5. 2011 Microchip Technology Inc. Preliminary DS39977C-page 271 PIC18F66K80 FAMILY REGISTER 20-1: R/W-0 P1M1 bit 7 Legend: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM1 CONTROL R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0 P1M0 R/W-0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as capture/compare input/output; P1B, P1C and P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output: P1A, P1B, P1C and P1D controlled by steering (see Section 20.4.7 "Pulse Steering Mode") 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C and P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A and P1D inactive DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. CCP1M<3:0>: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP1 module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every fourth rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize ECCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode, initialize ECCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode, generate software interrupt only, ECCP1 pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP1 resets TMR1 or TMR3, starts A/D conversion, sets CCP1IF bit) 1100 = PWM mode; P1A and P1C active-high; P1B and P1D active-high 1101 = PWM mode; P1A and P1C active-high; P1B and P1D active-low 1110 = PWM mode; P1A and P1C active-low; P1B and P1D active-high 1111 = PWM mode; P1A and P1C active-low; P1B and P1D active-low bit 5-4 bit 3-0 DS39977C-page 272 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 20-2: U-0 -- bit 7 Legend: CCPTMRS: CCP TIMER SELECT REGISTER U-0 -- U-0 -- R/W-x C5TSEL R/W-x C4TSEL R/W-x C3TSEL R/W-x C2TSEL R/W-x C1TSEL bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' C5TSEL: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR3/TMR4 C4TSEL: CCP4 Timer Selection bit 0 = CCP4 is based off of TMR1/TMR2 1 = CCP4 is based off of TMR3/TMR4 C3TSEL: CCP3 Timer Selection bit 0 = CCP3 is based off of TMR1/TMR2 1 = CCP3 is based off of TMR3/TMR4 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 is based off of TMR1/TMR2 1 = CCP2 is based off of TMR3/TMR4 C1TSEL: CCP1 Timer Selection bit 0 = ECCP1 is based off of TMR1/TMR2 1 = ECCP1 is based off of TMR3/TMR4 bit 3 bit 2 bit 1 bit 0 In addition to the expanded range of modes available through the CCP1CON and ECCP1AS registers, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: * ECCP1DEL - Enhanced PWM Control * PSTR1CON - Pulse Steering Control 2011 Microchip Technology Inc. Preliminary DS39977C-page 273 PIC18F66K80 FAMILY 20.1 ECCP Outputs and Configuration 20.2 Capture Mode The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. The CCP1CON register is modified to allow control over four PWM outputs: ECCP1/P1A, P1B, P1C and P1D. Applications can use one, two or four of these outputs. The outputs that are active depend on the ECCP operating mode selected. The pin assignments are summarized in Table 20-2. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M<1:0> and CCP1M<3:0> bits. The appropriate TRIS direction bits for the port pins must also be set as outputs. In Capture mode, the CCPR1H:CCPR1L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding ECCP1 pin. An event is defined as one of the following: * * * * Every falling edge Every rising edge Every fourth rising edge Every 16th rising edge 20.1.1 ECCP MODULE AND TIMER RESOURCES The event is selected by the mode select bits, CCP1M<3:0> (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF, is set (PIR3<1>). The flag must be cleared by software. If another capture occurs before the value in the CCPR1H/L register is read, the old captured value is overwritten by the new captured value. The ECCP modules use Timers, 1, 2, 3 and 4, depending on the mode selected. These timers are available to CCP modules in Capture, Compare or PWM modes, as shown in Table 20-1. 20.2.1 ECCP PIN CONFIGURATION In Capture mode, the appropriate ECCP1 pin should be configured as an input by setting the corresponding TRIS direction bit. Note: TABLE 20-1: ECCP Mode ECCP MODE - TIMER RESOURCE Timer Resource If the ECCP1 pin is configured as an output, a write to the port can cause a capture condition. Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 or Timer4 The assignment of a particular timer to a module is determined by the Timer to ECCP enable bits in the CCPTMRS register (Register 20-2). The interactions between the two modules are depicted in Figure 20-1. Capture operations are designed to be used when the timer is configured for Synchronous Counter mode. Capture operations may not work as expected if the associated timer is configured for Asynchronous Counter mode. DS39977C-page 274 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.2.2 TIMER1/2/3/4 MODE SELECTION 20.2.4 ECCP PRESCALER The timers that are to be used with the capture feature (Timer1 2, 3 or 4) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each ECCP module is selected in the CCPTMRS register (Register 20-2). There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP1M<3:0>). Whenever the ECCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 20-1 provides the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. 20.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCP1IF, should also be cleared following any such change in operating mode. EXAMPLE 20-1: CLRF MOVLW CHANGING BETWEEN CAPTURE PRESCALERS MOVWF CCP1CON ; Turn ECCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and ECCP ON CCP1CON ; Load ECCP1CON with ; this value FIGURE 20-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF ECCP1 Pin Prescaler 1, 4, 16 and Edge Detect TMR3H C1TSEL0 C1TSEL1 C1TSEL2 TMR3 Enable CCPR1H C1TSEL0 C1TSEL1 C1TSEL2 TMR1 Enable TMR1H TMR3L CCPR1L CCP1CON<3:0> Q1:Q4 4 4 TMR1L 2011 Microchip Technology Inc. Preliminary DS39977C-page 275 PIC18F66K80 FAMILY 20.3 Compare Mode 20.3.2 TIMER1/2/3/4 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against the Timer register pair value selected in the CCPTMR1 register. When a match occurs, the ECCP1 pin can be: * * * * Driven high Driven low Toggled (high-to-low or low-to-high) Unchanged (that is, reflecting the state of the I/O latch) Timer1, 2, 3 or 4 must be running in Timer mode or Synchronized Counter mode if the ECCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. 20.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the ECCP1 pin is not affected; only the CCP1IF interrupt flag is affected. The action on the pin is based on the value of the mode select bits (CCP1M<3:0>). At the same time, the interrupt flag bit, CCP1IF, is set. 20.3.4 SPECIAL EVENT TRIGGER 20.3.1 ECCP PIN CONFIGURATION Users must configure the ECCP1 pin as an output by clearing the appropriate TRIS bit. Note: The ECCP module is equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCP1M<3:0> = 1011). The Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module's time base. This allows the CCPR1 registers to serve as a programmable Period register for either timer. The Special Event Trigger can also start an A/D conversion. In order to do this, the A/D Converter must already be enabled. Clearing the CCP1CON register will force the ECCP1 compare output latch (depending on device configuration) to the default low level. This is not the port I/O data latch. FIGURE 20-2: COMPARE MODE OPERATION BLOCK DIAGRAM 0 TMR1H TMR1L 1 TMR3H TMR3L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) C1TSEL0 C1TSEL1 C1TSEL2 Set CCP1IF Comparator Compare Match Output Logic 4 CCP1CON<3:0> S R Q ECCP1 Pin CCPR1H CCPR1L TRIS Output Enable DS39977C-page 276 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.4 PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10 bits of resolution. It can do this through four different PWM Output modes: * * * * Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode The PWM outputs are multiplexed with I/O pins and are designated: P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. Table 20-1 provides the pin assignments for each Enhanced PWM mode. Figure 20-3 provides an example of a simplified block diagram of the Enhanced PWM module. Note: To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately. To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. FIGURE 20-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> 2 CCP1M<3:0> 4 Duty Cycle Registers CCPR1L ECCP1/P1A TRIS CCPR1H (Slave) Comparator R Q P1B Output Controller P1C TMR2 (1) S P1D Clear Timer2, Toggle PWM Pin and Latch Duty Cycle ECCP1DEL TRIS TRIS TRIS ECCP1/Output Pin Output Pin Output Pin Comparator Output Pin PR2 Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. 2011 Microchip Technology Inc. Preliminary DS39977C-page 277 PIC18F66K80 FAMILY TABLE 20-2: Single Half-Bridge Full-Bridge, Forward Full-Bridge, Reverse Note 1: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES P1M<1:0> 00 10 01 11 P1A P1B P1C P1D ECCP Mode Yes(1) Yes Yes Yes Yes(1) Yes Yes Yes Yes(1) No Yes Yes Yes(1) No Yes Yes Outputs are enabled by pulse steering in Single mode (see Register 20-5). FIGURE 20-4: P1M<1:0> EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal 0 Pulse Width Period PR2 + 1 00 (Single Output) P1A Modulated Delay(1) P1A Modulated Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 20.4.6 "Programmable Dead-Band Delay Mode"). DS39977C-page 278 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 20-5: P1M<1:0> EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal 0 Pulse Width Period PR2 + 1 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active Delay(1) 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 20.4.6 "Programmable Dead-Band Delay Mode"). 2011 Microchip Technology Inc. Preliminary DS39977C-page 279 PIC18F66K80 FAMILY 20.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 20-6). This mode can be used for half-bridge applications, as shown in Figure 20-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of the P1DC<6:0> bits of the ECCP1DEL register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. For more details on the dead-band delay operations, see Section 20.4.6 "Programmable Dead-Band Delay Mode". Since the P1A and P1B outputs are multiplexed with the port data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 20-6: EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width P1A(2) td P1B(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. FIGURE 20-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A + Load FET Driver P1B + - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver P1A Load FET Driver FET Driver P1B FET Driver DS39977C-page 280 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 20-8. In the Forward mode, the P1A pin is driven to its active state and the P1D pin is modulated, while the P1B and P1C pins are driven to their inactive state, as provided in Figure 20-9. In the Reverse mode, the P1C pin is driven to its active state and the P1B pin is modulated, while the P1A and P1D pins are driven to their inactive state, as provided Figure 20-9. The P1A, P1B, P1C and P1D outputs are multiplexed with the port data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 20-8: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver P1A QA QC FET Driver P1B FET Driver Load FET Driver P1C QB QD VP1D 2011 Microchip Technology Inc. Preliminary DS39977C-page 281 PIC18F66K80 FAMILY FIGURE 20-9: Forward Mode Period P1A (2) EXAMPLE OF FULL-BRIDGE PWM OUTPUT Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS39977C-page 282 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register. The following sequence occurs prior to the end of the current PWM period: * The modulated outputs (P1B and P1D) are placed in their inactive state. * The associated unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. * PWM modulation resumes at the beginning of the next period. For an illustration of this sequence, see Figure 20-10. The Full-Bridge mode does not provide a dead-band delay. As one output is modulated at a time, a dead-band delay is generally not required. There is a situation where a dead-band delay is required. This situation occurs when both of the following conditions are true: * The direction of the PWM output changes when the duty cycle of the output is at or near 100%. * The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 20-11 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time, t1, the P1A and P1D outputs become inactive, while the P1C output becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current will flow through power devices, QC and QD (see Figure 20-8), for the duration of `t'. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: * Reduce PWM duty cycle for one PWM period before changing directions. * Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 20-10: Signal EXAMPLE OF PWM DIRECTION CHANGE Period(1) Period P1A (Active-High) P1B (Active-High) P1C (Active-High) P1D (Active-High) Pulse Width Note 1: 2: The direction bit, P1M1 of the CCP1CON register, is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is: (1/FOSC) * TMR2 Prescale Value. (2) Pulse Width 2011 Microchip Technology Inc. Preliminary DS39977C-page 283 PIC18F66K80 FAMILY FIGURE 20-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B P1C P1D PW PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current T = TOFF - TON Note 1: 2: 3: All signals are shown as active-high. TON is the turn-on delay of power switch, QC, and its driver. TOFF is the turn-off delay of power switch, QD, and its driver. 20.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF or TMR4IF bit of the PIR1 or PIR4 register being set as the second PWM period begins. 20.4.4 ENHANCED PWM AUTO-SHUTDOWN MODE The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCP1AS<2:0> bits (ECCP1AS<6:4>). A shutdown event may be generated by: * A logic `0' on the pin that is assigned the FLT0 input function * Comparator C1 * Comparator C2 * Setting the ECCP1ASE bit in firmware DS39977C-page 284 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY A shutdown condition is indicated by the ECCP1ASE (Auto-Shutdown Event Status) bit (ECCP1AS<7>). If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: * The ECCP1ASE bit is set to `1'. The ECCP1ASE will remain set until cleared in firmware or an auto-restart occurs. (See Section 20.4.5 "Auto-Restart Mode".) * The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (P1A/P1C) and (P1B/P1D). The state of each pin pair is determined by the PSS1AC and PSS1BD bits (ECCP1AS<3:2> and <1:0>, respectively). Each pin pair may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance) REGISTER 20-3: R/W-0 ECCP1ASE bit 7 Legend: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 ECCP1AS1 R/W-0 ECCP1AS0 R/W-0 PSS1AC1 R/W-0 PSS1AC0 R/W-0 PSS1BD1 R/W-0 PSS1BD0 bit 0 ECCP1AS2 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ECCP1ASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 = ECCP outputs are operating ECCP1AS<2:0>: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1OUT output is high 010 = Comparator C2OUT output is high 011 = Either Comparator C1OUT or C2OUT is high 100 = VIL on FLT0 pin 101 = VIL on FLT0 pin or Comparator C1OUT output is high 110 = VIL on FLT0 pin or Comparator C2OUT output is high 111 = VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high PSS1AC<1:0>: P1A and P1C Pins Shutdown State Control bits 00 = Drive pins, P1A and P1C, to `0' 01 = Drive pins, P1A and P1C, to `1' 1x = Pins, P1A and P1C, tri-state PSS1BD<1:0>: P1B and P1D Pins Shutdown State Control bits 00 = Drive pins, P1B and P1D, to `0' 01 = Drive pins, P1B and P1D, to `1' 1x = Pins, P1B and P1D, tri-state bit 6-4 bit 3-2 bit 1-0 Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCP1ASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. 2011 Microchip Technology Inc. Preliminary DS39977C-page 285 PIC18F66K80 FAMILY FIGURE 20-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Event Occurs Shutdown Event Clears ECCP1ASE Cleared by Firmware PWM Resumes 20.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit (ECCP1DEL<7>). If auto-restart is enabled, the ECCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCP1ASE bit will be cleared via hardware and normal operation will resume. The module will wait until the next PWM period begins, however, before re-enabling the output pin. This behavior allows the auto-shutdown with auto-restart features to be used in applications based on current mode of PWM control. FIGURE 20-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (P1RSEN = 1) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Event Occurs Shutdown Event Clears PWM Resumes DS39977C-page 286 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 20-14: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. For an illustration, see Figure 20-14. The lower seven bits of the associated ECCP1DEL register (Register 20-4) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width P1A(2) td P1B(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. FIGURE 20-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A + V Load FET Driver P1B + V - V- 2011 Microchip Technology Inc. Preliminary DS39977C-page 287 PIC18F66K80 FAMILY REGISTER 20-4: R/W-0 P1RSEN bit 7 Legend: ECCP1DEL: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 P1DC5 R/W-0 P1DC4 R/W-0 P1DC3 R/W-0 P1DC2 R/W-0 P1DC1 R/W-0 P1DC0 bit 0 P1DC6 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCP1ASE must be cleared by software to restart the PWM P1DC<6:0>: PWM Delay Count bits P1DCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it does transition active. bit 6-0 20.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can simultaneously be available on multiple pins. Once the Single Output mode is selected (CCP1M<3:2> = 11 and P1M<1:0> = 00 of the CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR Note: While the PWM Steering mode is active, the CCP1M<1:0> bits (CCP1CON<1:0>) select the PWM output polarity for the P1 The associated TRIS bits must be set to output (`0') to enable the pin output driver in order to see the PWM signal on the pin. DS39977C-page 288 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 20-5: R/W-0 CMPL1 bit 7 Legend: PSTR1CON: PULSE STEERING CONTROL(1) R/W-0 U-0 -- R/W-0 STRSYNC R/W-0 STRD R/W-0 STRC R/W-0 STRB R/W-1 STRA bit 0 CMPL0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 00 = See STR bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: The PWM Steering mode is available only when the CCP1CON register bits, CCP1M<3:2> = 11 and P1M<1:0> = 00. 2011 Microchip Technology Inc. Preliminary DS39977C-page 289 PIC18F66K80 FAMILY FIGURE 20-16: STRA P1A Signal CCP1M1 Port Data STRB CCP1M0 Port Data STRC CCP1M1 Port Data STRD CCP1M0 Port Data Note 1: 1 0 1 0 TRIS 1 0 Output Pin 1 0 SIMPLIFIED STEERING BLOCK DIAGRAM(1,2) 20.4.7.1 Steering Synchronization TRIS Output Pin The STRSYNC bit of the PSTR1CON register gives the user two choices for when the steering event will happen. When the STRSYNC bit is `0', the steering event will happen at the end of the instruction that writes to the PSTR1CON register. In this case, the output signal at the P1 TRIS Output Pin Figures 20-17 and 20-18 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. Output Pin TRIS 2: Port outputs are configured as displayed when the CCP1CON register bits, P1M<1:0> = 00 and CCP1M<3:2> = 11. Single PWM output requires setting at least one of the STR FIGURE 20-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STR P1 Port Data P1n = PWM Port Data FIGURE 20-18: PWM EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) STR P1 Port Data P1n = PWM Port Data DS39977C-page 290 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 20.4.8 OPERATION IN POWER-MANAGED MODES 20.4.8.1 Operation with Fail-Safe Clock Monitor (FSCM) In Sleep mode, all clock sources are disabled. Timer2/4 will not increment and the state of the module will not change. If the ECCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HF-INTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCP1 module without change. If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock failure will force the device into the power-managed RC_RUN mode and the OSCFIF bit of the PIR2 register will be set. The ECCP1 will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. 20.4.9 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP registers to their Reset states. This forces the ECCP module to reset to a state compatible with previous, non-enhanced CCP modules used on other PIC18 and PIC16 devices. 2011 Microchip Technology Inc. Preliminary DS39977C-page 291 PIC18F66K80 FAMILY TABLE 20-3: File Name INTCON RCON PIR3 PIE3 IPR3 PIR4 PIE4 IPR4 TRISB TRISC TRISE TMR1H TMR1L TMR2 TMR3H TMR3L TMR4 PR2 PR4 T1CON T2CON T3CON T4CON CCPR1H CCPR1L CCPR2H CCPR2L CCPR3H CCPR3L CCP1CON CCP2CON CCP3CON CCPTMRS ECCP1AS ECCP1DEL PMD0 Note 1: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1/2/3/4 Bit 7 GIE/GIEH IPEN -- -- -- TMR4IF TMR4IE TMR4IP TRISB7 TRISC7 TRISE7 Bit 6 PEIE/GIEL SBOREN -- -- -- EEIF EEIE EEIP TRISB6 TRISC6 TRISE6 Bit 5 TMR0IE CM RC2IF RC2IE RC2IP CMP2IF CMP2IE CMP2IP TRISB5 TRISC5 TRISE5 Bit 4 INT0IE RI TX2IF TX2IE TX2IP CMP1IF CMP1IE CMP1IP TRISB4 TRISC4 TRISE4 Bit 3 RBIE TO CTMUIF CTMUIE CTMUIP -- -- -- TRISB3 TRISC3 -- Bit 2 TMR0IF PD CCP2IF CCP2IE CCP2IP CCP5IF CCP5IE CCP5IP TRISB2 TRISC2 TRISE2 Bit 1 INT0IF POR CCP1IF CCP1IE CCP1IP CCP4IF CCP4IE CCP4IP TRISB1 TRISC1 TRISE1 Bit 0 RBIF BOR -- -- -- CCP3IF CCP3IE CCP3IP TRISB0 TRISC0 TRISE0 Timer1 Register High Byte Timer1 Register Low Byte Timer2 Register Timer3 Register High Byte Timer3 Register Low Byte Timer4 Register Timer2 Period Register Timer4 Period Register TMR1CS1 -- TMR3CS1 -- TMR1CS0 T2OUTPS3 TMR3CS0 T4OUTPS3 T1CKPS1 T2OUTPS2 T3CKPS1 T4OUTPS2 T1CKPS0 T2OUTPS1 T3CKPS0 T4OUTPS1 SOSCEN T2OUTPS0 SOSCEN T4OUTPS0 T1SYNC TMR2ON T3SYNC TMR4ON RD16 T2CKPS1 RD16 T4CKPS1 TMR1ON T2CKPS0 TMR3ON T4CKPS0 Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte Capture/Compare/PWM Register 3 High Byte Capture/Compare/PWM Register 3 Low Byte P1M1 -- -- -- ECCP1ASE P1RSEN P1M0 -- -- -- P1DC6 DC1B1 DC2B1 DC3B1 -- P1DC5 DC1B0 DC2B0 DC3B0 C5TSEL P1DC4 CCP1M3 CCP2M3 CCP3M3 C4TSEL PSS1AC1 P1DC3 CCP1M2 CCP2M2 CCP3M2 C3TSEL PSS1AC0 P1DC2 CCP1M1 CCP2M1 CCP3M1 C2TSEL PSS1BD1 P1DC1 CCP1M0 CCP2M0 CCP3M0 C1TSEL PSS1BD0 P1DC0 ECCP1AS2 ECCP1AS1 ECCP1AS0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Unimplemented on devices with a program memory of 32 Kbytes (PIC18F25K80 and PIC18F46K80). DS39977C-page 292 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview FIGURE 21-1: MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPBUF reg Write 21.1 The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be devices such as serial EEPROMs, shift registers, display drivers and A/D Converters. The MSSP module can operate in either of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode with 5-bit and 7-bit address masking (with address masking for both 10-bit and 7-bit addressing) SDI SSPSR reg SDO bit 0 Shift Clock SS SS Control Enable Edge Select 2 Clock Select SSPM<3:0> SMP:CKE 4 TMR2 Output 2 2 21.2 Control Registers SCK ( ) Edge Select The MSSP module has three associated control registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. Prescaler TOSC 4, 16, 64 Data to TXx/RXx in SSPSR TRIS bit Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. 21.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDA/SDI * Serial Clock (SCK) - RC3/REF0/SCL/SCK Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RA5/AN4/C2INB/ HLVDIN/T1CKI/SS/CTMU1 Figure 21-1 shows the block diagram of the MSSP module when operating in SPI mode. 2011 Microchip Technology Inc. Preliminary DS39977C-page 293 PIC18F66K80 FAMILY 21.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: * MSSP Control Register 1 (SSPCON1) * MSSP Status Register (SSPSTAT) * Serial Receive/Transmit Buffer Register (SSPBUF) * MSSP Shift Register (SSPSR) - Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. REGISTER 21-1: R/W-0 SMP bit 7 Legend: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 R/W-0 CKE(1) R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SMP: Sample bit SPI Master mode: 1 = Input data sampled at the end of data output time 0 = Input data sampled at the middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state D/A: Data/Address bit Used in I2CTM mode only. P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled; SSPEN is cleared. S: Start bit Used in I2C mode only. R/W: Read/Write Information bit Used in I2C mode only. UA: Update Address bit Used in I2C mode only. BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>). DS39977C-page 294 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 21-2: R/W-0 WCOL bit 7 Legend: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 SSPEN(2) R/W-0 CKP R/W-0 SSPM3(3) R/W-0 SSPM2(3) R/W-0 SSPM1(3) R/W-0 SSPM0(3) bit 0 R/W-0 SSPOV(1) R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables the serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables the serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 1010 = SPI Master mode: clock = FOSC/8 0101 = SPI Slave mode: clock = SCK pin; SS pin control disabled; SS can be used as I/O pin 0100 = SPI Slave mode: clock = SCK pin; SS pin control enabled 0011 = SPI Master mode: clock = TMR2 output/2 0010 = SPI Master mode: clock = FOSC/64 0001 = SPI Master mode: clock = FOSC/16 0000 = SPI Master mode: clock = FOSC/4 bit 6 bit 5 bit 4 bit 3-0 Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as inputs or outputs. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 295 PIC18F66K80 FAMILY 21.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP module consists of a Transmit/Receive Shift register (SSPSR) and a Buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 21-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSPSTAT register indicates the various status conditions. 21.3.3 OPEN-DRAIN OUTPUT OPTION The drivers for the SDO output and SCK clock pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. For more information, see Section 11.1.3 "Open-Drain Outputs". The open-drain output option is controlled by the SSPOD bit (ODCON<7>). Setting the SSPOD bit configures the SDO and SCK pins for open-drain operation. EXAMPLE 21-1: LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF LOADING THE SSPBUF (SSPSR) REGISTER SSPSTAT, BF LOOP SSPBUF, W RXDATA TXDATA, W SSPBUF ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit DS39977C-page 296 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.3.4 ENABLING SPI I/O 21.3.5 TYPICAL CONNECTION To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI is automatically controlled by the SPI module * SDO must have the TRISC<5> bit cleared * SCK (Master mode) must have the TRISC<3> bit cleared * SCK (Slave mode) must have the TRISC<3> bit set * SS must have the TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. Figure 21-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data-Slave sends dummy data * Master sends data-Slave sends data * Master sends dummy data-Slave sends data FIGURE 21-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SDO SDI SPI Slave SSPM<3:0> = 010xb Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb SDI SDO Shift Register (SSPSR) MSb LSb SCK PROCESSOR 1 Serial Clock SCK PROCESSOR 2 2011 Microchip Technology Inc. Preliminary DS39977C-page 297 PIC18F66K80 FAMILY 21.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 1, Figure 21-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 21-3, Figure 21-5 and Figure 21-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 64 MHz) of 16 Mbps. Figure 21-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 21-3: Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF SPI MODE WAVEFORM (MASTER MODE) Four Clock Modes bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 bit 7 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 DS39977C-page 298 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device can be configured to wake-up from Sleep. transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode, with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode, with CKE set, then the SS pin control must be enabled. 21.3.8 SLAVE SELECT SYNCHRONIZATION When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with the SS pin control enabled (SSPCON1<3:0> = 04h). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a FIGURE 21-4: SS SLAVE SYNCHRONIZATION WAVEFORM SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit 0 bit 7 bit 7 Next Q4 Cycle after Q2 2011 Microchip Technology Inc. Preliminary DS39977C-page 299 PIC18F66K80 FAMILY FIGURE 21-5: SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) bit 7 bit 0 Next Q4 Cycle after Q2 FIGURE 21-6: SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 DS39977C-page 300 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.3.9 OPERATION IN POWER-MANAGED MODES 21.3.10 EFFECTS OF A RESET In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (SOSC oscillator) or the INTOSC source. See Section 3.3 "Clock Sources and Oscillator Switching" for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupt is enabled, it can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set, and if enabled, will wake the device. A Reset disables the MSSP module and terminates the current transfer. 21.3.11 BUS MODE COMPATIBILITY Table 21-1 shows the compatibility between the standard SPI modes, and the states of the CKP and CKE control bits. TABLE 21-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1 There is also an SMP bit which controls when the data is sampled. TABLE 21-2: Name REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 TRISA TRISC SSPBUF SSPCON1 SSPSTAT ODCON PMD0 GIE/GIEH PEIE/GIEL PSPIF PSPIE PSPIP TRISA7 TRISC7 WCOL SMP SSPOD CCP5MD ADIF ADIE ADIP TRISA6 TRISC6 SSPOV CKE CCP5OD CCP4MD TMR0IE RC1IF RC1IE RC1IP TRISA5 TRISC5 SSPEN D/A CCP4OD CCP3MD INT0IE TX1IF TX1IE TX1IP -- TRISC4 CKP P CCP3OD CCP2MD RBIE SSPIF SSPIE SSPIP TRISA3 TRISC3 SSPM3 S CCP2OD CCP1MD TMR0IF TMR1GIF TMR1GIE TMR1GIP TRISA2 TRISC2 SSPM2 R/W CCP1OD UART2MD INT0IF TMR2IF TMR2IE TMR2IP TRISA1 TRISC1 SSPM1 UA U2OD UART1MD RBIF TMR1IF TMR1IE TMR1IP TRISA0 TRISC0 SSPM0 BF U1OD SSPMD MSSP Receive Buffer/Transmit Register Legend: Shaded cells are not used by the MSSP module in SPI mode. 2011 Microchip Technology Inc. Preliminary DS39977C-page 301 PIC18F66K80 FAMILY 21.4 I2C Mode 21.4.1 REGISTERS The MSSP module in I 2C mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial Clock (SCL) - RC3/REFO/SCL/SCK * Serial Data (SDA) - RC4/SDA/SDI The user must configure these pins as inputs by setting the associated TRIS bits. The MSSP module has seven registers for I2C operation. These are: * * * * MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer Register (SSPBUF) * MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) * I2C Slave Address Mask Register (SSPMSK) SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value. SSPMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPADD; it is only accessible when the SSPM<3:0> bits are specifically set to permit access. Additional details are provided in Section 21.4.3.4 "7-Bit Address Masking Mode". In receive operations, SSPSR and SSPBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. FIGURE 21-7: MSSP BLOCK DIAGRAM (I2CTM MODE) Internal Data Bus Read SCL Shift Clock SSPSR reg SDA MSb SSPBUF reg Write LSb Addr Match Match Detect Address Mask SSPADD reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT reg) Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. DS39977C-page 302 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 21-3: R/W-0 SMP bit 7 Legend: SSPSTAT: MSSP STATUS REGISTER (I2CTM MODE) R-0 D/A R-0 P (1) R/W-0 CKE R-0 S (1) R-0 R/W (2,3) R-0 UA R-0 BF bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: This bit is cleared on Reset and when SSPEN is cleared. This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. 2011 Microchip Technology Inc. Preliminary DS39977C-page 303 PIC18F66K80 FAMILY REGISTER 21-4: R/W-0 WCOL bit 7 Legend: SSPCON1: MSSP CONTROL REGISTER 1 (I2CTM MODE) R/W-0 SSPEN(1) R/W-0 CKP R/W-0 SSPM3(2) R/W-0 SSPM2(2) R/W-0 SSPM1(2) R/W-0 SSPM0(2) bit 0 R/W-0 SSPOV R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: SCK Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1001 = Load SSPMSK register at SSPADD SFR address(3,4) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address bit 6 bit 5 bit 4 bit 3-0 Note 1: 2: 3: 4: When enabled, the SDA and SCL pins must be configured as inputs. Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. When SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address actually access the SSPMSK register. This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is `1'). DS39977C-page 304 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 21-5: R/W-0 GCEN bit 7 Legend: SSPCON2: MSSP CONTROL REGISTER 2 (I2CTM MASTER MODE) R/W-0 ACKDT(1) R/W-0 ACKEN(2) R/W-0 RCEN(2) R/W-0 PEN(2) R/W-0 RSEN(2) R/W-0 SEN(2) bit 0 R/W-0 ACKSTAT R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown GCEN: General Call Enable bit Unused in Master mode. ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2CTM 0 = Receive Idle PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2011 Microchip Technology Inc. Preliminary DS39977C-page 305 PIC18F66K80 FAMILY REGISTER 21-6: R/W-0 GCEN bit 7 Legend: SSPCON2: MSSP CONTROL REGISTER 2 (I2CTM SLAVE MODE) R/W-0 ACKDT(1) R/W-0 ACKEN(1) R/W-0 RCEN(1) R/W-0 PEN(1) R/W-0 RSEN(1) R/W-0 SEN(1) bit 0 R/W-1 ACKSTAT R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown GCEN: General Call Enable bit 1 = Enables interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit Unused in Slave mode. ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit(1) 1 = Initiates Acknowledge sequence on SDA and SCL pins and transmits ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle RCEN: Receive Enable bit (Master Receive mode only)(1) 1 = Enables Receive mode for I2CTM 0 = Receive Idle PEN: Stop Condition Enable bit(1) 1 = Initiates Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enable bit(1) 1 = Initiates Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). REGISTER 21-7: R/W-1 MSK7 bit 7 SSPMSK: I2CTM SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1) R/W-1 MSK5 R/W-1 MSK4 R/W-1 MSK3 R/W-1 MSK2 R/W-1 MSK1 R/W-1 MSK0(2) bit 0 R/W-1 MSK6 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-0 MSK<7:0>: Slave Address Mask Select bit 1 = Masking of corresponding bit of SSPADD enabled 0 = Masking of corresponding bit of SSPADD disabled Note 1: 2: This register shares the same SFR address as SSPADD and is only addressable in select MSSP operating modes. See Section 21.4.3.4 "7-Bit Address Masking Mode" for more details. MSK0 is not used as a mask bit in 7-bit addressing. DS39977C-page 306 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.2 OPERATION 21.4.3.1 Addressing The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I2C operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I2C modes to be selected: * * * * I2C Master mode, clock I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled * I 2C Firmware Controlled Master mode, slave is Idle Selection of any I 2C mode with the SSPEN bit set forces the SCL and SDA pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate TRISC bit. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins. Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register, SSPSR<7:1>, is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. The MSSP Interrupt Flag bit, SSPIF, is set (and interrupt is generated, if enabled) on the falling edge of the ninth SCL pulse. 21.4.3 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an address match. Address masking will allow the hardware to generate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and Stop bits. When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received. * The overflow bit, SSPOV (SSPCON1<6>), was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit, SSPIF, is set. The BF bit is cleared by reading the SSPBUF register, while bit, SSPOV, is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing Parameter 100 and Parameter 101. In 10-Bit Addressing mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. The R/W (SSPSTAT<2>) bit must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit addressing is as follows, with steps, 7 through 9, for the slave-transmitter: 1. 2. Receive first (high) byte of address (bits, SSPIF, BF and UA, are set on address match). Update the SSPADD register with second (low) byte of address (clears bit, UA, and releases the SCL line). Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. Receive second (low) byte of address (bits, SSPIF, BF and UA, are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit, UA. Read the SSPBUF register (clears bit, BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (bits, SSPIF and BF, are set). Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. 3. 4. 5. 6. 7. 8. 9. 2011 Microchip Technology Inc. Preliminary DS39977C-page 307 PIC18F66K80 FAMILY 21.4.3.2 Address Masking Modes Masking an address bit causes that bit to become a "don't care". When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I2C slave behaves the same way, whether address masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking the SSPBUF. The PIC18F66K80 family of devices is capable of using two different Address Masking modes in I2C slave operation: 5-Bit Address Masking and 7-Bit Address Masking. The Masking mode is selected at device configuration using the MSSPMSK Configuration bit. The default device configuration is 7-Bit Address Masking. Both Masking modes, in turn, support address masking of 7-bit and 10-bit addresses. The combination of Masking modes and addresses provide different ranges of Acknowledgable addresses for each combination. While both Masking modes function in roughly the same manner, the way they use address masks are different. of the incoming address. This allows the module to Acknowledge up to 31 addresses when using 7-bit addressing, or 63 addresses with 10-bit addressing (see Example 21-2). This Masking mode is selected when the MSSPMSK Configuration bit is programmed (`0'). The address mask in this mode is stored in the SSPCON2 register, which stops functioning as a control register in I2C Slave mode (Register 21-6). In 7-Bit Addressing mode, address mask bits, ADMSK<5:1> (SSPCON2<5:1>), mask the corresponding address bits in the SSPADD register. For any ADMSK bits that are set (ADMSK Note 1: ADMSK1 masks the two Least Significant bits of the address. 2: The two Most Significant bits of the address are not affected by address masking. 21.4.3.3 5-Bit Address Masking Mode As the name implies, 5-Bit Address Masking mode uses an address mask of up to 5 bits to create a range of addresses to be Acknowledged, using bits, 5 through 1, EXAMPLE 21-2: 7-Bit Addressing: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE SSPADD<7:1>= A0h (1010000) (SSPADD<0> is assumed to be `0') ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh DS39977C-page 308 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.3.4 7-Bit Address Masking Mode Unlike 5-bit masking, 7-Bit Address Masking mode uses a mask of up to 8 bits (in 10-bit addressing) to define a range of addresses that can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 21-3). This mode is the default configuration of the module, which is selected when MSSPMSK is unprogrammed (`1'). The address mask for 7-Bit Address Masking mode is stored in the SSPMSK register, instead of the SSPCON2 register. SSPMSK is a separate hardware register within the module, but it is not directly addressable. Instead, it shares an address in the SFR space with the SSPADD register. To access the SSPMSK register, it is necessary to select MSSP mode, `1001' (SSPCON1<3:0> = 1001) and then read or write to the location of SSPADD. To use 7-Bit Address Masking mode, it is necessary to initialize SSPMSK with a value before selecting the I2C Slave Addressing mode. Thus, the required sequence of events is: 1. 2. 3. Select SSPMSK Access mode (SSPCON2<3:0> = 1001). Write the mask value to the appropriate SSPADD register address (FC8h). Set the appropriate I2C Slave mode (SSPCON2<3:0> = 0111 for 10-bit addressing, 0110 for 7-bit addressing). Setting or clearing mask bits in SSPMSK behaves in the opposite manner of the ADMSK bits in 5-Bit Address Masking mode. That is, clearing a bit in SSPMSK causes the corresponding address bit to be masked; setting the bit requires a match in that position. SSPMSK resets to all `1's upon any Reset condition and, therefore, has no effect on the standard MSSP operation until written with a mask value. With 7-bit addressing, SSPMSK<7:1> bits mask the corresponding address bits in the SSPADD register. For any SSPMSK bits that are active (SSPMSK Note: The two Most Significant bits of the address are not affected by address masking. EXAMPLE 21-3: 7-Bit Addressing: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE = 1010 000 = 1111 001 SSPADD<7:1> SSPMSK<7:1> 10-Bit Addressing: Addresses Acknowledged = ACh, A8h, A4h, A0h SSPADD<7:0> SSPMSK<5:1> = 1010 0000 (The two MSb are ignored in this example since they are not affected) = 1111 0011 Addresses Acknowledged = ACh, A8h, A4h, A0h 2011 Microchip Technology Inc. Preliminary DS39977C-page 309 PIC18F66K80 FAMILY 21.4.3.5 Reception 21.4.3.6 Transmission When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON1<6>), is set. An MSSP interrupt is generated for each data transfer byte. The interrupt flag bit, SSPIF, must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON2<0> = 1), SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 21.4.4 "Clock Stretching" for more details. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin SCL is held low regardless of SEN (see Section 21.4.4 "Clock Stretching" for more details). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, the SCL pin should be enabled by setting bit, CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 21-10). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the SCL pin must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. DS39977C-page 310 Preliminary 2011 Microchip Technology Inc. FIGURE 21-8: 2011 Microchip Technology Inc. Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 R/W = 0 Receiving Data ACK Receiving Data D2 D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent. SDA A7 A6 SCL S 1 2 SSPIF (PIR1<3> or PIR3<7>) I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP (SSPCON<4>) PIC18F66K80 FAMILY (CKP does not reset to `0' when SEN = 0) DS39977C-page 311 FIGURE 21-9: DS39977C-page 312 Receiving Address A5 X A3 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent. SDA A7 A6 SCL S 1 2 PIC18F66K80 FAMILY SSPIF (PIR1<3> or PIR3<7>) I2CTM SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP (SSPCON<4>) (CKP does not reset to `0' when SEN = 0) Note 1: x = Don't care (i.e., address bit can either be a `1' or a `0'). 2011 Microchip Technology Inc. 2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. FIGURE 21-10: 2011 Microchip Technology Inc. R/W = 1 ACK D1 D0 D4 D3 D5 D7 D6 D2 A1 D3 D2 ACK D5 D4 D7 D6 Transmitting Data Transmitting Data D1 D0 ACK A4 A2 A3 4 SCL held low while CPU responds to SSPIF 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software SSPBUF is written in software Clear by reading From SSPIF ISR Cleared in software SSPBUF is written in software From SSPIF ISR CKP is set in software CKP is set in software Receiving Address SDA A7 A6 A5 SCL S 1 2 3 Data in sampled SSPIF (PIR1<3> or PIR3<7>) I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) PIC18F66K80 FAMILY CKP (SSPCON<4>) DS39977C-page 313 FIGURE 21-11: DS39977C-page 314 Clock is held low until update of SSPADD has taken place R/W = 0 A8 D3 D2 D1 D0 ACK A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte ACK Clock is held low until update of SSPADD has taken place 6 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address Receive First Byte of Address SDA 1 1 1 1 0 A9 SCL S 1 2 3 4 5 SSPIF (PIR1<3> or PIR3<7>) Cleared in software PIC18F66K80 FAMILY BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR I2CTM SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) Preliminary SSPOV (SSPCON1<6>) UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated CKP (SSPCON<4>) (CKP does not reset to `0' when SEN = 0) Note 1: x = Don't care (i.e., address bit can either be a `1' or a `0'). 2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. 2011 Microchip Technology Inc. 3: Note that the Most Significant bits of the address are not affected by the bit masking. FIGURE 21-12: Clock is held low until update of SSPADD has taken place R/W = 0 A8 ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 Clock is held low until update of SSPADD has taken place ACK Receive First Byte of Address 0 A9 2011 Microchip Technology Inc. 5 1 2 3 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address SDA 1 1 1 1 SCL S 1 2 3 4 SSPIF (PIR1<3> or PIR3<7>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) Preliminary SSPOV (SSPCON1<6>) UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated CKP (SSPCON<4>) PIC18F66K80 FAMILY (CKP does not reset to `0' when SEN = 0) DS39977C-page 315 FIGURE 21-13: DS39977C-page 316 Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to `1' R/W = 1 ACK D7 D6 D5 Transmitting Data Byte D4 D3 D2 D1 D0 ACK R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place Bus master terminates transfer 4 Sr 6 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address. Receive First Byte of Address SDA 1 1 1 SCL S 1 2 3 PIC18F66K80 FAMILY SSPIF (PIR1<3> or PIR3<7>) I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated CKP (SSPCON1<4>) CKP is set in software CKP is automatically cleared in hardware, holding SCL low 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.4 CLOCK STRETCHING 21.4.4.3 Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. Clock Stretching for 7-Bit Slave Transmit Mode The 7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 21-10). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. 21.4.4.1 Clock Stretching for 7-Bit Slave Receive Mode (SEN = 1) In 7-Bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP bit being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 21-15). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software, regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. 21.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-Bit Slave Receive mode. The first two addresses are followed by a third address sequence, which contains the high-order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 21-13). 21.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. 2011 Microchip Technology Inc. Preliminary DS39977C-page 317 PIC18F66K80 FAMILY 21.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to `0'. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 21-14). FIGURE 21-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX - 1 SCL CKP Master device asserts clock Master device deasserts clock WR SSPCON1 DS39977C-page 318 Preliminary 2011 Microchip Technology Inc. FIGURE 21-15: 2011 Microchip Technology Inc. Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK D2 D1 D0 D7 D6 D5 D4 Receiving Data D3 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent. If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs CKP written to `1' in software SDA A7 A6 SCL S 1 2 SSPIF (PIR1<3> or PIR3<7>) I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) PIC18F66K80 FAMILY CKP (SSPCON<4>) DS39977C-page 319 FIGURE 21-16: DS39977C-page 320 Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D0 D7 D6 D5 D4 D3 D2 ACK D1 D0 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte ACK Clock is held low until update of SSPADD has taken place Clock is not held low because ACK = 1 A9 A8 6 1 2 3 4 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus master terminates transfer Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock Receive First Byte of Address SDA 1 1 1 1 0 SCL S 1 2 3 4 5 SSPIF (PIR1<3> or PIR3<7>) Cleared in software PIC18F66K80 FAMILY BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) Preliminary Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. SSPOV (SSPCON1<6>) UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated CKP (SSPCON<4>) CKP written to `1' in software 2011 Microchip Technology Inc. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. PIC18F66K80 FAMILY 21.4.5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPCON2<7> set). Following a Start bit detect, eight bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device-specific or a general call address. In 10-Bit Addressing mode, the SSPADD is required to be updated for the second half of the address to match and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 21-17). FIGURE 21-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is Compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 D6 Receiving Data D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF BF (SSPSTAT<0>) General Call Address 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) GCEN (SSPCON2<7>) `1' `0' 2011 Microchip Technology Inc. Preliminary DS39977C-page 321 PIC18F66K80 FAMILY 21.4.6 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware if the TRIS bits are set. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDA and SCL. Assert a Repeated Start condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDA and SCL. The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. The following events will cause the MSSP Interrupt Flag bit, SSPIF, to be set (and MSSP interrupt, if enabled): * * * * * Start condition Stop condition Data transfer byte transmitted/received Acknowledge transmitted Repeated Start FIGURE 21-18: MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) 2011 Microchip Technology Inc. Shift Clock SSPSR Receive Enable MSb LSb SSPM<3:0> SSPADD<6:0> SDA SDA In SCL SCL In Bus Collision Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for End of XMIT/RCV Set/Reset S, P (SSPSTAT), WCOL (SSPCON1); Set SSPIF, BCLIF; Reset ACKSTAT, PEN (SSPCON2) DS39977C-page 322 Preliminary Clock Cntl Start bit, Stop bit, Acknowledge Generate PIC18F66K80 FAMILY 21.4.6.1 I2CTM Master Mode Operation A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out the SDA pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out the SDA pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted, 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address, followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received, 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator, used for the SPI mode operation, is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 21.4.7 "Baud Rate" for more details. 2011 Microchip Technology Inc. Preliminary DS39977C-page 323 PIC18F66K80 FAMILY 21.4.7 2 BAUD RATE In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 21-19). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 21-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. The SSPADD BRG value of 00h is not supported. FIGURE 21-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<6:0> SSPM<3:0> SCL Reload Control CLKO Reload BRG Down Counter FOSC/4 TABLE 21-3: FOSC I2CTM CLOCK RATE w/BRG FCY FCY * 2 BRG Value FSCL (2 Rollovers of BRG) 40 MHz 40 MHz 40 MHz 16 MHz 16 MHz 16 MHz 4 MHz 4 MHz 16 MHz(2) Note 1: 2: 10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 4 MHz 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 8 MHz 18h 1Fh 63h 09h 0Ch 27h 02h 09h 03h 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100 kHz 1 MHz(1) The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. A minimum 16-MHz FOSC is required for 1 MHz I2C. DS39977C-page 324 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 21-20). FIGURE 21-20: SDA BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX SCL deasserted but slave holds SCL low (clock arbitration) DX - 1 SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 2011 Microchip Technology Inc. Preliminary DS39977C-page 325 PIC18F66K80 FAMILY 21.4.8 I2CTM MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware. The Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. If, at the beginning of the Start condition, the SDA and SCL pins are already sampled low or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 21.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. FIGURE 21-21: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of Start bit, hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit TBRG TBRG S 2nd bit TBRG SDA SCL DS39977C-page 326 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.9 I2CTM MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, and if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 21.4.9.1 WCOL Status Flag If the user writes the SSPBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 21-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDA = 1, SCL = 1 TBRG SDA RSEN bit set by hardware on falling edge of ninth clock, end of XMIT SCL TBRG Sr = Repeated Start TBRG TBRG 1st bit Write to SSPCON2 occurs here: SDA = 1, SCL (no change). At completion of Start bit, hardware clears RSEN bit and sets SSPIF Write to SSPBUF occurs here TBRG 2011 Microchip Technology Inc. Preliminary DS39977C-page 327 PIC18F66K80 FAMILY 21.4.10 I2CTM MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification Parameter 106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification Parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 21-23). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF flag is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. The user should verify that the WCOL bit is clear after each write to SSPBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. 21.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 21.4.11 I2CTM MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2<3>). Note: The MSSP module must be in an inactive state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting, and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). 21.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 21.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 21.4.10.1 BF Status Flag 21.4.11.3 WCOL Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). 21.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur) after 2 TCY after the SSPBUF write. If SSPBUF is rewritten within 2 TCY, the WCOL bit is set and SSPBUF is updated. This may result in a corrupted transfer. DS39977C-page 328 Preliminary 2011 Microchip Technology Inc. FIGURE 21-23: Write SSPCON2<0> (SEN = 1), Start condition begins From slave, clear ACKSTAT bit (SSPCON2<6>) R/W = 0 ACKSTAT in SSPCON2 = 1 2011 Microchip Technology Inc. SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W, start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 Transmitting Data or Second Half of 10-bit Address D1 D0 ACK SSPIF Cleared in software Cleared in software service routine from MSSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SEN After Start condition, SEN cleared by hardware SSPBUF is written in software PEN R/W I 2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Preliminary PIC18F66K80 FAMILY DS39977C-page 329 FIGURE 21-24: DS39977C-page 330 Write to SSPCON2<4> to start Acknowledge sequence, SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically RCEN = 1, start next receive RCEN cleared automatically ACK ACK from master, SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence, SDA = ACKDT = 1 PEN bit = 1 written here Write to SSPCON2<0> (SEN = 1), begin Start condition SEN = 0 Write to SSPBUF occurs here, start XMIT Transmit Address to Slave SDA D0 A7 A1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 ACK ACK is not sent Bus master terminates transfer SCL Set SSPIF interrupt at end of receive S 1 5 1 2 3 4 5 1 2 3 4 8 5 2 3 4 9 6 7 6 7 8 9 6 7 8 9 Set SSPIF at end of receive P Set SSPIF interrupt at end of Acknowledge sequence PIC18F66K80 FAMILY Data shifted in on falling edge of CLK SSPIF Cleared in software Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software I 2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Preliminary Last bit is shifted into SSPSR and contents are unloaded into SSPBUF Cleared in software SDA = 0, SCL = 1, while CPU responds to SSPIF Set P bit (SSPSTAT<4>) and SSPIF BF (SSPSTAT<0>) SSPOV SSPOV is set because SSPBUF is still full 2011 Microchip Technology Inc. ACKEN PIC18F66K80 FAMILY 21.4.12 ACKNOWLEDGE SEQUENCE TIMING 21.4.13 STOP CONDITION TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG; the SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into an inactive state (Figure 21-25). A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 21-26). 21.4.13.1 WCOL Status Flag 21.4.12.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 21-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2, ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Cleared in software SSPIF set at the end of Acknowledge sequence SSPIF set at the end of receive Note: TBRG = one Baud Rate Generator period. Cleared in software FIGURE 21-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, set PEN Falling edge of 9th clock SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 2011 Microchip Technology Inc. Preliminary DS39977C-page 331 PIC18F66K80 FAMILY 21.4.14 SLEEP OPERATION 2 21.4.17 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION 21.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 21.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high, and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the I2C port to its Idle state (Figure 21-27). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 21-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn't match what is driven by the master; bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS39977C-page 332 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL is sampled low at the beginning of the Start condition (Figure 21-28). SCL is sampled low before SDA is asserted low (Figure 21-29). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 21-30). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to 0. If the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLIF flag is set and * the MSSP module is reset to its inactive state (Figure 21-28) The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. FIGURE 21-28: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SEN cleared automatically because of bus collision. MSSP module reset into Idle state. BCLIF SSPIF SSPIF and BCLIF are cleared in software 2011 Microchip Technology Inc. Preliminary DS39977C-page 333 PIC18F66K80 FAMILY FIGURE 21-29: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S SSPIF `0' `0' `0' `0' SCL SEN FIGURE 21-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG TBRG Set SSPIF SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out Set SEN, enable Start sequence if SDA = 1, SCL = 1 SEN BCLIF `0' S SSPIF SDA = 0, SCL = 1, set SSPIF Interrupts cleared in software DS39977C-page 334 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 21.4.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from a low level to a high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 21-31). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition (see Figure 21-32). If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. When the user deasserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 21-31: SDA BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S SSPIF `0' `0' FIGURE 21-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S SSPIF `0' BCLIF 2011 Microchip Technology Inc. Preliminary DS39977C-page 335 PIC18F66K80 FAMILY 21.4.17.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 21-33). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 21-34). b) FIGURE 21-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P SSPIF `0' `0' FIGURE 21-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL PEN BCLIF P SSPIF `0' `0' SCL goes low before SDA goes high, set BCLIF DS39977C-page 336 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 21-4: Name REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 TRISC SSPBUF SSPADD SSPMSK(1) SSPCON1 SSPCON2 SSPSTAT PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP OSCFIF OSCFIE OSCFIP TRISC7 PEIE/GIEL ADIF ADIE ADIP -- -- -- TRISC6 TMR0IE RC1IF RC1IE RC1IP -- -- -- TRISC5 INT0IE TX1IF TX1IE TX1IP -- -- -- TRISC4 RBIE SSPIF SSPIE SSPIP BCLIF BCLIE BCLIP TRISC3 TMR0IF TMR1GIF TMR1GIE TMR1GIP HLVDIF HLVDIE HLVDIP TRISC2 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP TRISC1 RBIF TMR1IF TMR1IE TMR1IP TMR3GIF TMR3GIE TMR3GIP TRISC0 MSSP Receive Buffer/Transmit Register MSSP Address Register (I2CTM Slave mode), MSSP Baud Rate Reload Register (I2C Master mode) MSK7 WCOL GCEN GCEN SMP CCP5MD SSPOD MSK6 SSPOV ACKSTAT ACKSTAT CKE CCP4MD CCP5OD MSK5 SSPEN ACKDT ADMSK5(2) D/A CCP3MD CCP4OD MSK4 CKP ACKEN ADMSK4(2) P CCP2MD CCP3OD MSK3 SSPM3 RCEN ADMSK3(2) S CCP1MD CCP2OD MSK2 SSPM2 PEN ADMSK2(2) R/W CCP1OD MSK1 SSPM1 RSEN ADMSK1(2) UA U2OD MSK0 SSPM0 SEN SEN BF SSPMD U1OD UART2MD UART1MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. Note 1: SSPMSK shares the same address in SFR space as SSPADD, but is only accessible in certain I2CTM Slave operating modes in 7-Bit Masking mode. See Section 21.4.3.4 "7-Bit Address Masking Mode" for more details. 2: Alternate bit definitions for use in I2C Slave mode operations only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 337 PIC18F66K80 FAMILY NOTES: DS39977C-page 338 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) All members of the PIC18F66K80 family are equipped with two independent EUSART modules, referred to as EUSART1 and EUSART2. They can be configured in the following modes: * Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission * Synchronous - Master (half duplex) with selectable clock polarity * Synchronous - Slave (half duplex) with selectable clock polarity The pins of EUSART1 and EUSART2 are multiplexed with the functions with the following ports, depending on the device pin count. See Table 22-1. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex, asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN/J2602 bus) systems. TABLE 22-1: Pin Count CONFIGURING EUSART PINS(1) USART1 USART2 Port Pins Port Pins 28-pin PORTB RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3 RC6/TX1/CK1 and RC7/RX1/DT1 RE7/TX2/CK2 and RE6/RX2/DT2 PORTC PORTD PORTG RC6/TX1/CK1 and RC7/RX1/DT1 RD6/TX2/CK2/P1C/PSP6 and RD7/RX2/DT2/P1D/PSP7 RG3/TX1/CK1 and RG0/RX1/DT1 40/44-pin PORTC 64-pin Note 1: PORTE The EUSART control will automatically reconfigure the pin from input to output as needed. In order to configure the pins as an EUSART: * For EUSART1: - SPEN (RCSTA1<7>) must be set (= 1) - TRISx 2011 Microchip Technology Inc. Preliminary DS39977C-page 339 PIC18F66K80 FAMILY 22.1 EUSART Control Registers Note: The operation of each Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTAx) * Receive Status and Control (RCSTAx) * Baud Rate Control (BAUDCONx) These are detailed on the following pages in Register 22-1, Register 22-2 and Register 22-3, respectively. Throughout this section, references to register and bit names that may be associated with a specific EUSART module are referred to generically by the use of `x' in place of the specific module number. Thus, "RCSTAx" might refer to the Receive Status register for either EUSART1 or EUSART2. REGISTER 22-1: R/W-x CSRC bit 7 TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-x TXEN(1) R/W-x SYNC R/W-x SENDB R/W-x BRGH R-x TRMT R/W-x TX9D bit 0 R/W-x TX9 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7 bit 6 bit 5 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: SREN/CREN overrides TXEN in Sync mode. DS39977C-page 340 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 22-2: R/W-0 SPEN bit 7 Legend: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 RX9 R/W-0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in Reset) RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and the ninth bit can be used as a parity bit Asynchronous mode 9-Bit (RX9 = 0): Don't care. FERR: Framing Error bit 1 = Framing error (can be cleared by reading the RCREGx register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 341 PIC18F66K80 FAMILY REGISTER 22-3: R/W-0 ABDOVF bit 7 Legend: BAUDCONx: BAUD RATE CONTROL REGISTER R-1 R/W-x RXDTP R/W-0 TXCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0 RCIDL R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active RXDTP: Received Data Polarity Select bit (Asynchronous mode only) Asynchronous mode: 1 = Receive data (RXx) is inverted 0 = Receive data (RXx) is not inverted TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator - SPBRGx only (Compatible mode), SPBRGHx value is ignored Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin: interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character: requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39977C-page 342 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.2 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), also control the baud rate. In Synchronous mode, BRGH is ignored. Table 22-2 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table 22-2. From this, the error in baud rate can be determined. An example calculation is shown in Example 22-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 22-3. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 22.2.1 OPERATION IN POWER-MANAGED MODES The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRGHx:SPBRGx register pair. 22.2.2 SAMPLING The data on the RXx pin (either RC7/CANRX/RX1/DT1 or RB7/PGD/T3G/RX2/DT2/KBI3) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RXx pin. TABLE 22-2: SYNC 0 0 0 0 1 1 BAUD RATE FORMULAS BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x BRG/EUSART Mode Baud Rate Formula Configuration Bits 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[64 (n + 1)] FOSC/[16 (n + 1)] FOSC/[4 (n + 1)] Legend: x = Don't care, n = value of SPBRGHx:SPBRGx register pair 2011 Microchip Technology Inc. Preliminary DS39977C-page 343 PIC18F66K80 FAMILY EXAMPLE 22-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 22-3: Name REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXSTA1 RCSTA1 BAUDCON1 SPBRGH1 SPBRG1 TXSTA2 RCSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 CSRC SPEN ABDOVF TX9 RX9 RCIDL TXEN SREN RXDTP SYNC CREN TXCKP SENDB ADDEN BRG16 BRGH FERR -- TRMT OERR WUE TX9D RX9D ABDEN EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register CSRC SPEN ABDOVF TX9 RX9 RCIDL TXEN SREN RXDTP SYNC CREN TXCKP SENDB ADDEN BRG16 BRGH FERR -- TRMT OERR WUE TX9D RX9D ABDEN EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG. DS39977C-page 344 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 22-4: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 40.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value (decimal) FOSC = 64.000 MHz Actual Rate (K) -- -- -- 9.615 19.231 58.824 111.111 % Error -- -- -- 0.16 0.16 2.13 -3.55 SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) -- 1.221 2.404 9.766 19.531 62.500 104.167 % Error -- 1.73 0.16 1.73 1.73 8.51 -9.58 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) -- 1.202 2.404 9.766 19.531 52.083 78.125 % Error -- 0.16 0.16 1.73 1.73 -9.58 -32.18 SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- -- -- 103 51 16 8 -- -- 255 64 31 10 4 -- 255 129 31 15 4 2 -- 129 64 15 7 2 1 SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 8.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 8.929 20.833 62.500 62.500 % Error 0.16 0.16 0.16 -6.99 8.51 8.51 -45.75 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 -- -- -- -- -- % Error -0.16 -0.16 -- -- -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- 103 51 12 -- -- -- 207 51 25 6 2 0 0 103 25 12 -- -- -- -- 51 12 -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 64.000 MHz Actual Rate (K) -- -- -- -- 19.417 59.701 121.212 % Error -- -- -- -- 1.13 3.65 5.22 SPBRG value (decimal) FOSC = 40.000 MHz Actual Rate (K) -- -- -- 9.766 19.231 58.140 113.636 % Error -- -- -- 1.73 0.16 0.94 -1.36 SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) -- -- -- 9.615 19.231 56.818 113.636 % Error -- -- -- 0.16 0.16 -1.36 -1.36 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- -- -- -- 207 68 34 -- -- -- 255 129 42 21 -- -- -- 129 64 21 10 -- -- 255 64 31 10 4 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 8.000 MHz Actual Rate (K) -- -- 2.403 9.615 19.230 55.555 -- % Error -- -- -0.16 -0.16 -0.16 3.55 -- SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate (K) -- 1.202 2.404 9.615 19.231 62.500 125.000 % Error -- 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- -- 207 51 25 8 -- -- 207 103 25 12 3 1 -- 103 51 12 -- -- -- 207 51 25 -- -- -- -- 2011 Microchip Technology Inc. Preliminary DS39977C-page 345 PIC18F66K80 FAMILY TABLE 22-4: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value (decimal) FOSC = 64.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.592 19.417 59.701 121.212 % Error 0.00 0.00 0.00 -0.08 1.13 3.65 5.22 SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.399 9.615 19.231 56.818 113.636 % Error 0.02 -0.03 -0.03 0.16 0.16 -1.36 -1.36 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.531 56.818 125.000 % Error 0.02 -0.03 0.16 0.16 1.73 -1.36 8.51 SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 13332 3332 1666 416 207 68 34 8332 2082 1040 259 129 42 21 4165 1041 520 129 64 21 10 2082 520 259 64 31 10 4 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 8.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 9.615 19.231 62.500 125.000 % Error 0.04 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 -- -- -- % Error -0.16 -0.16 -0.16 -0.16 -- -- -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 1665 415 207 51 25 8 -- 832 207 103 25 12 3 1 415 103 51 12 -- -- -- 207 51 25 -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 64.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.598 19.208 57.348 115.108 % Error 0.00 0.00 0.00 -0.02 0.04 -0.44 -0.08 SPBRG value (decimal) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.606 19.193 57.803 114.943 % Error 0.00 0.00 0.02 0.06 -0.03 0.35 -0.22 SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.596 19.231 57.471 116.279 % Error 0.00 0.02 0.02 -0.03 0.16 -0.22 0.94 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 53332 13332 6666 1666 832 278 138 33332 8332 4165 1040 520 172 86 16665 4165 2082 520 259 86 42 8332 2082 1040 259 129 42 21 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 8.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.615 19.230 57.142 117.647 % Error -0.01 -0.04 -0.04 -0.16 -0.16 0.79 -2.12 SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.231 58.824 111.111 % Error 0.01 0.04 0.16 0.16 0.16 2.12 -3.55 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 -- -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 6665 1665 832 207 103 34 16 3332 832 415 103 51 16 8 1665 415 207 51 25 8 -- 832 207 103 25 12 -- -- DS39977C-page 346 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.2.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 22-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value, 55h (ASCII "U", which is also the LIN/J2602 bus Sync character), in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRGx begins counting up, using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCONx<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 22-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. The BRG clock will be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table 22-5 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. 3: To maximize baud rate range, if that feature is used it is recommended that the BRG16 bit (BAUDCONx<3>) be set. TABLE 22-5: BRG16 0 0 1 1 BRGH 0 1 0 1 BRG COUNTER CLOCK RATES BRG Counter Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32 22.2.3.1 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREGx cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. 2011 Microchip Technology Inc. Preliminary DS39977C-page 347 PIC18F66K80 FAMILY FIGURE 22-1: BRG Value RXx pin AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 001Ch Edge #5 Stop Bit BRG Clock Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx SPBRGHx XXXXh XXXXh 1Ch 00h Auto-Cleared Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 22-2: BRG Clock ABDEN bit RXx pin ABDOVF bit BRG OVERFLOW SEQUENCE Start Bit 0 FFFFh BRG Value XXXXh 0000h 0000h DS39977C-page 348 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.3 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software. TXxIF is also not cleared immediately upon loading TXREGx, but becomes valid in the second instruction cycle following the load instruction. Polling TXxIF immediately following a load of TXREGx will return invalid results. While TXxIF indicates the status of the TXREGx register; another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit, TXxIF, is set when enable bit, TXEN, is set. To set up an Asynchronous Transmission: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. Enable the transmission by setting bit, TXEN, which will also set bit, TXxIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Load data to the TXREGx register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. 2. 3. 4. 5. 6. 7. 8. 22.3.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 22-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREGx register (if available). FIGURE 22-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXxIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPEN TSR Register TXREGx Register 8 LSb 0 Pin Buffer and Control TXx pin BRG16 SPBRGHx SPBRGx Baud Rate Generator TX9 TX9D 2011 Microchip Technology Inc. Preliminary DS39977C-page 349 PIC18F66K80 FAMILY FIGURE 22-4: Write to TXREGx BRG Output (Shift Clock) TXx (pin) TXxIF bit (Transmit Buffer Reg. Empty Flag) ASYNCHRONOUS TRANSMISSION Word 1 Start bit 1 TCY bit 0 bit 1 Word 1 bit 7/8 Stop bit TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg FIGURE 22-5: Write to TXREGx ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) TXxIF bit (Interrupt Reg. Flag) 1 TCY 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0 TRMT bit (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS39977C-page 350 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 22-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTA1 TXREG1 TXSTA1 BAUDCON1 SPBRGH1 SPBRG1 RCSTA2 TXREG2 TXSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP -- -- -- SPEN CSRC ABDOVF PEIE/GIEL ADIF ADIE ADIP -- -- -- RX9 TX9 RCIDL TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP RBIE SSPIF SSPIE SSPIP CTMUIF CTMUIE CTMUIP ADDEN SENDB BRG16 TMR0IF TMR1GIF TMR1GIE TMR1GIP CCP2IF CCP2IE CCP2IP FERR BRGH -- INT0IF TMR2IF TMR2IE TMR2IP CCP1IF CCP1IE CCP1IP OERR TRMT WUE RBIF TMR1IF TMR1IE TMR1IP -- -- -- RX9D TX9D ABDEN EUSART1 Transmit Register EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register Low Byte SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RXDTP CREN SYNC TXCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EUSART2 Transmit Register EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD SSPOD CCP4MD CCP5OD CCP3MD CCP4OD CCP2MD CCP3OD CCP1MD CCP2OD UART2MD UART1MD CCP1OD U2OD SSPMD U1OD Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. 2011 Microchip Technology Inc. Preliminary DS39977C-page 351 PIC18F66K80 FAMILY 22.3.2 EUSART ASYNCHRONOUS RECEIVER 22.3.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT The receiver block diagram is shown in Figure 22-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 3. If interrupts are desired, set enable bit, RCxIE. 4. If 9-bit reception is desired, set bit, RX9. 5. Enable the reception by setting bit, CREN. 6. Flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCxIE, was set. 7. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREGx register. 9. If any error occurred, clear the error by clearing enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCxIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCxIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCxIE and GIE bits are set. 8. Read the RCSTAx register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREGx to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 1. FIGURE 22-6: EUSART RECEIVE BLOCK DIAGRAM CREN x64 Baud Rate CLK OERR FERR BRG16 SPBRGHx SPBRGx Baud Rate Generator 64 or 16 or 4 MSb Stop (8) 7 RSR Register 1 0 LSb Start RX9 Pin Buffer and Control RXx Data Recovery RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF RCxIE Data Bus DS39977C-page 352 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 22-7: RXx (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. ASYNCHRONOUS RECEPTION Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 1 RCREGx Word 2 RCREGx Note: TABLE 22-7: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTA1 RCREG1 TXSTA1 BAUDCON1 SPBRGH1 SPBRG1 RCSTA2 RCREG2 TXSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP -- -- -- SPEN CSRC ABDOVF PEIE/GIEL ADIF ADIE ADIP -- -- -- RX9 TX9 RCIDL TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP RBIE SSPIF SSPIE SSPIP CTMUIF CTMUIE CTMUIP ADDEN SENDB BRG16 TMR0IF TMR1GIF TMR1GIE TMR1GIP CCP2IF CCP2IE CCP2IP FERR BRGH -- INT0IF TMR2IF TMR2IE TMR2IP CCP1IF CCP1IE CCP1IP OERR TRMT WUE RBIF TMR1IF TMR1IE TMR1IP -- -- -- RX9D TX9D ABDEN EUSART1 Receive Register EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RXDTP CREN SYNC TXCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EUSART2 Receive Register EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD SSPOD CCP4MD CCP5OD CCP3MD CCP4OD CCP2MD CCP3OD CCP1MD CCP2OD UART2MD UART1MD CCP1OD U2OD SSPMD U1OD Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. 2011 Microchip Technology Inc. Preliminary DS39977C-page 353 PIC18F66K80 FAMILY 22.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER 22.3.4.1 Special Considerations Using Auto-Wake-up During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 22-8) and asynchronously if the device is in Sleep mode (Figure 22-9). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false End-of-Character (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN/J2602 bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., HS or HSPLL mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. DS39977C-page 354 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.3.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCxIF flag is set should not be used as an indicator of the integrity of the data in RCREGx. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 22-8: OSC1 WUE bit(1) RXx/DTx Line RCxIF AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user Auto-Cleared Cleared due to user read of RCREGx Note 1: The EUSART remains in Idle while the WUE bit is set. FIGURE 22-9: OSC1 WUE bit(2) RXx/DTx Line RCxIF AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user Auto-Cleared Note 1 Sleep Ends Cleared due to user read of RCREGx SLEEP Command Executed Note 1: 2: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2011 Microchip Technology Inc. Preliminary DS39977C-page 355 PIC18F66K80 FAMILY 22.3.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>, respectively) are set while the Transmit Shift Register is loaded with data. Note that the value of data written to TXREGx will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN/J2602 specification). Note that the data value written to the TXREGx for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 22-10 for the timing of the Break character sequence. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to TXREGx. 22.3.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 22.3.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RXx/DTx, cause an RCxIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. 22.3.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN/J2602 bus master. FIGURE 22-10: Write to TXREGx BRG Output (Shift Clock) TXx (pin) SEND BREAK CHARACTER SEQUENCE Dummy Write Start Bit Bit 0 Bit 1 Break Bit 11 Stop Bit TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here SENDB bit (Transmit Shift Reg. Empty Flag) Auto-Cleared DS39977C-page 356 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.4 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register. While flag bit, TXxIF, indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. The Synchronous Master mode is entered by setting the CSRC bit (TXSTAx<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTAx<4>). In addition, enable bit, SPEN (RCSTAx<7>), is set in order to configure the TXx and RXx pins to CKx (clock) and DTx (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CKx line. Clock polarity is selected with the TXCKP bit (BAUDCONx<4>). Setting TXCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 22.4.1 EUSART SYNCHRONOUS MASTER TRANSMISSION 2. 3. 4. 5. 6. 7. 8. The EUSART transmitter block diagram is shown in Figure 22-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). FIGURE 22-11: SYNCHRONOUS TRANSMISSION Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/CANRX/RX1/ DT1/CCP4Pin RC6/CANTX/TX1/CK1/ CCP3/Pin (TXCKP = 0) RC6/CANTX/TX1/CK1/ CCP3/Pin (TXCKP = 1) Write to TxREG1 Reg Tx1IF bit (Interrupt Flag) TRMT bit TxEN bit `1' bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 Write Word 1 Write Word 2 `1' Note: Sync Master mode, SPBRGx = 0; continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3). 2011 Microchip Technology Inc. Preliminary DS39977C-page 357 PIC18F66K80 FAMILY FIGURE 22-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit 0 bit 1 bit 2 bit 6 bit 7 RC7/CANRX/RX1/DT1/ CCP4 Pin RC6/CANTX/TX1/CK1/ CCP3 Pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3). TABLE 22-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTA1 TXREG1 TXSTA1 BAUDCON1 SPBRGH1 SPBRG1 RCSTA2 TXREG2 TXSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP -- -- -- SPEN CSRC ABDOVF PEIE/GIEL ADIF ADIE ADIP -- -- -- RX9 TX9 RCIDL TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP RBIE SSPIF SSPIE SSPIP CTMUIF CTMUIE CTMUIP ADDEN SENDB BRG16 TMR0IF TMR1GIF TMR1GIE TMR1GIP CCP2IF CCP2IE CCP2IP FERR BRGH -- INT0IF TMR2IF TMR2IE TMR2IP CCP1IF CCP1IE CCP1IP OERR TRMT WUE RBIF TMR1IF TMR1IE TMR1IP -- -- -- RX9D TX9D ABDEN EUSART1 Transmit Register EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register Low Byte SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RXDTP CREN SYNC TXCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EUSART2 Transmit Register EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD SSPOD CCP4MD CCP5OD CCP3MD CCP4OD CCP2MD CCP3OD CCP1MD CCP2OD UART2MD UART1MD CCP1OD U2OD SSPMD U1OD Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. DS39977C-page 358 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.4.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>) or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCxIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCxIE, was set. 8. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREGx register. 10. If any error occurred, clear the error by clearing bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. 3. 4. 5. 6. FIGURE 22-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/CANRX/ RX1/DT1/CCP4 RC6/CANTX/TX1/ CK1/CCP3 (TXCKP = 0) RC6/CANTX/TX1/ CK1/CCP3 (TXCKP = 0) Write to bit, SREN SREN bit CREN bit `0' RC1IF bit (Interrupt) Read RCREG1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 `0' Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3). 2011 Microchip Technology Inc. Preliminary DS39977C-page 359 PIC18F66K80 FAMILY TABLE 22-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTA1 RCREG1 TXSTA1 BAUDCON1 SPBRGH1 SPBRG1 RCSTA2 RCREG2 TXSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP -- -- -- SPEN CSRC ABDOVF PEIE/GIEL ADIF ADIE ADIP -- -- -- RX9 TX9 RCIDL TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP RBIE SSPIF SSPIE SSPIP CTMUIF CTMUIE CTMUIP ADDEN SENDB BRG16 TMR0IF TMR1GIF TMR1GIE TMR1GIP CCP2IF CCP2IE CCP2IP FERR BRGH -- INT0IF TMR2IF TMR2IE TMR2IP CCP1IF CCP1IE CCP1IP OERR TRMT WUE RBIF TMR1IF TMR1IE TMR1IP -- -- -- RX9D TX9D ABDEN EUSART1 Receive Register EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register Low Byte SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RXDTP CREN SYNC TXCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EUSART2 Receive Register EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD SSPOD CCP4MD CCP5OD CCP3MD CCP2MD CCP4OD CCP3OD CCP1MD CCP2OD UART2MD UART1MD CCP1OD U2OD SSPMD U1OD Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. DS39977C-page 360 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 22.5 EUSART Synchronous Slave Mode e) If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. Clear bits, CREN and SREN. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting enable bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. To set up a Synchronous Slave Transmission: 1. 22.5.1 EUSART SYNCHRONOUS SLAVE TRANSMISSION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep mode. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREGx register. Flag bit, TXxIF, will not be set. When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. 2. 3. 4. 5. 6. 7. 8. TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTA1 TXREG1 TXSTA1 BAUDCON1 SPBRGH1 SPBRG1 RCSTA2 TXREG2 TXSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP -- -- -- SPEN CSRC ABDOVF PEIE/GIEL ADIF ADIE ADIP -- -- -- RX9 TX9 RCIDL TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP RBIE SSPIF SSPIE SSPIP CTMUIF CTMUIE CTMUIP ADDEN SENDB BRG16 TMR0IF TMR1GIF TMR1GIE TMR1GIP CCP2IF CCP2IE CCP2IP FERR BRGH -- INT0IF TMR2IF TMR2IE TMR2IP CCP1IF CCP1IE CCP1IP OERR TRMT WUE RBIF TMR1IF TMR1IE TMR1IP -- -- -- RX9D TX9D ABDEN EUSART1 Transmit Register EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register Low Byte SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RXDTP CREN SYNC TXCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EUSART2 Transmit Register EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD SSPOD CCP4MD CCP5OD CCP3MD CCP4OD CCP2MD CCP3OD CCP1MD CCP2OD UART2MD UART1MD CCP1OD U2OD SSPMD U1OD Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. 2011 Microchip Technology Inc. Preliminary DS39977C-page 361 PIC18F66K80 FAMILY 22.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. If interrupts are desired, set enable bit, RCxIE. If 9-bit reception is desired, set bit, RX9. To enable reception, set enable bit, CREN. Flag bit, RCxIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCxIE, was set. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREGx register. If any error occurred, clear the error by clearing bit, CREN. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREGx register. If the RCxIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. 6. 7. 8. 9. TABLE 22-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTA1 RCREG1 TXSTA1 BAUDCON1 SPBRGH1 SPBRG1 RCSTA2 RCREG2 TXSTA2 BAUDCON2 SPBRGH2 SPBRG2 PMD0 ODCON GIE/GIEH PSPIF PSPIE PSPIP -- -- -- SPEN CSRC ABDOVF PEIE/GIEL ADIF ADIE ADIP -- -- -- RX9 TX9 RCIDL TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP RBIE SSPIF SSPIE SSPIP CTMUIF CTMUIE CTMUIP ADDEN SENDB BRG16 TMR0IF TMR1GIF TMR1GIE TMR1GIP CCP2IF CCP2IE CCP2IP FERR BRGH -- INT0IF TMR2IF TMR2IE TMR2IP CCP1IF CCP1IE CCP1IP OERR TRMT WUE RBIF TMR1IF TMR1IE TMR1IP -- -- -- RX9D TX9D ABDEN EUSART1 Receive Register EUSART1 Baud Rate Generator Register High Byte EUSART1 Baud Rate Generator Register Low Byte SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RXDTP CREN SYNC TXCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EUSART2 Receive Register EUSART2 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register Low Byte CCP5MD SSPOD CCP4MD CCP5OD CCP3MD CCP4OD CCP2MD CCP3OD CCP1MD CCP2OD UART2MD UART1MD CCP1OD U2OD SSPMD U1OD Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. DS39977C-page 362 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 23.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE 23.1 Differential A/D Converter The converter in PIC18F66K80 family devices is implemented as a differential A/D where the differential voltage between two channels is measured and converted to digital values (see Figure 23-1). The converter also can be configured to measure a voltage from a single input by clearing the CHSN bits (ADCON1<2:0>). With this configuration, the negative channel input is connected internally to AVSS (see Figure 23-2). The Analog-to-Digital (A/D) Converter module in the PIC18F66K80 family of devices has eight inputs for the 28-pin devices, 11 inputs for the 40/44-pin and 64-pin devices. This module allows conversion of an analog input signal to a corresponding 12-bit digital number. The module has these registers: * * * * * * * A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) A/D Port Configuration Register 1 (ANCON0) A/D Port Configuration Register 2 (ANCON1) ADRESH (the upper, A/D Results register) ADRESL (the lower, A/D Results register) FIGURE 23-1: DIFFERENTIAL CHANNEL MEASUREMENT Positive input CHS<4:0> Negative input CHSN<2:0> The ADCON0 register, shown in Register 23-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 23-2, configures the voltage reference and special trigger selection. The ADCON2 register, shown in Register 23-3, configures the A/D clock source and programmed acquisition time and justification. + - ADC Differential conversion feeds the two input channels to a unity gain differential amplifier. The positive channel input is selected using the CHS bits (ADCON0<6:2>) and the negative channel input is selected using the CHSN bits (ADCON1<2:0>). The output from the amplifier is fed to the A/D Converter, as shown in Figure 23-1. The 12-bit result is available on the ADRESH and ADRESL registers. An additional bit indicates if the 12-bit result is a positive or negative value. FIGURE 23-2: Positive Input CHS<4:0> CHSN<2:0> = 000 SINGLE CHANNEL MEASUREMENT + - ADC AVSS In the Single Channel Measurement mode, the negative input is connected to AVSS by clearing the CHSN bits (ADCON1<2:0>). 2011 Microchip Technology Inc. Preliminary DS39977C-page 363 PIC18F66K80 FAMILY 23.2 23.2.1 A/D Registers A/D CONTROL REGISTERS ADCON0: A/D CONTROL REGISTER 0 R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0 REGISTER 23-1: U-0 -- bit 7 Legend: R/W-0 CHS4 R = Readable bit -n = Value at POR bit 7 bit 6-2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CHS<4:0>: Analog Channel Select bits 00000 = Channel 00 (AN0) 00001 = Channel 01 (AN1) 00010 = Channel 02 (AN2) 00011 = Channel 03 (AN3) 00100 = Channel 04 (AN4) 00101 = Channel 05 (AN5)(1,2) 00110 = Channel 06 (AN6)(1,2) 00111 = Channel 07 (AN7)(1,2) 01000 = Channel 08 (AN8) 01001 = Channel 09 (AN9) 01010 = Channel 10 (AN10) 01011 = (Reserved)(2) 01100 = (Reserved)(2)) 01101 = (Reserved)(2)) 01110 = (Reserved)(2)) 01111 = (Reserved)(2) 10000 = (Reserved)(2) 10001 = (Reserved)(2) 10010 = (Reserved)(2) 10011 = (Reserved)(2) 10100 = (Reserved)(2) 10101 = (Reserved)(2) 10110 = (Reserved)(2) 10111 = (Reserved)(2) 11000 = (Reserved)(2) 11001 = (Reserved)(2) 11010 = (Reserved)(2) 11011 = (Reserved)(2) 11100 = (MUX disconnect)(3) 11101 = Channel 29 (temperature diode) 11110 = Channel 30 (VDDCORE) 11111 = Channel 31 (1.024V band gap) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D cycle is in progress. Setting this bit starts an A/D conversion cycle. The bit is cleared automatically by hardware when the A/D conversion is completed. 0 = A/D conversion has completed or is not in progress ADON: A/D On bit 1 = A/D Converter is operating 0 = A/D conversion module is shut off and consuming no operating current bit 0 Note 1: 2: 3: These channels are not implemented on 28-pin devices. Performing a conversion on unimplemented channels will return random values. Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of the ADC input, for finer resolution CTMU time measurements. DS39977C-page 364 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 23-2: R/W-0 TRIGSEL1 bit 7 Legend: ADCON1: A/D CONTROL REGISTER 1 R/W-0 VCFG1 R/W-0 VCFG0 R/W-x VNCFG R/W-x CHSN2 R/W-x CHSN1 R/W-x CHSN0 bit 0 R/W-0 TRIGSEL0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRIGSEL<1:0>: Special Trigger Select bits 11 = Selects the special trigger from the CCP2 10 = Selects the special trigger from the Timer1 01 = Selects the special trigger from the CTMU 00 = Selects the special trigger from the ECCP1 VCFG<1:0>: A/D VREF+ Configuration bits 11 = Internal VREF+ (4.096V) 10 = Internal VREF+ (2.048V) 01 = External VREF+ 00 = AVDD VNCFG: A/D VREF- Configuration bit 1 = External VREF 0 = AVSS CHSN<2:0>: Analog Negative Channel Select bits 111 = Channel 07 (AN6) 110 = Channel 06 (AN5) 101 = Channel 05 (AN4) 100 = Channel 04 (AN3) 011 = Channel 03 (AN2) 010 = Channel 02 (AN1) 001 = Channel 01 (AN0) 000 = Channel 00 (AVSS) bit 5-4 bit 3 bit 2-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 365 PIC18F66K80 FAMILY REGISTER 23-3: R/W-0 ADFM bit 7 Legend: ADCON2: A/D CONTROL REGISTER 2 U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 6 bit 5-3 bit 2-0 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. DS39977C-page 366 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 23.2.2 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is where the 12-bit A/D result and extended sign bits (ADSGN) are loaded at the completion of a conversion. This register pair is 16 bits wide. The A/D module gives the flexibility of left or right justifying the 12-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 23-3 shows the operation of the A/D result justification and location of the extended sign bits (ADSGN). The extended sign bits allow for easier 16-bit math to be performed on the result. When the A/D Converter is disabled, these 8-bit registers can be used as two, general purpose registers. FIGURE 23-3: A/D RESULT JUSTIFICATION 12-Bit Result Left Justified ADFM = 0 Right Justified ADFM = 1 ADRESH ADRESL ADRESH ADRESL Result bits ADSGN bits 2010 _18_0001 REGISTER 23-4: R/W-x ADRES11 bit 7 Legend: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x ADRES9 R/W-x ADRES8 R/W-x ADRES7 R/W-x ADRES6 R/W-x ADRES5 R/W-x ADRES4 ADRES10 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADRES<11:4>: A/D Result High Byte bits 2011 Microchip Technology Inc. Preliminary DS39977C-page 367 PIC18F66K80 FAMILY REGISTER 23-5: R/W-x ADRES3 bit 7 Legend: ADRESL: A/D RESULT LOW BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x U-x ADRES1 U-x ADRES0 U-x ADSGN U-x ADSGN U-x ADSGN R/W-x ADSGN ADRES2 R = Readable bit -n = Value at POR bit 7-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADRES<3:0>: A/D Result Low Byte bits ADSGN: A/D Result Sign bit 1 = A/D result is negative 0 = A/D result is positive REGISTER 23-6: U-x ADSGN bit 7 Legend: ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) U-x U-x ADSGN U-x ADSGN R/W-x ADRES11 R/W-x ADRES10 R/W-x ADRES9 R/W-x ADRES8 ADSGN R = Readable bit -n = Value at POR bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADSGN: A/D Result Sign bit 1 = A/D result is negative 0 = A/D result is positive ADRES<11:8>: A/D Result High Byte bits bit 3-0 REGISTER 23-7: R/W-x ADRES7 bit 7 Legend: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) R/W-x R/W-x ADRES5 R/W-x ADRES4 R/W-x ADRES3 R/W-x ADRES2 R/W-x ADRES1 R/W-x ADRES0 ADRES6 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADRES<7:0>: A/D Result Low Byte bits DS39977C-page 368 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY The ANCONx registers are used to configure the operation of the I/O pin associated with each analog channel. Clearing an ANSELx bit configures the corresponding pin (ANx) to operate as a digital only I/O. Setting a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator module, with all digital peripherals disabled and digital inputs read as `0'. As a rule, I/O pins that are multiplexed with analog inputs default to analog operation on any device Reset. REGISTER 23-8: R/W-x ANSEL7(1) bit 7 Legend: ANCON0: A/D PORT CONFIGURATION REGISTER 0 R/W-x (1) R/W-x ANSEL6 R/W-x (1) R/W-x ANSEL3 R/W-x ANSEL2 R/W-x ANSEL1 R/W-x ANSEL0 bit 0 ANSEL5 ANSEL4 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0)(1) 1 = Pin configured as an analog channel: digital input disabled and any inputs read as `0' 0 = Pin configured as a digital port Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect. REGISTER 23-9: U-1 -- bit 7 Legend: ANCON1: A/D PORT CONFIGURATION REGISTER 1 R/W-x ANSEL13(1) R/W-x ANSEL12(1) R/W-x ANSEL11(1) R/W-x ANSEL10 R/W-x ANSEL9 R/W-x ANSEL8 bit 0 R/W-x ANSEL14(1) R = Readable bit -n = Value at POR bit 7 bit 6-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' ANSEL<14:8>: Analog Port Configuration bits (AN14 through AN8)(1) 1 = Pin configured as an analog channel: digital input disabled and any inputs read as `0' 0 = Pin configured as a digital port Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect. Each port pin associated with the A/D Converter can be configured as an analog input or a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF (PIR1<6>), is set. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. The value in the ADRESH:ADRESL register pair is not modified for a Power-on Reset. These registers will contain unknown data after a Power-on Reset. The block diagram of the A/D module is shown in Figure 23-4. The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS) or the voltage level on the RA3/VREF+/AN3 and RA2/VREF-/AN2 pins. VREF+ has two additional internal voltage reference selections: 2.048V and 4.096V. The A/D Converter can uniquely operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. 2011 Microchip Technology Inc. Preliminary DS39977C-page 369 PIC18F66K80 FAMILY FIGURE 23-4: A/D BLOCK DIAGRAM CHS<4:0> 11111 11110 11101 11100 11011 11010 11001 11000 1.024V Band Gap VDDCORE Reserved Temperature Diode (MUX Disconnected)(3) (Unimplemented) (Unimplemented) (Unimplemented) (Unimplemented) 01110 12-Bit A/D Converter 01101 AN14(1) AN13(1) 00100 00011 00010 00001 00000 AN4 AN3 AN2 AN1 AN0 Positive Input Voltage CHSN<2:0> 111 110 Negative Input Voltage Reference Voltage VCFG<1:0> Internal VREF+ (4.096V) Internal VREF+ (2.048V) AN3 VDD(4) AN6 AN5 VREF+ VREFVNCFG AN2 11 10 01 00 001 000 AN0 AVSS(4) VSS(2,4) Note 1: Channels, AN14 through AN11, and AN7 through AN5, are implemented only on 40/44-pin and 64-pin devices. For 28-pin devices, the corresponding ANSELx bits are still implemented for those channels, but have no effect. 2: I/O pins have diode protection to VDD and VSS. 3: Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of ADC inputs for finer resolution CTMU time measurements. 4: I/O pins have diode protection to VDD and VSS. DS39977C-page 370 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion can start. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 23.3 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. To do an A/D conversion, follow these steps: 1. Configure the A/D module: * Configure the required ADC pins as analog pins (ANCON0 and ANCON1) * Set the voltage reference (ADCON1) * Select the A/D positive and negative input channels (ADCON0 and ADCON1) * Select the A/D acquisition time (ADCON2) * Select the A/D conversion clock (ADCON2) * Turn on the A/D module (ADCON0) 2. Configure the A/D interrupt (if desired): * Clear the ADIF bit (PIR1<6>) * Set the ADIE bit (PIE1<6>) * Set the GIE bit (INTCON<7>) Wait the required acquisition time (if required). Start the conversion: * Set the GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL) and, if required, clear bit, ADIF. For the next conversion, begin with step 1 or 2, as required. The A/D conversion time per bit is defined as TAD. Before the next acquisition starts, a minimum wait of 2 TAD is required. 3. 4. 5. FIGURE 23-5: ANALOG INPUT MODEL VDD VT = 0.6V RIC 1k Sampling Switch SS RSS RS ANx VAIN CPIN 5 pF VT = 0.6V ILEAKAGE 100 nA CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance VDD 1 2 3 4 Sampling Switch (k) 2011 Microchip Technology Inc. Preliminary DS39977C-page 371 PIC18F66K80 FAMILY 23.3 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the Charge Holding (CHOLD) capacitor must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 23-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected or changed, the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: To calculate the minimum acquisition time, Equation 23-1 can be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Equation 23-3 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD Rs VDD Temperature = 25 pF = 2.5 k = 3V Rss = 2 k = 85C (system max.) Conversion Error 1/2 LSb When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 23-1: TACQ = = ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF EQUATION 23-2: VHOLD or TC = = A/D MINIMUM CHARGING TIME (VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 23-3: TACQ TAMP TCOFF = = = 0.2 s CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TAMP + TC + TCOFF (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s 0.2 s + 1.05 s + 1.2 s 2.45 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = TACQ = DS39977C-page 372 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 23.4 Selecting and Configuring Automatic Acquisition Time TABLE 23-1: TAD vs. DEVICE OPERATING FREQUENCIES Maximum Device Frequency AD Clock Source (TAD) Operation ADCS<2:0> 000 100 001 101 010 110 x11 The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits (ADCON2<5:3>) remain in their Reset state (`000'), which is compatible with devices that do not offer programmable acquisition times. If desired, the ACQTx bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(2) Note 1: 2: 2.50 MHz 5.00 MHz 10.00 MHz 20.00 MHz 40.00 MHz 64.00 MHz 1.00 MHz(1) The RC source has a typical TAD time of 4 s. For device frequencies above 1 MHz, the device must be in Sleep mode for the entire conversion or the A/D accuracy may be out of specification. 23.6 Configuring Analog Port Pins The ANCON0, ANCON1, TRISA, TRISB, TRISC and TRISC registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRISx bits set (input). If the TRISx bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<3:0> bits and the TRISx bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 23.5 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 14 TAD per 12-bit conversion. The source of the A/D conversion clock is software selectable. The possible options for TAD are: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Using the internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD. (For more information, see Parameter 130 in Table 31-26.) Table 23-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. 2011 Microchip Technology Inc. Preliminary DS39977C-page 373 PIC18F66K80 FAMILY 23.7 A/D Conversions Figure 23-6 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 23-7 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<2:0> bits set to `010' and a 4 TAD acquisition time selected. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 23-6: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 b1 b0 b6 b3 b2 b8 b9 b4 b5 b11 b10 b7 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 23-7: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles 1 2 3 4 1 2 b11 3 b10 4 b9 TAD Cycles 5 b8 6 b7 7 b6 8 b5 9 b4 10 b3 11 b2 12 b1 13 b0 Automatic Acquisition Time Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39977C-page 374 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 23.8 Use of the Special Event Triggers 23.9 A/D conversion can be started by the Special Event Trigger of any of these modules: * CCP2 - Requires CCP2M<3:0> bits (CCP2CON<3:0>) set at `1011'() * ECCP1 * CTMU - Requires the setting of the CTTRIG bit (CTMUCONH<0>) * Timer1 To start an A/D conversion: * The A/D module must be enabled (ADON = 1) * The appropriate analog input channel selected * The minimum acquisition period set one of these ways: - Timing provided by the user - Selection made of an appropriate TACQ time With these conditions met, the trigger sets the GO/DONE bit and the A/D acquisition starts. If the A/D module is not enabled (ADON = 0), the module ignores the Special Event Trigger. Note: Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined, in part, by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in Sleep mode requires that the A/D RC clock be selected. If bits, ACQT<2:0>, are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry into Sleep mode. The IDLEN and SCS<1:0> bits in the OSCCON register must have already been cleared prior to starting the conversion. With an ECCP1 or CCP2 trigger, Timer1 or Timer3 is cleared. The timers reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). If the A/D module is not enabled, the Special Event Trigger is ignored by the module, but the timer's counter resets. 2011 Microchip Technology Inc. Preliminary DS39977C-page 375 PIC18F66K80 FAMILY TABLE 23-2: Name REGISTERS ASSOCIATED WITH THE A/D MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON PIR1 PIE1 IPR1 ADRESH ADRESL ADCON0 ADCON1 ADCON2 ANCON0 ANCON1 PORTA TRISA PORTB TRISB PORTE TRISE PMD1 GIE/GIEH PSPIF PSPIE PSPIP PEIE/GIEL ADIF ADIE ADIP TMR0IE RC1IF RC1IE RC1IP INT0IE TX1IF TX1IE TX1IP RBIE SSPIF SSPIE SSPIP TMR0IF TMR1GIF TMR1GIE TMR1GIP INT0IF TMR2IF TMR2IE TMR2IP RBIF TMR1IF TMR1IE TMR1IP A/D Result Register High Byte A/D Result Register Low Byte -- TRIGSEL1 ADFM ANSEL7 -- RA7(1) TRISA7 RB7 TRISB7 RE7 TRISE7 PSPMD (1) CHS4 TRIGSEL0 -- ANSEL6 ANSEL14 RA6(1) TRISA6 RB6 TRISB6 RE6 TRISE6 CTMUMD (1) CHS3 VCFG1 ACQT2 ANSEL5 ANSEL13 RA5 TRISA5 RB5 TRISB5 RE5 TRISE5 ADCMD CHS2 VCFG0 ACQT1 ANSEL4 ANSEL12 -- -- RB4 TRISB4 RE4 TRISE4 TMR4MD CHS1 VNCFG ACQT0 ANSEL3 ANSEL11 RA3 TRISA3 RB3 TRISB3 RE3(2) -- TMR3MD CHS0 CHSN2 ADCS2 ANSEL2 ANSEL10 RA2 TRISA2 RB2 TRISB2 -- TRISE2 TMR2MD GO/DONE CHSN1 ADCS1 ANSEL1 ANSEL9 RA1 TRISA1 RB1 TRISB1 RE1 TRISE1 TMR1MD ADON CHSN0 ADCS0 ANSEL0 ANSEL8 RA0 TRISA0 RB0 TRISB0 RE0 TRISE0 TMR0MD Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: These bits are available only in certain oscillator modes when the FOSC2 Configuration bit = 0. If that Configuration bit is cleared, this signal is not implemented. 2: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. DS39977C-page 376 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 24.0 COMPARATOR MODULE 24.1 Registers The analog comparator module contains two comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation are also available. A generic single comparator from the module is shown in Figure 24-1. Key features of the module includes: * * * * * Independent comparator control Programmable input configuration Output to both pin and register levels Programmable output polarity Independent interrupt generation for each comparator with configurable interrupt-on-change The CMxCON registers (CM1CON and CM2CON) select the input and output configuration for each comparator, as well as the settings for interrupt generation (see Register 24-1). The CMSTAT register (Register 24-2) provides the output results of the comparators. The bits in this register are read-only. FIGURE 24-1: CCH<1:0> CxINB CxINC C2INB/C2IND(1) VBG CREF COMPARATOR SIMPLIFIED BLOCK DIAGRAM CMPxOUT (CMSTAT<7:6>) 0 1 2 3 EVPOL<1:0> VIN- Interrupt Logic CMPxIF COE Cx Polarity Logic CxOUT CxINA CVREF 0 1 VIN+ CON CPOL Note 1: Comparator 1 uses C2INB as an input to the inverted terminal. Comparator 2 uses C1INB as an input to the inverted terminal. 2011 Microchip Technology Inc. Preliminary DS39977C-page 377 PIC18F66K80 FAMILY REGISTER 24-1: R/W-0 CON bit 7 Legend: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 CPOL R/W-1 EVPOL1 R/W-1 EVPOL0 R/W-1 CREF R/W-1 CCH1 R/W-1 CCH0 bit 0 COE R/W-0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted EVPOL<1:0>: Interrupt Polarity Select bits 11 = Interrupt generation on any change of the output(1) 10 = Interrupt generation only on high-to-low transition of the output 01 = Interrupt generation only on low-to-high transition of the output 00 = Interrupt generation is disabled CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG 10 = Inverting input of comparator connects to C2INB pin(2) 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to C1INB pin(2) bit 6 bit 5 bit 4-3 bit 2 bit 1-0 Note 1: 2: The CMPxIF is automatically set any time this mode is selected and must be cleared by the application after the initial configuration. Comparator 1 uses C2INB as an input to the inverting terminal. Comparator 2 uses C1INB as an input to the inverted terminal. DS39977C-page 378 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 24-2: R-x CMP2OUT bit 7 Legend: CMSTAT: COMPARATOR STATUS REGISTER R-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 CMP1OUT R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CMP2OUT:CMP1OUT: Comparator x Status bits If CPOL (CMxCON<5>)= 0 (non-inverted polarity): 1 = Comparator x's VIN+ > VIN0 = Comparator x's VIN+ < VINIf CPOL = 1 (inverted polarity): 1 = Comparator x's VIN+ < VIN0 = Comparator x's VIN+ > VINUnimplemented: Read as `0' bit 4-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 379 PIC18F66K80 FAMILY 24.2 Comparator Operation 24.3 Comparator Response Time A single comparator is shown in Figure 24-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 24-2 represent the uncertainty due to input offsets and response time. Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response to a comparator input change. Otherwise, the maximum delay of the comparators should be used (see Section 31.0 "Electrical Characteristics"). FIGURE 24-2: VINVIN+ SINGLE COMPARATOR - + 24.4 Analog Input Connection Considerations Output VINVIN+ A simplified circuit for an analog input is shown in Figure 24-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Output FIGURE 24-3: COMPARATOR ANALOG INPUT MODEL VDD RS <10 k AIN CPIN 5 pF VT = 0.6V VT = 0.6V RIC Comparator Input ILEAKAGE 100 nA VA VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage DS39977C-page 380 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 24.5 Comparator Control and Configuration The external reference is used when CREF = 0 (CMxCON<2>) and VIN+ is connected to the CxINA pin. When external voltage references are used, the comparator module can be configured to have the reference sources externally. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator. The comparator module also allows the selection of an internally generated voltage reference (CVREF) from the comparator voltage reference module. This module is described in more detail in Section 25.0 "Comparator Voltage Reference Module". The reference from the comparator voltage reference module is only available when CREF = 1. In this mode, the internal voltage reference is applied to the comparator's VIN+ pin. Note: Each comparator has up to eight possible combinations of inputs: up to four external analog inputs and one of two internal voltage references. All of the comparators allow a selection of the signal from pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is compared to either C1INB, CxINC, C2INB or the microcontroller's fixed internal reference voltage (VBG, 1.024V nominal) on the inverting channel. The comparator inputs and outputs are tied to fixed I/O pins, defined in Table 24-1. The available comparator configurations and their corresponding bit settings are shown in Figure 24-4. TABLE 24-1: Comparator COMPARATOR INPUTS AND OUTPUTS Input or Output I/O Pin() The comparator input pin selected by CCH<1:0> must be configured as an input by setting both the corresponding TRIS bit and the corresponding ANSELx bit in the ANCONx register. C1INA (VIN+) C1INB (VIN-) 1 C1INC (VIN-) C2INB(VIN-) C1OUT C2INA(VIN+) 2 C2INB(VIN-) C2INC(VIN-) C2OUT RB0/RD0 RB1/RD1 RA1 RA5/RD3 RB2/RE1 RB4/RD2 RA5/RD3 RA2 RB3/RE2 24.5.2 COMPARATOR ENABLE AND OUTPUT SELECTION The comparator outputs are read through the CMSTAT register. The CMSTAT<6> bit reads the Comparator 1 output, CMSTAT<7> reads the Comparator 2 output. These bits are read-only. The comparator outputs may also be directly output to the RE2 and RE1 pins by setting the COE bit (CMxCON<6>). When enabled, multiplexers in the output path of the pins switch to the output of the comparator. While in this mode, the TRISE<2:1> bits still function as the digital output enable bits for the RE2, and RE1 pins. By default, the comparator's output is at logic high whenever the voltage on VIN+ is greater than on VIN-. The polarity of the comparator outputs can be inverted using the CPOL bit (CMxCON<5>). The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications, as discussed in Section 24.2 "Comparator Operation". The I/O pin is dependent on package type. 24.5.1 COMPARATOR ENABLE AND INPUT SELECTION Setting the CON bit of the CMxCON register (CMxCON<7>) enables the comparator for operation. Clearing the CON bit disables the comparator, resulting in minimum current consumption. The CCH<1:0> bits in the CMxCON register (CMxCON<1:0>) direct either one of three analog input pins, or the Internal Reference Voltage (VBG), to the comparator, VIN-. Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly. 2011 Microchip Technology Inc. Preliminary DS39977C-page 381 PIC18F66K80 FAMILY FIGURE 24-4: COMPARATOR CONFIGURATIONS COE VINVIN+ Comparator Off CON = 0, CREF = x, CCH<1:0> = xx Cx Off (Read as `0') CxOUT Pin Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE CxINB CxINA VINVIN+ COE CxINC VINVIN+ Cx CxOUT Pin CxINA Cx CxOUT Pin Comparator C2INB/C1INB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11 COE C2INB/ C1INB CxINA VINVIN+ COE VBG VINVIN+ Cx CxOUT Pin CxINA Cx CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 01 COE CxINB CVREF VINVIN+ COE CxINC VINVIN+ Cx CxOUT Pin CVREF Cx CxOUT Pin Comparator C2INB/C1INB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 10 Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 11 COE C2INB/ C1INB CVREF VINVIN+ COE VBG VINVIN+ Cx CxOUT Pin CVREF Cx CxOUT Pin Note 1: VBG is the Internal Reference Voltage (see Table 31-2). DS39977C-page 382 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 24.6 Comparator Interrupts The comparator interrupt flag is set whenever any of the following occurs: * Low-to-high transition of the comparator output * High-to-low transition of the comparator output * Any change in the comparator output The comparator interrupt selection is done by the EVPOL<1:0> bits in the CMxCON register (CMxCON<4:3>). In order to provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit in the CMxCON register (CMxCON<5>). This is functionally identical to reversing the inverting and non-inverting inputs of the comparator for a particular mode. An interrupt is generated on the low-to-high or high-tolow transition of the comparator output. This mode of interrupt generation is dependent on EVPOL<1:0> in the CMxCON register. When EVPOL<1:0> = 01 or 10, the interrupt is generated on a low-to-high or high-tolow transition of the comparator output. Once the interrupt is generated, it is required to clear the interrupt flag by software. When EVPOL<1:0> = 11, the comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMSTAT<7:6>, to determine the actual change that occurred. The CMPxIF<2:0> (PIR4<5:4) bits are the Comparator Interrupt Flags. The CMPxIF bits must be reset by clearing them. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Table 24-2 shows the interrupt generation with respect to comparator input voltages and EVPOL bit settings. Both the CMPxIE bits (PIE4<5:4>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMPxIF bits will still be set if an interrupt condition occurs. A simplified diagram of the interrupt section is shown in Figure 24-3. Note: CMPxIF will not EVPOL<1:0> = 00. be set when TABLE 24-2: CPOL COMPARATOR INTERRUPT GENERATION EVPOL<1:0> 00 01 Comparator Input Change CxOUT Transition Interrupt Generated VIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VIN- Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High No No Yes No No Yes Yes Yes No No No Yes Yes No Yes Yes 0 10 11 00 01 1 10 11 2011 Microchip Technology Inc. Preliminary DS39977C-page 383 PIC18F66K80 FAMILY 24.7 Comparator Operation During Sleep To minimize power consumption while in Sleep mode, turn off the comparators (CON = 0) before entering Sleep. If the device wakes up from Sleep, the contents of the CMxCON register are not affected. When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current. 24.8 Effects of a Reset A device Reset forces the CMxCON registers to their Reset state. This forces both comparators and the voltage reference to the OFF state. TABLE 24-3: Name REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON CM1CON CM2CON CVRCON CMSTAT PIR4 PIE4 IPR4 ANCON0 ANCON1 PMD2 Legend: GIE/GIEH CON CON CVREN CMP2OUT TMR4IF TMR4IE TMR4IP ANSEL7 -- -- PEIE/GIEL COE COE CVROE CMP1OUT EEIF EEIE EEIP ANSEL6 ANSEL14 -- TMR0IE CPOL CPOL CVRSS -- CMP2IF CMP2IE CMP2IP ANSEL5 ANSEL13 -- INT0IE EVPOL1 EVPOL1 CVR4 -- CMP1IF CMP1IE CMP1IP ANSEL4 ANSEL12 -- RBIE EVPOL0 EVPOL0 CVR3 -- -- -- -- ANSEL3 ANSEL11 MODMD TMR0IF CREF CREF CVR2 -- CCP5IF CCP5IE CCP5IP ANSEL2 ANSEL10 ECANMD INT0IF CCH1 CCH1 CVR1 -- CCP4IF CCP4IE CCP4IP ANSEL1 ANSEL9 CMP2MD RBIF CCH0 CCH0 CVR0 -- CCP3IF CCP3IE CCP3IP ANSEL0 ANSEL8 CMP1MD -- = unimplemented, read as `0'. DS39977C-page 384 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 25.0 COMPARATOR VOLTAGE REFERENCE MODULE EQUATION 25-1: If CVRSS = 1: CVREF = VREF- + The comparator voltage reference is a 32-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 25-1. The resistor ladder is segmented to provide a range of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. ( ( CVR<4:0> 32 ) * (VREF+ - VREF-) ) * (AVDD - AVSS) If CVRSS = 0: CVREF = AVSS + CVR<4:0> 32 25.1 Configuring the Comparator Voltage Reference The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA3 and RA2. The voltage source is selected by the CVRSS bit (CVRCON<5>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 31-2 in Section 31.0 "Electrical Characteristics"). The comparator voltage reference module is controlled through the CVRCON register (Register 25-1). The comparator voltage reference provides a range of output voltage with 32 levels. The CVR<4:0> selection bits (CVRCON<4:0>) offer a range of output voltages. Equation 25-1 shows the how the comparator voltage reference is computed. REGISTER 25-1: R/W-0 CVREN bit 7 Legend: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 CVRSS R/W-0 CVR4 R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0 R/W-0 CVROE R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ - VREF0 = Comparator reference source, CVRSRC = AVDD - AVSS CVR<4:0>: Comparator VREF Value Selection 0 CVR<4:0> 31 bits When CVRSS = 1: CVREF = (VREF-) + (CVR<4:0>/32) (VREF+ - VREF-) When CVRSS = 0: CVREF = (AVSS) + (CVR<4:0>/32) (AVDD - AVSS) bit 6 bit 5 bit 4-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 385 PIC18F66K80 FAMILY FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R R R R CVR<4:0> CVREN 32 Steps 32-to-1 MUX R CVREF R R R VREF- CVRSS = 1 CVRSS = 0 25.2 Voltage Reference Accuracy/Error 25.4 Effects of a Reset The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 25-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 31.0 "Electrical Characteristics". A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset also disconnects the reference from the RF5 pin by clearing bit, CVROE (CVRCON<6>). 25.5 Connection Considerations 25.3 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA0 pin if the CVROE bit is set. Enabling the voltage reference output onto RA0 when it is configured as a digital input will increase current consumption. Connecting RA0 as a digital output with CVRSS enabled will also increase current consumption. The RA0 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 25-2 shows an example buffering technique. DS39977C-page 386 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F66K80 CVREF Module R(1) Voltage Reference Output Impedance RA0 + - CVREF Output Note 1: R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 25-1: Name REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVRCON CM1CON CM2CON TRISA ANCON0 CVREN CON CON TRISA7 ANSEL7 CVROE COE COE TRISA6 ANSEL6 CVRSS CPOL CPOL TRISA5 ANSEL5 CVR4 EVPOL1 EVPOL1 -- ANSEL4 CVR3 EVPOL0 EVPOL0 TRISA3 ANSEL3 CVR2 CREF CREF TRISA2 ANSEL2 CVR1 CCH1 CCH1 TRISA1 ANSEL1 CVR0 CCH0 CCH0 TRISA0 ANSEL0 Legend: -- = unimplemented, read as `0'. Shaded cells are not used with the comparator voltage reference. 2011 Microchip Technology Inc. Preliminary DS39977C-page 387 PIC18F66K80 FAMILY NOTES: DS39977C-page 388 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 26.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The High/Low-Voltage Detect Control register (Register 26-1) completely controls the operation of the HLVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. The module's block diagram is shown in Figure 26-1. The PIC18F66K80 family of devices has a High/LowVoltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt. REGISTER 26-1: R/W-0 VDIRMAG bit 7 Legend: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R-0 R-0 IRVST R/W-0 HLVDEN R/W-0 HLVDL3(1) R/W-0 HLVDL2 (1) R/W-0 HLVDL1 (1) R/W-0 HLVDL0(1) bit 0 BGVST R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Internal band gap voltage references are stable 0 = Internal band gap voltage references are not stable IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting bit 6 bit 5 bit 4 bit 3-0 Note 1: For the electrical specifications, see Parameter D042 in Section 31.0 "Electrical Characteristics". 2011 Microchip Technology Inc. Preliminary DS39977C-page 389 PIC18F66K80 FAMILY The module is enabled by setting the HLVDEN bit (HLVDCON<4>). Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit (HLVDCON<5>) is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. The VDIRMAG bit (HLVDCON<7>) determines the overall operation of the module. When VDIRMAG is cleared, the module monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises in VDD above the set point. trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The trip point voltage is software programmable to any one of 16 values. The trip point is selected by programming the HLVDL<3:0> bits (HLVDCON<3:0>). The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, HLVDL<3:0>, are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, HLVDIN. This gives users the flexibility of configuring the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. 26.1 Operation When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a FIGURE 26-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) VDD Externally Generated Trip Point VDD HLVDL<3:0> HLVDCON Register HLVDIN HLVDEN VDIRMAG HLVDEN 16-to-1 MUX Set HLVDIF BOREN Internal Voltage Reference 1.024V Typical DS39977C-page 390 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 26.2 1. 2. 3. 4. 5. HLVD Setup 26.3 Current Consumption To set up the HLVD module: Select the desired HLVD trip point by writing the value to the HLVDL<3:0> bits. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE bits (PIE2<2> and INTCON<7>, respectively). An interrupt will not be generated until the IRVST bit is set. Note: When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The total current consumption, when enabled, is specified in electrical specification Parameter D022B (Ihlvd) (Table 31-11). Depending on the application, the HLVD module does not need to operate constantly. To reduce current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After such a check, the module could be disabled. 26.4 HLVD Start-up Time Before changing any module settings (VDIRMAG, HLVDL<3:0>), first disable the module (HLVDEN = 0), make the changes and re-enable the module. This prevents the generation of false HLVD events. The internal reference voltage of the HLVD module, specified in electrical specification Parameter 37 (Section 31.0 "Electrical Characteristics"), may be used by other internal circuitry, such as the programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification Parameter 37 (Table 31-11). The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see Figure 26-2 or Figure 26-3). 2011 Microchip Technology Inc. Preliminary DS39977C-page 391 PIC18F66K80 FAMILY FIGURE 26-2: CASE 1: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST Internal reference is stable CASE 2: HLVDIF cleared in software VDD VHLVD HLVDIF Enable HLVD IRVST Internal reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists TIRVST DS39977C-page 392 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 26-3: CASE 1: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST Internal reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists TIRVST 26.5 Applications FIGURE 26-4: For general battery applications, Figure 26-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, which would allow the application to perform "housekeeping tasks" and a controlled shutdown before the device voltage exits the valid operating range at TB. This would give the application a time window, represented by the difference between TA and TB, to safely exit. Voltage In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin). TYPICAL LOW-VOLTAGE DETECT APPLICATION VA VB Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage 2011 Microchip Technology Inc. Preliminary DS39977C-page 393 PIC18F66K80 FAMILY 26.6 Operation During Sleep 26.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. TABLE 26-1: Name REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HLVDCON INTCON PIR2 PIE2 IPR2 TRISA VDIRMAG GIE/GIEH OSCFIF OSCFIE OSCFIP TRISA7(1) BGVST PEIE/GIEL -- -- -- TRISA6(1) IRVST TMR0IE -- -- -- TRISA5 HLVDEN INT0IE -- -- -- -- HLVDL3 RBIE BCLIF BCLIE BCLIP TRISA3 HLVDL2 TMR0IF HLVDIF HLVDIE HLVDIP TRISA2 HLVDL1 INT0IF TMR3IF TMR3IE TMR3IP TRISA1 HLVDL0 RBIF TMR3GIF TMR3GIE TMR3GIP TRISA0 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the HLVD module. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. DS39977C-page 394 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.0 ECAN MODULE 27.1 Module Overview PIC18F66K80 family devices contain an Enhanced Controller Area Network (ECAN) module. The ECAN module is fully backward compatible with the CAN module available in PIC18CXX8 and PIC18FXX8 devices and the ECAN module in PIC18Fxx80 devices. The Controller Area Network (CAN) module is a serial interface which is useful for communicating with other peripherals or microcontroller devices. This interface, or protocol, was designed to allow communications within noisy environments. The ECAN module is a communication controller, implementing the CAN 2.0A or B protocol as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system; however, the CAN specification is not covered within this data sheet. Refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol, CAN 1.2, CAN 2.0A and CAN 2.0B * DeviceNetTM data bytes filter support * Standard and extended data frames * 0-8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Fully backward compatible with the PIC18XXX8 CAN module * Three modes of operation: - Mode 0 - Legacy mode - Mode 1 - Enhanced Legacy mode with DeviceNet support - Mode 2 - FIFO mode with DeviceNet support * Support for remote frames with automated handling * Double-buffered receiver with two prioritized received message storage buffers * Six buffers programmable as RX and TX message buffers * 16 full (standard/extended identifier) acceptance filters that can be linked to one of four masks * Two full acceptance filter masks that can be assigned to any filter * One full acceptance filter that can be used as either an acceptance filter or acceptance filter mask * Three dedicated transmit buffers with application specified prioritization and abort capability * Programmable wake-up functionality with integrated low-pass filter * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to timer module for time-stamping and network synchronization * Low-power Sleep mode The CAN bus module consists of a protocol engine and message buffering and control. The CAN protocol engine automatically handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the two receive registers. The CAN module supports the following frame types: * * * * * Standard Data Frame Extended Data Frame Remote Frame Error Frame Overload Frame Reception The CAN module uses the RB2/CANTX and RB3/ CANRX pins to interface with the CAN bus. The CANTX and CANRX pins can be placed on alternate I/O pins by setting the CANMX (CONFIG3H<0>) Configuration bit. For the PIC18F2XK80 and PIC18F4XK80, the alternate pin locations are RC6/CANTX and RC7/CANRX. For the PIC18F6XK80, the alternate pin locations are RE4/CANRX and RE5/CANTX. In normal mode, the CAN module automatically overrides the appropriate TRIS bit for CANTX. The user must ensure that the appropriate TRIS bit for CANRX is set. 27.1.1 MODULE FUNCTIONALITY The CAN bus module consists of a protocol engine, message buffering and control (see Figure 27-1). The protocol engine can best be understood by defining the types of data frames to be transmitted and received by the module. The following sequence illustrates the necessary initialization steps before the ECAN module can be used to transmit or receive a message. Steps can be added or removed depending on the requirements of the application. 1. 2. 3. 4. 5. 6. Initial LAT and TRIS bits for RX and TX CAN. Ensure that the ECAN module is in Configuration mode. Select ECAN Operational mode. Set up the Baud Rate registers. Set up the Filter and Mask registers. Set the ECAN module to normal mode or any other mode required by the application logic. 2011 Microchip Technology Inc. Preliminary DS39977C-page 395 PIC18F66K80 FAMILY FIGURE 27-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM 16 - 4 to 1 MUXs Acceptance Filters (RXF0-RXF05) MODE 0 Acceptance Mask RXM0 Acceptance Mask RXM1 BUFFERS TXB0 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF TXB1 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF TXB2 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF A c c e p t VCC Acceptance Filters (RXF06-RXF15) MODE 1, 2 MODE 0 2 RX Buffers RXF15 Message Queue Control Transmit Byte Sequencer Identifier Data Field M A B Rcv Byte MODE 1, 2 6 TX/RX Buffers Transmit Option MESSAGE BUFFERS PROTOCOL ENGINE Receive Error Counter Transmit Error Counter REC TEC Err-Pas Bus-Off Transmit<7:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator Receive<8:0> CRC<14:0> Protocol Finite State Machine Transmit Logic Bit Timing Logic Clock Generator Configuration Registers TX RX DS39977C-page 396 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.2 Note: CAN Module Registers Not all CAN registers are available in the Access Bank. 27.2.1 CAN CONTROL AND STATUS REGISTERS There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: * * * * * * * Control and Status Registers Dedicated Transmit Buffer Registers Dedicated Receive Buffer Registers Programmable TX/RX and Auto RTR Buffers Baud Rate Control Registers I/O Control Register Interrupt Status and Control Registers The registers described in this section control the overall operation of the CAN module and show its operational status. Detailed descriptions of each register and their usage are described in the following sections. 2011 Microchip Technology Inc. Preliminary DS39977C-page 397 PIC18F66K80 FAMILY REGISTER 27-1: Mode 0 CANCON: CAN CONTROL REGISTER R/W-0 REQOP1 R/W-0 REQOP1 R/W-0 REQOP1 R/W-0 REQOP0 R/W-0 REQOP0 R/W-0 REQOP0 R/S-0 ABAT R/S-0 ABAT R/S-0 ABAT R/W-0 WIN2 U0 -- R-0 FP3 R/W-0 WIN1 U-0 -- R-0 FP2 R/W-0 WIN0 U-0 -- R-0 FP1 U-0 -- U-0 -- R-0 FP0 bit 0 S = Settable bit W = Writable bit `1' = Bit is set R/W-1 REQOP2 R/W-1 REQOP2 R/W-1 REQOP2 bit 7 Mode 1 Mode 2 Legend: R = Readable bit -n = Value at POR U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-5 bit 4 bit 3-1 bit 0 bit 4-0 REQOP<2:0>: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Disabled/Sleep mode 000 = Request Normal mode ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers)(1) 0 = Transmissions proceeding as normal Mode 0: WIN<2:0>: Window Address bits These bits select which of the CAN buffers to switch into the Access Bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE<3:0> bits can be copied to the WIN<2:0> bits to select the correct buffer. See Example 27-2 for a code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 Mode 0: Unimplemented: Read as `0' Mode 1: Unimplemented: Read as `0' Mode 2: FP<3:0>: FIFO Read Pointer bits These bits point to the message buffer to be read. 0000 = Receive Message Buffer 0 0001 = Receive Message Buffer 1 0010 = Receive Message Buffer 2 0011 = Receive Message Buffer 3 0100 = Receive Message Buffer 4 0101 = Receive Message Buffer 5 0110 = Receive Message Buffer 6 0111 = Receive Message Buffer 7 1000:1111 Reserved Note 1: This bit will clear when all transmissions are aborted. DS39977C-page 398 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-2: Mode 0 CANSTAT: CAN STATUS REGISTER R-0 -- R-0 ICODE2 R-0 ICODE1 R-0 EICODE2 R-0 ICODE0 R-0 EICODE1 U-0 -- R-0 EICODE0 bit 0 R-1 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) Mode 1,2 R-1 R-0 R-0 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-5 bit 4 bit 3-1,4-0 OPMODE<2:0>: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode Mode 0: Unimplemented: Read as `0' Mode 0: ICODE<2:0>: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE<3:1> to WIN<3:0> (Mode 0) or EICODE<4:0> to EWIN<4:0> (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area. See Example 27-2 for a code example. To simplify the description, the following table lists all five bits. No interrupt CAN bus error interrupt TXB2 interrupt TXB1 interrupt TXB0 interrupt RXB1 interrupt RXB0 interrupt Wake-up interrupt RXB0 interrupt RXB1 interrupt RX/TX B0 interrupt RX/TX B1 interrupt RX/TX B2 interrupt RX/TX B3 interrupt RX/TX B4 interrupt RX/TX B5 interrupt bit 0 bit 4-0 Mode 0 00000 00010 00100 00110 01000 01010 01100 00010 --------------------------------- Mode 1 00000 00010 00100 00110 01000 10001 10000 01110 10000 10001 10010 10011 10100 10101 10110 10111 Mode 2 00000 00010 00100 00110 01000 ----10000 01110 10000 10000 10010(2) 10011(2) 10100(2) 10101(2) 10110(2) 10111(2) Mode 0: Unimplemented: Read as `0' Mode 1, 2: EICODE<4:0>: Interrupt Code bits See ICODE<3:1> above. To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch the CAN module in Disable/Sleep mode before putting the device to Sleep. If the buffer is configured as a receiver, the EICODE bits will contain `10000' upon interrupt. Note 1: 2: 2011 Microchip Technology Inc. Preliminary DS39977C-page 399 PIC18F66K80 FAMILY EXAMPLE 27-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B'10000000' ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing. ConfigWait: MOVF CANSTAT, W ; Read current mode state. ANDLW B'10000000' ; Interested in OPMODE bits only. TSTFSZ WREG ; Is it Configuration mode yet? BRA ConfigWait ; No. Continue to wait... ; Module is in Configuration mode now. ; Modify configuration registers as required. ; Switch back to Normal mode to be able to communicate. EXAMPLE 27-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B'00001110' ADDWF PCL, F ; Perform computed GOTO ; to corresponding interrupt cause BRA NoInterrupt ; 000 = No interrupt BRA ErrorInterrupt ; 001 = Error interrupt BRA TXB2Interrupt ; 010 = TXB2 interrupt BRA TXB1Interrupt ; 011 = TXB1 interrupt BRA TXB0Interrupt ; 100 = TXB0 interrupt BRA RXB1Interrupt ; 101 = RXB1 interrupt BRA RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here ... NoInterrupt ... ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. DS39977C-page 400 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 27-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag ... ; Handle error. RETFIE TXB2Interrupt BCF PIR3, TXB2IF ; Clear the interrupt flag GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF ; Clear the interrupt flag GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF ; Clear the interrupt flag GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF ; Clear the interrupt flag GOTO Accessbuffer RXB0Interrupt BCF PIR3, RXB0IF ; Clear the interrupt flag GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANSTAT.ICODE bits to CANCON.WIN bits MOVF TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW B'11110001' ; Use previously saved CANCON value to ; make sure same value. MOVWF TempCANCON ; Copy masked value back to TempCANCON MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B'00001110' ; Use previously saved CANSTAT value ; to make sure same value. IORWF TempCANCON ; Copy ICODE bits to WIN bits. MOVFF TempCANCON, CANCON ; Copy the result to actual CANCON ; Access current buffer... ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ; Preserve current non WIN bits ANDLW B'11110001' IORWF TempCANCON ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source 2011 Microchip Technology Inc. Preliminary DS39977C-page 401 PIC18F66K80 FAMILY REGISTER 27-3: R/W-0 MDSEL1(1) bit 7 Legend: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 FIFOWM(2) R/W-1 EWIN4 R/W-0 EWIN3 R/W-0 EWIN2 R/W-0 EWIN1 R/W-0 EWIN0 bit 0 MDSEL0(1) R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MDSEL<1:0>: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mode (Mode 2) 11 = Reserved FIFOWM: FIFO High Water Mark bit(2) 1 = Will cause FIFO interrupt when one receive buffer remains 0 = Will cause FIFO interrupt when four receive buffers remain(3) EWIN<4:0>: Enhanced Window Address bits These bits map the group of 16 banked CAN SFRs into Access Bank addresses, 0F60-0F6Dh. The exact group of registers to map is determined by the binary value of these bits. Mode 0: Unimplemented: Read as `0' Mode 1, 2: 00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3 00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON 00010 = Acceptance Filter Masks, Error and Interrupt Control 00011 = Transmit Buffer 0 00100 = Transmit Buffer 1 00101 = Transmit Buffer 2 00110 = Acceptance Filters 6, 7, 8 00111 = Acceptance Filters 9, 10, 11 01000 = Acceptance Filters 12, 13, 14 01001 = Acceptance Filter 15 01010-01110 = Reserved 01111 = RXINT0, RXINT1 10000 = Receive Buffer 0 10001 = Receive Buffer 1 10010 = TX/RX Buffer 0 10011 = TX/RX Buffer 1 10100 = TX/RX Buffer 2 10101 = TX/RX Buffer 3 10110 = TX/RX Buffer 4 10111 = TX/RX Buffer 5 11000-11111 = Reserved bit 5 bit 4-0 Note 1: 2: 3: These bits can only be changed in Configuration mode. See Register 27-1 to change to Configuration mode. This bit is used in Mode 2 only. If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger. DS39977C-page 402 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-4: Mode 0 COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 RXB1OVFL R/C-0 RXBnOVFL R/C-0 R-0 TXBO R-0 TXB0 R-0 TXBO R-0 TXBP R-0 TXBP R-0 TXBP R-0 RXBP R-0 RXBP R-0 RXBP R-0 TXWARN R-0 TXWARN R-0 TXWARN R-0 RXWARN R-0 RXWARN R-0 RXWARN R-0 EWARN R-0 EWARN R-0 EWARN bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 RXB0OVFL R/C-0 -- R/C-0 bit 7 Mode 1 Mode 2 FIFOEMPTY RXBnOVFL Legend: R = Readable bit -n = Value at POR bit 7 Mode 0: RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 has overflowed 0 = Receive Buffer 0 has not overflowed Mode 1: Unimplemented: Read as `0' Mode 2: FIFOEMPTY: FIFO Not Empty bit 1 = Receive FIFO is not empty 0 = Receive FIFO is empty Mode 0: RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 has overflowed 0 = Receive Buffer 1 has not overflowed Mode 1, 2: RXBnOVFL: Receive Buffer n Overflow bit 1 = Receive Buffer n has overflowed 0 = Receive Buffer n has not overflowed TXBO: Transmitter Bus-Off bit 1 = Transmit error counter > 255 0 = Transmit error counter 255 TXBP: Transmitter Bus Passive bit 1 = Transmit error counter > 127 0 = Transmit error counter 127 RXBP: Receiver Bus Passive bit 1 = Receive error counter > 127 0 = Receive error counter 127 TXWARN: Transmitter Warning bit 1 = Transmit error counter > 95 0 = Transmit error counter 95 RXWARN: Receiver Warning bit 1 = 127 Receive error counter > 95 0 = Receive error counter 95 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits. 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 403 PIC18F66K80 FAMILY 27.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers. REGISTER 27-5: Mode 0 TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 n 2] R-0 TXABT(1) R-0 TXABT(1) R-0 TXLARB(1) R-0 TXLARB(1) R-0 R/W-0 U-0 -- U-0 -- R/W-0 TXPRI1(3) R/W-0 TXPRI1(3) R/W-0 TXPRI0(3) R/W-0 TXPRI0(3) bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TXERR(1) TXREQ(2) R-0 R/W-0 U-0 TXBIF R/C-0 TXBIF bit 7 Mode 1,2 TXERR(1) TXREQ(2) Legend: R = Readable bit -n = Value at POR bit 7 TXBIF: Transmit Buffer Interrupt Flag bit 1 = Transmit buffer has completed transmission of a message and may be reloaded 0 = Transmit buffer has not completed transmission of a message TXABT: Transmission Aborted Status bit(1) 1 = Message was aborted 0 = Message was not aborted TXLARB: Transmission Lost Arbitration Status bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERR: Transmission Error Detected Status bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQ: Transmit Request Status bit(2) 1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits 0 = Automatically cleared when the message is successfully sent Unimplemented: Read as `0' TXPRI<1:0>: Transmit Priority bits(3) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: This bit is automatically cleared when TXREQ is set. While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is set will request a message abort. These bits define the order in which transmit buffers will be transferred. They do not alter the CAN message identifier. DS39977C-page 404 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-6: R/W-x SID10 bit 7 Legend: TXBnSIDH: TRANSMIT BUFFER `n' STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 n 2] R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). REGISTER 27-7: R/W-x SID2 bit 7 Legend: TXBnSIDL: TRANSMIT BUFFER `n' STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 n 2] R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 R/W-x EID16 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<2:0>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits, EID<20:18> (if EXIDE = 1). Unimplemented: Read as `0' EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended ID, SID<10:0> become EID<28:18> 0 = Message will transmit standard ID, EID<17:0> are ignored Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits bit 2 bit 1-0 REGISTER 27-8: R/W-x EID15 bit 7 Legend: TXBnEIDH: TRANSMIT BUFFER `n' EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 2] R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:8>: Extended Identifier bits (not used when transmitting standard identifier message) 2011 Microchip Technology Inc. Preliminary DS39977C-page 405 PIC18F66K80 FAMILY REGISTER 27-9: R/W-x EID7 bit 7 Legend: TXBnEIDL: TRANSMIT BUFFER `n' EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 n 2] R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<7:0>: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER 27-10: TXBnDm: TRANSMIT BUFFER `n' DATA FIELD BYTE `m' REGISTERS [0 n 2, 0 m 7] R/W-x TXBnDm7 bit 7 Legend: R/W-x TXBnDm6 R/W-x TXBnDm5 R/W-x TXBnDm4 R/W-x TXBnDm3 R/W-x TXBnDm2 R/W-x TXBnDm1 R/W-x TXBnDm0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TXBnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. DS39977C-page 406 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-11: TXBnDLC: TRANSMIT BUFFER `n' DATA LENGTH CODE REGISTERS [0 n 2] U-0 -- bit 7 Legend: R/W-x TXRTR U-0 -- U-0 -- R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have the TXRTR bit set 0 = Transmitted message will have the TXRTR bit cleared Unimplemented: Read as `0' DLC<3:0>: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes bit 5-4 bit 3-0 REGISTER 27-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER R-0 TEC7 bit 7 Legend: R-0 TEC6 R-0 TEC5 R-0 TEC4 R-0 TEC3 R-0 TEC2 R-0 TEC1 R-0 TEC0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TEC<7:0>: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. 2011 Microchip Technology Inc. Preliminary DS39977C-page 407 PIC18F66K80 FAMILY EXAMPLE 27-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access. ; Now load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF TXB0D0 ; Compiler will automatically set "BANKED" bit ; Load rest of data bytes - up to 8 bytes into TXB0 buffer. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF TXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF TXB0SIDH ; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B'00001000' ; Normal priority; Request transmission MOVWF TXB0CON ; If required, wait for message to get transmitted BTFSC TXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. DS39977C-page 408 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 27-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits. ANDLW B'11110000' ; Clear WIN bits. IORLW B'00001000' ; Select Transmit Buffer 0 MOVWF CANCON ; Apply the changes. ; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually ; yield TXB0 register values. ; Load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF RXB0D0 ; Access TXB0D0 via RXB0D0 address. ; Load rest of the data bytes - up to 8 bytes into "TXB0" buffer using RXB0 registers. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF RXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF RXB0SIDH ; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B'00001000' ; Normal priority; Request transmission MOVWF RXB0CON ; If required, wait for message to get transmitted BTFSC RXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. ; If required, reset the WIN bits to default state. 2011 Microchip Technology Inc. Preliminary DS39977C-page 409 PIC18F66K80 FAMILY 27.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers. REGISTER 27-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER Mode 0 R/C-0 RXFUL(1) R/C-0 RXFUL(1) bit 7 R/W-0 RXM1 R/W-0 RXM1 R/W-0 RXM0 R-0 RTRRO U-0 -- R-0 FILHITF4 R-0 R/W-0 RXRTRRO RXB0DBEN R-0 FILHIT3 R-0 FILHIT2 R-0 JTOFF(2) R-0 FILHIT1 R-0 FILHIT0 R-0 FILHIT0 bit 0 Mode 1,2 Legend: R = Readable bit -n = Value at POR C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7 bit 6,6-5 bit 5 bit 4 bit 3 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Mode 0: RXM<1:0>: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be `1' 01 = Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be `0' 00 = Receive all valid messages as per the EXIDEN bit in the RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters Mode 0: RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0>bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 0: Unimplemented: Read as `0' Mode 1, 2: FILHIT<4:0>: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits<4:0>. Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT<4:0>: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits<4:0>. Note 1: 2: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. After clearing the RXFUL flag, the PIR5 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. This bit allows the same filter jump table for both RXB0CON and RXB1CON. DS39977C-page 410 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits<4:0>. Mode 0: JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)(2) 1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 1 This bit combines with other bits to form filter acceptance bits<4:0>. Mode 0: FILHIT0: Filter Hit bit 0 This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0. 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Mode 1, 2: FILHIT<4:0>: Filter Hit bit 0 This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. After clearing the RXFUL flag, the PIR5 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. This bit allows the same filter jump table for both RXB0CON and RXB1CON. bit 1 bit 0 Note 1: 2: 2011 Microchip Technology Inc. Preliminary DS39977C-page 411 PIC18F66K80 FAMILY REGISTER 27-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER Mode 0 R/C-0 RXFUL(1) R/C-0 RXFUL(1) bit 7 R/W-0 RXM1 R/W-0 RXM1 R/W-0 RXM0 R-0 RTRRO U-0 -- R-0 FILHIT4 R-0 RXRTRRO R-0 FILHIT3 R/W-0 FILHIT2 R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT1 R-0 FILHIT0 R-0 FILHIT0 bit 0 Mode 1,2 Legend: C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 bit 6-5, 6 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Mode 0: RXM<1:0>: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be `1' 01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be `0' 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM<1:0>: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 0: FILHIT24: Filter Hit bit 4 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 4 This bit combines with other bits to form the filter acceptance bits<4:0>. Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT<4:0>: Filter Hit bit 3 This bit combines with other bits to form the filter acceptance bits<4:0>. This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. bit 4 bit 3 Note 1: DS39977C-page 412 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Mode 0: FILHIT<2:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set Mode 1, 2: FILHIT<4:0>: Filter Hit bits<2:0> These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. Note 1: REGISTER 27-15: RXBnSIDH: RECEIVE BUFFER `n' STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 n 1] R-x SID10 bit 7 Legend: R-x SID9 R-x SID8 R-x SID7 R-x SID6 R-x SID5 R-x SID4 R-x SID3 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXID (RXBnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXID = 1). 2011 Microchip Technology Inc. Preliminary DS39977C-page 413 PIC18F66K80 FAMILY REGISTER 27-16: RXBnSIDL: RECEIVE BUFFER `n' STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 n 1] R-x SID2 bit 7 Legend: R-x SID1 R-x SID0 R-x SRR R-x EXID U-0 -- R-x EID17 R-x EID16 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1). SRR: Substitute Remote Request bit EXID: Extended Identifier bit 1 = Received message is an extended data frame, SID<10:0> are EID<28:18> 0 = Received message is a standard data frame Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits bit 2 bit 1-0 REGISTER 27-17: RXBnEIDH: RECEIVE BUFFER `n' EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 1] R-x EID15 bit 7 Legend: R-x EID14 R-x EID13 R-x EID12 R-x EID11 R-x EID10 R-x EID9 R-x EID8 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:8>: Extended Identifier bits REGISTER 27-18: RXBnEIDL: RECEIVE BUFFER `n' EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 n 1] R-x EID7 bit 7 Legend: R-x EID6 R-x EID5 R-x EID4 R-x EID3 R-x EID2 R-x EID1 R-x EID0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<7:0>: Extended Identifier bits DS39977C-page 414 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-19: RXBnDLC: RECEIVE BUFFER `n' DATA LENGTH CODE REGISTERS [0 n 1] U-0 -- bit 7 Legend: R-x RXRTR R-x RB1 R-x R0 R-x DLC3 R-x DLC2 R-x DLC1 R-x DLC0 bit 0 R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request RB1: Reserved bit 1 Reserved by CAN Spec and read as `0'. RB0: Reserved bit 0 Reserved by CAN Spec and read as `0'. DLC<3:0>: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 byte 0000 = Data length = 0 bytes bit 5 bit 4 bit 3-0 REGISTER 27-20: RXBnDm: RECEIVE BUFFER `n' DATA FIELD BYTE `m' REGISTERS [0 n 1, 0 m 7] R-x RXBnDm7 bit 7 Legend: R-x RXBnDm6 R-x RXBnDm5 R-x RXBnDm4 R-x RXBnDm3 R-x RXBnDm2 R-x RXBnDm1 R-x RXBnDm0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RXBnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7. 2011 Microchip Technology Inc. Preliminary DS39977C-page 415 PIC18F66K80 FAMILY REGISTER 27-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 REC7 bit 7 Legend: R-0 REC6 R-0 REC5 R-0 REC4 R-0 REC3 R-0 REC2 R-0 REC1 R-0 REC0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REC<7:0>: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error-passive state. RXERRCNT does not have the ability to put the module in "bus-off" state. EXAMPLE 27-5: READING A CAN MESSAGE ; Need to read a pending message from RXB0 buffer. ; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be ; programmed correctly. ; ; Make sure that there is a message pending in RXB0. BTFSS RXB0CON, RXFUL ; Does RXB0 contain a message? BRA NoMessage ; No. Handle this situation... ; We have verified that a message is pending in RXB0 buffer. ; If this buffer can receive both Standard or Extended Identifier messages, ; identify type of message received. BTFSS RXB0SIDL, EXID ; Is this Extended Identifier? BRA StandardMessage ; No. This is Standard Identifier message. ; Yes. This is Extended Identifier message. ; Read all 29-bits of Extended Identifier message. ... ; Now read all data bytes MOVFF RXB0DO, MY_DATA_BYTE1 ... ; Once entire message is read, mark the RXB0 that it is read and no longer FULL. BCF RXB0CON, RXFUL ; This will allow CAN Module to load new messages ; into this buffer. ... DS39977C-page 416 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0. REGISTER 27-22: BnCON: TX/RX BUFFER `n' CONTROL REGISTERS IN RECEIVE MODE [0 n 5, TXnEN (BSEL0 R/W-0 RXFUL(2) bit 7 Legend: R/W-0 RXM1 R-0 RXRTRRO R-0 FILHIT4 R-0 FILHIT3 R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RXFUL: Receive Full Status bit(2) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message RXM1: Receive Buffer Mode bit 1 = Receive all messages including partial and invalid (acceptance filters are ignored) 0 = Receive all valid messages as per acceptance filters RXRTRRO: Read-Only Remote Transmission Request for Received Message bit 1 = Received message is a remote transmission request 0 = Received message is not a remote transmission request FILHIT<4:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into this buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00001 = Acceptance Filter 1 (RXF1) 00000 = Acceptance Filter 0 (RXF0) bit 6 bit 5 bit 4-0 Note 1: 2: These registers are available in Mode 1 and 2 only. This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. 2011 Microchip Technology Inc. Preliminary DS39977C-page 417 PIC18F66K80 FAMILY REGISTER 27-23: BnCON: TX/RX BUFFER `n' CONTROL REGISTERS IN TRANSMIT MODE [0 n 5, TXnEN (BSEL0 R/W-0 TXBIF(3) bit 7 Legend: R-0 TXABT(3) R-0 TXLARB(3) R-0 TXERR(3) R/W-0 TXREQ(2,4) R/W-0 RTREN R/W-0 TXPRI1(5) R/W-0 TXPRI0(5) bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message was successfully transmitted 0 = No message was transmitted TXABT: Transmission Aborted Status bit(3) 1 = Message was aborted 0 = Message was not aborted TXLARB: Transmission Lost Arbitration Status bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERR: Transmission Error Detected Status bit(3) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQ: Transmit Request Status bit(2,4) 1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits 0 = Automatically cleared when the message is successfully sent RTREN: Automatic Remote Transmission Request Enable bit 1 = When a remote transmission request is received, TXREQ will be automatically set 0 = When a remote transmission request is received, TXREQ will be unaffected TXPRI<1:0>: Transmit Priority bits(5) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: 4: 5: These registers are available in Mode 1 and 2 only. Clearing this bit in software while the bit is set will request a message abort. This bit is automatically cleared when TXREQ is set. While TXREQ is set or a transmission is in progress, Transmit Buffer registers remain read-only. These bits set the order in which the Transmit Buffer register will be transferred. They do not alter the CAN message identifier. DS39977C-page 418 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-24: BnSIDH: TX/RX BUFFER `n' STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0 R-x SID10 bit 7 Legend: R-x SID9 R-x SID8 R-x SID7 R-x SID6 R-x SID5 R-x SID4 R-x SID3 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-25: BnSIDH: TX/RX BUFFER `n' STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 n 5, TXnEN (BSEL0 R/W-x SID10 bit 7 Legend: R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). Note 1: These registers are available in Mode 1 and 2 only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 419 PIC18F66K80 FAMILY REGISTER 27-26: BnSIDL: TX/RX BUFFER `n' STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0 R-x SID2 bit 7 Legend: R-x SID1 R-x SID0 R-x SRR R-x EXIDE U-0 -- R-x EID17 R-x EID16 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1). SRR: Substitute Remote Transmission Request bit This bit is always `1' when EXID = 1 or equal to the value of RXRTRRO (BnCON<5>) when EXID = 0. EXIDE: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID<10:0> are EID<28:18>) 0 = Received message is a standard identifier frame Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits bit 2 bit 1-0 Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-27: BnSIDL: TX/RX BUFFER `n' STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0 R/W-x SID2 bit 7 Legend: R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 R/W-x EID16 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<2:0>: Standard Identifier bits (if EXIDE = 0) Extended Identifier bits, EID<20:18> (if EXIDE = 1). Unimplemented: Read as `0' EXIDE: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID<10:0> are EID<28:18>) 0 = Received message is a standard identifier frame Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits bit 2 bit 1-0 Note 1: These registers are available in Mode 1 and 2 only. DS39977C-page 420 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-28: BnEIDH: TX/RX BUFFER `n' EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0 R-x EID15 bit 7 Legend: R-x EID14 R-x EID13 R-x EID12 R-x EID11 R-x EID10 R-x EID9 R-x EID8 bit 0 R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:8>: Extended Identifier bits These registers are available in Mode 1 and 2 only. REGISTER 27-29: BnEIDH: TX/RX BUFFER `n' EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 n 5, TXnEN (BSEL0 R/W-x EID15 bit 7 Legend: R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:8>: Extended Identifier bits These registers are available in Mode 1 and 2 only. REGISTER 27-30: BnEIDL: TX/RX BUFFER `n' EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL R-x EID7 bit 7 Legend: R-x EID6 R-x EID5 R-x EID4 R-x EID3 R-x EID2 R-x EID1 R-x EID0 bit 0 R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<7:0>: Extended Identifier bits These registers are available in Mode 1 and 2 only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 421 PIC18F66K80 FAMILY REGISTER 27-31: BnEIDL: TX/RX BUFFER `n' EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL R/W-x EID7 bit 7 Legend: R/W-x EID6 R/W-x EID5 R/W-x FEID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<7:0>: Extended Identifier bits These registers are available in Mode 1 and 2 only. REGISTER 27-32: BnDm: TX/RX BUFFER `n' DATA FIELD BYTE `m' REGISTERS IN RECEIVE MODE [0 n 5, 0 m 7, TXnEN (BSEL R-x BnDm7 bit 7 Legend: R-x BnDm6 R-x BnDm5 R-x BnDm4 R-x BnDm3 R-x BnDm2 R-x BnDm1 R-x BnDm0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to B0D7. Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-33: BnDm: TX/RX BUFFER `n' DATA FIELD BYTE `m' REGISTERS IN TRANSMIT MODE [0 n 5, 0 m 7, TXnEN (BSEL R/W-x BnDm7 bit 7 Legend: R/W-x BnDm6 R/W-x BnDm5 R/W-x BnDm4 R/W-x BnDm3 R/W-x BnDm2 R/W-x BnDm1 R/W-x BnDm0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. Note 1: These registers are available in Mode 1 and 2 only. DS39977C-page 422 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-34: BnDLC: TX/RX BUFFER `n' DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0 n 5, TXnEN (BSEL U-0 -- bit 7 Legend: R-x RXRTR R-x RB1 R-x RB0 R-x DLC3 R-x DLC2 R-x DLC1 R-x DLC0 bit 0 R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request 0 = This is not a remote transmission request RB1: Reserved bit 1 Reserved by CAN Spec and read as `0'. RB0: Reserved bit 0 Reserved by CAN Spec and read as `0'. DLC<3:0>: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 byte 0000 = Data length = 0 bytes bit 5 bit 4 bit 3-0 Note 1: These registers are available in Mode 1 and 2 only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 423 PIC18F66K80 FAMILY REGISTER 27-35: BnDLC: TX/RX BUFFER `n' DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0 n 5, TXnEN (BSEL U-0 -- bit 7 Legend: R/W-x TXRTR U-0 -- U-0 -- R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will have the RTR bit set 0 = Transmitted message will have the RTR bit cleared Unimplemented: Read as `0' DLC<3:0>: Data Length Code bits 1111-1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 byte 0000 = Data length = 0 bytes bit 5-4 bit 3-0 Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-36: BSEL0: BUFFER SELECT REGISTER 0(1) R/W-0 B5TXEN bit 7 Legend: R/W-0 B4TXEN R/W-0 B3TXEN R/W-0 B2TXEN R/W-0 B1TXEN R/W-0 B0TXEN U-0 -- U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7-2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown B<5:0>TXEN: Buffer 5 to Buffer 0 Transmit Enable bits 1 = Buffer is configured in Transmit mode 0 = Buffer is configured in Receive mode Unimplemented: Read as `0' bit 1-0 Note 1: These registers are available in Mode 1 and 2 only. DS39977C-page 424 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers. REGISTER 27-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER `n' STANDARD IDENTIFIER FILTER REGISTERS, HIGH BYTE [0 n 15](1) R/W-x SID10 bit 7 Legend: R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<10:3>: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits, EID<28:21> (if EXIDEN = 1). Note 1: Registers, RXF6SIDH:RXF15SIDH, are available in Mode 1 and 2 only. REGISTER 27-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER `n' STANDARD IDENTIFIER FILTER REGISTERS, LOW BYTE [0 n 15](1) R/W-x SID2 bit 7 Legend: R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDEN(2) U-0 -- R/W-x EID17 R/W-x EID16 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<2:0>: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits, EID<20:18> (if EXIDEN = 1). Unimplemented: Read as `0' EXIDEN: Extended Identifier Filter Enable bit(2) 1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages Unimplemented: Read as `0' EID<17:16>: Extended Identifier Filter bits bit 2 bit 1-0 Note 1: 2: Registers, RXF6SIDL:RXF15SIDL, are available in Mode 1 and 2 only. In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value. 2011 Microchip Technology Inc. Preliminary DS39977C-page 425 PIC18F66K80 FAMILY REGISTER 27-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER `n' EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 15](1) R/W-x EID15 bit 7 Legend: R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:8>: Extended Identifier Filter bits Registers, RXF6EIDH:RXF15EIDH, are available in Mode 1 and 2 only. REGISTER 27-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER `n' EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 n 15](1) R/W-x EID7 bit 7 Legend: R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<7:0>: Extended Identifier Filter bits Registers, RXF6EIDL:RXF15EIDL, are available in Mode 1 and 2 only. REGISTER 27-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK `n' STANDARD IDENTIFIER MASK REGISTERS, HIGH BYTE [0 n 1] R/W-x SID10 bit 7 Legend: R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<10:3>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<28:21>) DS39977C-page 426 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK `n' STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0 n 1] R/W-x SID2 bit 7 Legend: R/W-x SID1 R/W-x SID0 U-0 -- R/W-0 EXIDEN(1) U-0 -- R/W-x EID17 R/W-x EID16 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>) Unimplemented: Read as `0' Mode 0: Unimplemented: Read as `0' Mode 1, 2: EXIDEN: Extended Identifier Filter Enable Mask bit(1) 1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted 0 = Both standard and extended identifier messages will be accepted Unimplemented: Read as `0' EID<17:16>: Extended Identifier Mask bits bit 2 bit 1-0 Note 1: This bit is available in Mode 1 and 2 only. REGISTER 27-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK `n' EXTENDED IDENTIFIER MASK REGISTERS, HIGH BYTE [0 n 1] R/W-x EID15 bit 7 Legend: R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:8>: Extended Identifier Mask bits REGISTER 27-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK `n' EXTENDED IDENTIFIER MASK REGISTERS, LOW BYTE [0 n 1] R/W-x EID7 bit 7 Legend: R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<7:0>: Extended Identifier Mask bits 2011 Microchip Technology Inc. Preliminary DS39977C-page 427 PIC18F66K80 FAMILY REGISTER 27-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER `n' [0 n 1](1) RXFCON0 R/W-0 RXF7EN R/W-0 RXF15EN bit 7 R/W-0 RXF6EN R/W-0 RXF14EN R/W-0 RXF5EN R/W-0 RXF13EN R/W-0 RXF4EN R/W-0 RXF3EN R/W-0 RXF2EN R/W-0 RXF10EN R/W-0 RXF1EN R/W-0 RXF9EN R/W-0 RXF0EN R/W-0 RXF8EN bit 0 RXFCON1 R/W-0 R/W-0 RXF12EN RXF11EN Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-0 RXF<7:0>EN: Receive Filter n Enable bits 0 = Filter is disabled 1 = Filter is enabled Note 1: This register is available in Mode 1 and 2 only. Note: Register 27-46 through Register 27-51 are writable in Configuration mode only. REGISTER 27-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1) U-0 -- bit 7 Legend: U-0 -- U-0 -- R/W-0 FLC4 R/W-0 FLC3 R/W-0 FLC2 R/W-0 FLC1 R/W-0 FLC0 bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' FLC<4:0>: Filter Length Count bits Mode 0: Not used; forced to `00000'. 00000-10010 = 0 18 bits are available for standard data byte filter. Actual number of bits used depends on the DLC<3:0> bits (RXBnDLC<3:0> or BnDLC<3:0> if configured as RX buffer) of the message being received. If DLC<3:0> = 0000 No bits will be compared with incoming data bits. If DLC<3:0> = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC<2:0>, will be compared with the corresponding number of data bits of the incoming message. If DLC<3:0> = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC<3:0>, will be compared with the corresponding number of data bits of the incoming message. If DLC<3:0> = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC<4:0>, will be compared with the corresponding number of data bits of the incoming message. Note 1: This register is available in Mode 1 and 2 only. DS39977C-page 428 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER `n'(1) RXFBCON0 R/W-0 F1BP_3 R/W-0 F3BP_3 R/W-0 F5BP_3 R/W-0 F7BP_3 R/W-0 F9BP_3 R/W-0 F11BP_3 R/W-0 F13BP_3 R/W-0 F15BP_3 bit 7 R/W-0 F1BP_2 R/W-0 F3BP_2 R/W-0 F5BP_2 R/W-0 F7BP_2 R/W-0 F9BP_2 R/W-0 F11BP_2 R/W-0 F13BP_2 R/W-0 F15BP_2 R/W-0 F1BP_1 R/W-0 F3BP_1 R/W-0 F5BP_1 R/W-0 F7BP_1 R/W-0 F9BP_1 R/W-0 F11BP_1 R/W-0 F13BP_1 R/W-0 F15BP_1 R/W-0 F1BP_0 R/W-1 F3BP_0 R/W-1 F5BP_0 R/W-0 F7BP_0 R/W-0 F9BP_0 R/W-0 F11BP_0 R/W-0 F13BP_0 R/W-0 F15BP_0 R/W-0 F0BP_3 R/W-0 F2BP_3 R/W-0 F4BP_3 R/W-0 F6BP_3 R/W-0 F8BP_3 R/W-0 F10BP_3 R/W-0 F12BP_3 R/W-0 F14BP_3 R/W-0 F0BP_2 R/W-0 F2BP_2 R/W-0 F4BP_2 R/W-0 F6BP_2 R/W-0 F8BP_2 R/W-0 F10BP_2 R/W-0 F12BP_2 R/W-0 F14BP_2 R/W-0 F0BP_1 R/W-0 F2BP_1 R/W-0 F4BP_1 R/W-0 F6BP_1 R/W-0 F8BP_1 R/W-0 F10BP_1 R/W-0 F12BP_1 R/W-0 F14BP_1 R/W-0 F0BP_0 R/W-1 F2BP_0 R/W-1 F4BP_0 R/W-0 F6BP_0 R/W-0 F8BP_0 R/W-0 F10BP_0 R/W-0 F12BP_0 R/W-0 F14BP_0 bit 0 RXFBCON1 RXFBCON2 RXFBCON3 RXFBCON4 RXFBCON5 RXFBCON6 RXFBCON7 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-0 F<15:2>BP_<3:0>: Filter n Buffer Pointer Nibble bits 0000 = Filter n is associated with RXB0 0001 = Filter n is associated with RXB1 0010 = Filter n is associated with B0 0011 = Filter n is associated with B1 ... 0111 = Filter n is associated with B5 1111-1000 = Reserved Note 1: This register is available in Mode 1 and 2 only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 429 PIC18F66K80 FAMILY REGISTER 27-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 FIL3_1 bit 7 Legend: R/W-1 FIL3_0 R/W-0 FIL2_1 R/W-1 FIL2_0 R/W-0 FIL1_1 R/W-0 FIL1_0 R/W-0 FIL0_1 R/W-0 FIL0_0 bit 0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FIL3_<1:0>: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL2_<1:0>: Filter 2 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL1_<1:0>: Filter 1 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL0_<1:0>: Filter 0 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 bit 3-2 bit 1-0 Note 1: This register is available in Mode 1 and 2 only. DS39977C-page 430 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 FIL7_1 bit 7 Legend: R/W-0 FIL7_0 R/W-0 FIL6_1 R/W-0 FIL6_0 R/W-0 FIL5_1 R/W-1 FIL5_0 R/W-0 FIL4_1 R/W-1 FIL4_0 bit 0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FIL7_<1:0>: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL6_<1:0>: Filter 6 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL5_<1:0>: Filter 5 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL4_<1:0>: Filter 4 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 bit 3-2 bit 1-0 Note 1: This register is available in Mode 1 and 2 only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 431 PIC18F66K80 FAMILY REGISTER 27-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 FIL11_1 bit 7 Legend: R/W-0 FIL11_0 R/W-0 FIL10_1 R/W-0 FIL10_0 R/W-0 FIL9_1 R/W-0 FIL9_0 R/W-0 FIL8_1 R/W-0 FIL8_0 bit 0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FIL11_<1:0>: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL10_<1:0>: Filter 10 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL9_<1:0>: Filter 9 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL8_<1:0>: Filter 8 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 bit 3-2 bit 1-0 Note 1: This register is available in Mode 1 and 2 only. DS39977C-page 432 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 FIL15_1 bit 7 Legend: R/W-0 FIL15_0 R/W-0 FIL14_1 R/W-0 FIL14_0 R/W-0 FIL13_1 R/W-0 FIL13_0 R/W-0 FIL12_1 R/W-0 FIL12_0 bit 0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FIL15_<1:0>: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL14_<1:0>: Filter 14 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL13_<1:0>: Filter 13 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 FIL12_<1:0>: Filter 12 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 bit 3-2 bit 1-0 Note 1: This register is available in Mode 1 and 2 only. 2011 Microchip Technology Inc. Preliminary DS39977C-page 433 PIC18F66K80 FAMILY 27.2.4 Note: CAN BAUD RATE REGISTERS These registers are Configuration mode only. writable in This section describes the CAN Baud Rate registers. REGISTER 27-52: BRGCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 SJW1 bit 7 Legend: R/W-0 SJW0 R/W-0 BRP5 R/W-0 BRP4 R/W-0 BRP3 R/W-0 BRP2 R/W-0 BRP1 R/W-0 BRP0 bit 0 R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SJW<1:0>: Synchronized Jump Width bits 11 = Synchronization jump width time = 4 x TQ 10 = Synchronization jump width time = 3 x TQ 01 = Synchronization jump width time = 2 x TQ 00 = Synchronization jump width time = 1 x TQ BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC bit 5-0 DS39977C-page 434 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 SEG2PHTS bit 7 Legend: R/W-0 SAM R/W-0 SEG1PH2 R/W-0 SEG1PH1 R/W-0 SEG1PH0 R/W-0 PRSEG2 R/W-0 PRSEG1 R/W-0 PRSEG0 bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point SEG1PH<2:0>: Phase Segment 1 bits 111 = Phase Segment 1 time = 8 x TQ 110 = Phase Segment 1 time = 7 x TQ 101 = Phase Segment 1 time = 6 x TQ 100 = Phase Segment 1 time = 5 x TQ 011 = Phase Segment 1 time = 4 x TQ 010 = Phase Segment 1 time = 3 x TQ 001 = Phase Segment 1 time = 2 x TQ 000 = Phase Segment 1 time = 1 x TQ PRSEG<2:0>: Propagation Time Select bits 111 = Propagation time = 8 x TQ 110 = Propagation time = 7 x TQ 101 = Propagation time = 6 x TQ 100 = Propagation time = 5 x TQ 011 = Propagation time = 4 x TQ 010 = Propagation time = 3 x TQ 001 = Propagation time = 2 x TQ 000 = Propagation time = 1 x TQ bit 6 bit 5-3 bit 2-0 2011 Microchip Technology Inc. Preliminary DS39977C-page 435 PIC18F66K80 FAMILY REGISTER 27-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 WAKDIS bit 7 Legend: R/W-0 WAKFIL U-0 -- U-0 -- U-0 -- R/W-0 SEG2PH2(1) R/W-0 R/W-0 bit 0 SEG2PH1(1) SEG2PH0(1) R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up Unimplemented: Read as `0' SEG2PH<2:0>: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 time = 8 x TQ 110 = Phase Segment 2 time = 7 x TQ 101 = Phase Segment 2 time = 6 x TQ 100 = Phase Segment 2 time = 5 x TQ 011 = Phase Segment 2 time = 4 x TQ 010 = Phase Segment 2 time = 3 x TQ 001 = Phase Segment 2 time = 2 x TQ 000 = Phase Segment 2 time = 1 x TQ bit 6 bit 5-3 bit 2-0 Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is `0'. DS39977C-page 436 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module's I/O pins in relation to the rest of the microcontroller. REGISTER 27-55: CIOCON: CAN I/O CONTROL REGISTER R/W-0 TX2SRC bit 7 Legend: R/W-0 TX2EN R/W-0 ENDRHI(1) R/W-0 CANCAP U-0 -- U-0 -- U-0 -- R/W-0 CLKSEL bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TX2SRC: CANTX2 Pin Data Source bit 1 = CANTX2 pin will output the CAN clock 0 = CANTX2 pin will output CANTX TX2EN: CANTX Pin Enable bit 1 = CANTX2 pin will output CANTX or CAN clock as selected by the TX2SRC bit 0 = CANTX2 pin will have digital I/O function ENDRHI: Enable Drive High bit(1) 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will be tri-state when recessive CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture; CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture; RC2/CCP1 input to CCP1 module Unimplemented: Read as `0' CLKSEL: CAN Clock Source Selection bit 1 = Use the oscillator as the source of the CAN system clock 0 = Use the PLL as the source of the CAN system clock bit 6 bit 5 bit 4 bit 3-1 bit 0 Note 1: Always set this bit when using a differential bus to avoid signal crosstalk in CANTX from other nearby pins. 2011 Microchip Technology Inc. Preliminary DS39977C-page 437 PIC18F66K80 FAMILY 27.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 10.0 "Interrupts". They are duplicated here for convenience. REGISTER 27-56: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 Mode 0 R/W-x IRXIF R/W-x IRXIF bit 7 R/W-x WAKIF R/W-x WAKIF R/W-x ERRIF R/W-x ERRIF R/W-x TXB2IF R/W-x TXBnIF R/W-x TXB1IF(1) R/W-x TXB1IF(1) R/W-x TXB0IF(1) R/W-x TXB0IF(1) R/W-x RXB1IF R/W-x RXBnIF R/W-x RXB0IF R/W-x FIFOWMIF bit 0 Mode 1,2 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IRXIF: CAN Bus Error Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on the CAN bus WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = No activity on the CAN bus ERRIF: CAN Module Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources; refer to Section 27.15.6 "Error Interrupt") 0 = No CAN module errors When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers have completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Note 1: In CAN Mode 1 and 2, these bits are forced to `0'. DS39977C-page 438 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-57: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 Mode 0 R/W-x IRXIE R/W-x IRXIE bit 7 R/W-x WAKIE R/W-x WAKIE R/W-x ERRIE R/W-x ERRIE R/W-x TXB2IE R/W-x TXBnIE R/W-x TXB1IE(1) R/W-x TXB1IE(1) R/W-x TXB0IE(1) R/W-x TXB0IE(1) R/W-x RXB1IE R/W-x RXBnIE R/W-x RXB0IE R/W-x FIFOWMIE bit 0 Mode 1 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IRXIE: CAN Bus Error Message Received Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN module error interrupt 0 = Disable CAN module error interrupt When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to `0'. 2011 Microchip Technology Inc. Preliminary DS39977C-page 439 PIC18F66K80 FAMILY REGISTER 27-58: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 Mode 0 R/W-x IRXIP R/W-x IRXIP bit 7 R/W-x WAKIP R/W-x WAKIP R/W-x ERRIP R/W-x ERRIP R/W-x TXB2IP R/W-x TXBnIP R/W-x TXB1IP(1) R/W-x TXB1IP(1) R/W-x TXB0IP(1) R/W-x TXB0IP (1) R/W-x RXB1IP R/W-x RXBnIP R/W-x RXB0IP R/W-x FIFOWMIP bit 0 Mode 1,2 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IRXIP: CAN Bus Error Message Received Interrupt Priority bit 1 = High priority 0 = Low priority WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority ERRIP: CAN Module Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 3 bit 2 bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority In CAN Mode 1 and 2, these bits are forced to `0'. bit 0 Note 1: DS39977C-page 440 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 27-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 -- bit 7 Legend: U-0 -- U-0 -- R/W-0 TXB2IE(2) R/W-0 TXB1IE(2) R/W-0 TXB0IE(2) U-0 -- U-0 -- bit 0 R = Readable bit -n = Value at POR bit 7-5 bit 4-2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bits(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt is disabled Unimplemented: Read as `0' bit 1-0 Note 1: 2: This register is available in Mode 1 and 2 only. TXBnIE in PIE5 register must be set to get an interrupt. REGISTER 27-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1) R/W-0 B5IE(2) bit 7 Legend: R/W-0 B4IE(2) R/W-0 B3IE(2) R/W-0 B2IE(2) R/W-0 B1IE(2) R/W-0 B0IE(2) R/W-0 RXB1IE(2) R/W-0 RXB0IE(2) bit 0 R = Readable bit -n = Value at POR bit 7-2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown B<5:0>IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bits(2) 1 = Interrupt is enabled 0 = Interrupt is disabled RXB<1:0>IE: Dedicated Receive Buffer 1-0 Interrupt Enable bits(2) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1-0 Note 1: 2: This register is available in Mode 1 and 2 only. Either TXBnIE or RXBnIE in the PIE5 register must be set to get an interrupt. 2011 Microchip Technology Inc. Preliminary DS39977C-page 441 PIC18F66K80 FAMILY 27.3 CAN Modes of Operation 27.3.2 DISABLE/SLEEP MODE The PIC18F66K80 family has six main modes of operation: * * * * * * Configuration mode Disable/Sleep mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode In Disable/Sleep mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity; however, any pending interrupts will remain and the error counters will retain their value. If the REQOP<2:0> bits are set to `001', the module will enter the module Disable/Sleep mode. This mode is similar to disabling other peripheral modules by turning off the module enables. This causes the module internal clock to stop unless the module is active (i.e., receiving or transmitting a message). If the module is active, the module will wait for 11 recessive bits on the CAN bus, detect that condition as an Idle bus, then accept the module Disable/Sleep command. OPMODE<2:0> = 001 indicates whether the module successfully went into the module Disable/Sleep mode. The WAKIF interrupt is the only module interrupt that is still active in the Disable/Sleep mode. If the WAKDIS is cleared and WAKIE is set, the processor will receive an interrupt whenever the module detects recessive to dominant transition. On wake-up, the module will automatically be set to the previous mode of operation. For example, if the module was switched from Normal to Disable/Sleep mode on bus activity wake-up, the module will automatically enter into Normal mode and the first message that caused the module to wake-up is lost. The module will not generate any error frame. Firmware logic must detect this condition and make sure that retransmission is requested. If the processor receives a wake-up interrupt while it is sleeping, more than one message may get lost. The actual number of messages lost would depend on the processor oscillator start-up time and incoming message bit rate. The TXCAN pin will stay in the recessive state while the module is in Disable/Sleep mode. All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>). Error Recognition mode is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is Acknowledged by monitoring the OPMODE bits. When changing modes, the mode will not actually change until all pending message transmissions are complete. Because of this, the user must verify that the device has actually changed into the requested mode before further operations are executed. 27.3.1 CONFIGURATION MODE The CAN module has to be initialized before the activation. This is only possible if the module is in the Configuration mode. The Configuration mode is requested by setting the REQOP2 bit. Only when the status bit, OPMODE2, has a high level can the initialization be performed. Afterwards, the Configuration registers, the acceptance mask registers and the acceptance filter registers can be written. The module is activated by setting the REQOP control bits to zero. The module will protect the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is online. The CAN module will not be allowed to enter the Configuration mode while a transmission or reception is taking place. The Configuration mode serves as a lock to protect the following registers: * * * * * * * Configuration Registers Functional Mode Selection Registers Bit Timing Registers Identifier Acceptance Filter Registers Identifier Acceptance Mask Registers Filter and Mask Control Registers Mask Selection Registers 27.3.3 NORMAL MODE This is the standard operating mode of the PIC18F66K80 family devices. In this mode, the device actively monitors all bus messages and generates Acknowledge bits, error frames, etc. This is also the only mode in which the PIC18F66K80 family devices will transmit messages over the CAN bus. In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will have access to Configuration registers that are access restricted in other modes. I/O pins will revert to normal I/O functions. DS39977C-page 442 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.3.4 LISTEN ONLY MODE 27.4 CAN Module Functional Modes Listen Only mode provides a means for the PIC18F66K80 family devices to receive all messages, including messages with errors. This mode can be used for bus monitor applications or for detecting the baud rate in `hot plugging' situations. For auto-baud detection, it is necessary that there are at least two other nodes which are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received. The Listen Only mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or Acknowledge signals. The filters and masks can be used to allow only particular messages to be loaded into the receive registers or the filter masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen Only mode is activated by setting the mode request bits in the CANCON register. In addition to CAN modes of operation, the ECAN module offers a total of 3 functional modes. Each of these modes are identified as Mode 0, Mode 1 and Mode 2. 27.4.1 MODE 0 - LEGACY MODE Mode 0 is designed to be fully compatible with CAN modules used in PIC18CXX8 and PIC18FXX8 devices. This is the default mode of operation on all Reset conditions. As a result, module code written for the PIC18XX8 CAN module may be used on the ECAN module without any code changes. The following is the list of resources available in Mode 0: * Three transmit buffers: TXB0, TXB1 and TXB2 * Two receive buffers: RXB0 and RXB1 * Two acceptance masks, one for each receive buffer: RXM0, RXM1 * Six acceptance filters, 2 for RXB0 and 4 for RXB1: RXF0, RXF1, RXF2, RXF3, RXF4, RXF5 27.3.5 LOOPBACK MODE This mode will allow internal transmission of messages from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus. This mode can be used in system development and testing. In this mode, the ACK bit is ignored and the device will allow incoming messages from itself, just as if they were coming from another node. The Loopback mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or Acknowledge signals. The TXCAN pin will revert to port I/O while the device is in this mode. The filters and masks can be used to allow only particular messages to be loaded into the receive registers. The masks can be set to all zeros to provide a mode that accepts all messages. The Loopback mode is activated by setting the mode request bits in the CANCON register. 27.4.2 MODE 1 - ENHANCED LEGACY MODE Mode 1 is similar to Mode 0, with the exception that more resources are available in Mode 1. There are 16 acceptance filters and two acceptance mask registers. Acceptance Filter 15 can be used as either an acceptance filter or an acceptance mask register. In addition to three transmit and two receive buffers, there are six more message buffers. One or more of these additional buffers can be programmed as transmit or receive buffers. These additional buffers can also be programmed to automatically handle RTR messages. Fourteen of sixteen acceptance filter registers can be dynamically associated to any receive buffer and acceptance mask register. One can use this capability to associate more than one filter to any one buffer. When a receive buffer is programmed to use standard identifier messages, part of the full acceptance filter register can be used as a data byte filter. The length of the data byte filter is programmable from 0 to 18 bits. This functionality simplifies implementation of high-level protocols, such as the DeviceNetTM protocol. The following is the list of resources available in Mode 1: Three transmit buffers: TXB0, TXB1 and TXB2 Two receive buffers: RXB0 and RXB1 Six buffers programmable as TX or RX: B0-B5 Automatic RTR handling on B0-B5 Sixteen dynamically assigned acceptance filters: RXF0-RXF15 * Two dedicated acceptance mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 * Programmable data filter on standard identifier messages: SDFLC * * * * * 27.3.6 ERROR RECOGNITION MODE The module can be set to ignore all errors and receive any message. In functional Mode 0, the Error Recognition mode is activated by setting the RXM<1:0> bits in the RXBnCON registers to `11'. In this mode, the data which is in the message assembly buffer until the error time, is copied in the receive buffer and can be read via the CPU interface. 2011 Microchip Technology Inc. Preliminary DS39977C-page 443 PIC18F66K80 FAMILY 27.4.3 MODE 2 - ENHANCED FIFO MODE In Mode 2, two or more receive buffers are used to form the receive FIFO (first in, first out) buffer. There is no one-to-one relationship between the receive buffer and acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate acceptance and cause FIFO to be updated. FIFO length is user-programmable, from 2-8 buffers deep. FIFO length is determined by the very first programmable buffer that is configured as a transmit buffer. For example, if Buffer 2 (B2) is programmed as a transmit buffer, FIFO consists of RXB0, RXB1, B0 and B1, creating a FIFO length of 4. If all programmable buffers are configured as receive buffers, FIFO will have the maximum length of 8. The following is the list of resources available in Mode 2: * Three transmit buffers: TXB0, TXB1 and TXB2 * Two receive buffers: RXB0 and RXB1 * Six buffers programmable as TX or RX; receive buffers form FIFO: B0-B5 * Automatic RTR handling on B0-B5 * Sixteen acceptance filters: RXF0-RXF15 * Two dedicated acceptance mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 * Programmable data filter on standard identifier messages: SDFLC, useful for DeviceNet protocol Each receive buffer contains one Control register (RXBnCON), four Identifier registers (RXBnSIDL, RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length Count register (RXBnDLC) and eight Data Byte registers (RXBnDm). There is also a separate Message Assembly Buffer (MAB) which acts as an additional receive buffer. MAB is always committed to receiving the next message from the bus and is not directly accessible to user firmware. The MAB assembles all incoming messages one by one. A message is transferred to appropriate receive buffers only if the corresponding acceptance filter criteria is met. 27.5.3 PROGRAMMABLE TRANSMIT/ RECEIVE BUFFERS The ECAN module implements six new buffers: B0-B5. These buffers are individually programmable as either transmit or receive buffers. These buffers are available only in Mode 1 and 2. As with dedicated transmit and receive buffers, each of these programmable buffers occupies 14 bytes of SRAM and are mapped into SFR memory map. Each buffer contains one Control register (BnCON), four Identifier registers (BnSIDL, BnSIDH, BnEIDL, BnEIDH), one Data Length Count register (BnDLC) and eight Data Byte registers (BnDm). Each of these registers contains two sets of control bits. Depending on whether the buffer is configured as transmit or receive, one would use the corresponding control bit set. By default, all buffers are configured as receive buffers. Each buffer can be individually configured as a transmit or receive buffer by setting the corresponding TXENn bit in the BSEL0 register. When configured as transmit buffers, user firmware may access transmit buffers in any order similar to accessing dedicated transmit buffers. In receive configuration with Mode 1 enabled, user firmware may also access receive buffers in any order required. But in Mode 2, all receive buffers are combined to form a single FIFO. Actual FIFO length is programmable by user firmware. Access to FIFO must be done through the FIFO Pointer bits (FP<4:0>) in the CANCON register. It must be noted that there is no hardware protection against out of order FIFO reads. 27.5 27.5.1 CAN Message Buffers DEDICATED TRANSMIT BUFFERS The PIC18F66K80 family devices implement three dedicated transmit buffers - TXB0, TXB1 and TXB2. Each of these buffers occupies 14 bytes of SRAM and are mapped into the SFR memory map. These are the only transmit buffers available in Mode 0. Mode 1 and 2 may access these and other additional buffers. Each transmit buffer contains one Control register (TXBnCON), four Identifier registers (TXBnSIDL, TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length Count register (TXBnDLC) and eight Data Byte registers (TXBnDm). 27.5.2 DEDICATED RECEIVE BUFFERS The PIC18F66K80 family devices implement two dedicated receive buffers: RXB0 and RXB1. Each of these buffers occupies 14 bytes of SRAM and are mapped into SFR memory map. These are the only receive buffers available in Mode 0. Mode 1 and 2 may access these and other additional buffers. DS39977C-page 444 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.5.4 PROGRAMMABLE AUTO-RTR BUFFERS In Mode 1 and 2, any of six programmable transmit/ receive buffers may be programmed to automatically respond to predefined RTR messages without user firmware intervention. Automatic RTR handling is enabled by setting the TX2EN bit in the BSEL0 register and the RTREN bit in the BnCON register. After this setup, when an RTR request is received, the TXREQ bit is automatically set and the current buffer content is automatically queued for transmission as a RTR response. As with all transmit buffers, once the TXREQ bit is set, buffer registers become read-only and any writes to them will be ignored. The following outlines the steps automatically handle RTR messages: 1. 2. required to Setting the TXREQ bit does not initiate a message transmission; it merely flags a message buffer as ready for transmission. Transmission will start when the device detects that the bus is available. The device will then begin transmission of the highest priority message that is ready. When the transmission has completed successfully, the TXREQ bit will be cleared, the TXBnIF bit will be set and an interrupt will be generated if the TXBnIE bit is set. If the message transmission fails, the TXREQ will remain set, indicating that the message is still pending for transmission and one of the following condition flags will be set. If the message started to transmit but encountered an error condition, the TXERR and the IRXIF bits will be set and an interrupt will be generated. If the message lost arbitration, the TXLARB bit will be set. 3. 4. Set buffer to Transmit mode by setting the TXnEN bit to `1' in the BSEL0 register. At least one acceptance filter must be associated with this buffer and preloaded with the expected RTR identifier. Bit, RTREN in the BnCON register, must be set to `1'. Buffer must be preloaded with the data to be sent as a RTR response. 27.6.2 ABORTING TRANSMISSION Normally, user firmware will keep buffer data registers up to date. If firmware attempts to update the buffer while an automatic RTR response is in the process of transmission, all writes to buffers are ignored. 27.6 27.6.1 CAN Message Transmission INITIATING TRANSMISSION For the MCU to have write access to the message buffer, the TXREQ bit must be clear, indicating that the message buffer is clear of any pending message to be transmitted. At a minimum, the SIDH, SIDL and DLC registers must be loaded. If data bytes are present in the message, the Data registers must also be loaded. If the message is to use extended identifiers, the EIDH:EIDL registers must also be loaded and the EXIDE bit set. To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. To successfully complete the transmission, there must be at least one node with matching baud rate on the network. The MCU can request to abort a message by clearing the TXREQ bit associated with the corresponding message buffer (TXBnCON<3> or BnCON<3>). Setting the ABAT bit (CANCON<4>) will request an abort of all pending messages. If the message has not yet started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. The abort is indicated when the module sets the TXABT bit for the corresponding buffer (TXBnCON<6> or BnCON<6>). If the message has started to transmit, it will attempt to transmit the current message fully. If the current message is transmitted fully and is not lost to arbitration or an error, the TXABT bit will not be set because the message was transmitted successfully. Likewise, if a message is being transmitted during an abort request and the message is lost to arbitration or an error, the message will not be retransmitted and the TXABT bit will be set, indicating that the message was successfully aborted. Once an abort is requested by setting the ABAT or TXABT bits, it cannot be cleared to cancel the abort request. Only CAN module hardware or a POR condition can clear it. 2011 Microchip Technology Inc. Preliminary DS39977C-page 445 PIC18F66K80 FAMILY 27.6.3 TRANSMIT PRIORITY Transmit priority is a prioritization within the PIC18F66K80 family devices of the pending transmittable messages. This is independent from, and not related to, any prioritization implicit in the message arbitration scheme built into the CAN protocol. Prior to sending the Start-of-Frame (SOF), the priority of all buffers that are queued for transmission is compared. The transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If the TXP bits for a particular message buffer are set to `11', that buffer has the highest possible priority. If the TXP bits for a particular message buffer are set to `00', that buffer has the lowest possible priority. FIGURE 27-2: TRANSMIT BUFFERS TXB0 MESSAGE TXLARB TXLARB TXB1 MESSAGE TXLARB TXB2 MESSAGE TXB3-TXB8 MESSAGE TXLARB TXREQ TXREQ TXREQ TXREQ TXERR TXERR TXERR TXERR TXB0IF TXB1IF TXB2IF Message Queue Control Transmit Byte Sequencer DS39977C-page 446 Preliminary 2011 Microchip Technology Inc. TXB2IF TXABT TXABT TXABT TXABT PIC18F66K80 FAMILY 27.7 27.7.1 Message Reception RECEIVING A MESSAGE Of all receive buffers, the MAB is always committed to receiving the next message from the bus. The MCU can access one buffer while the other buffer is available for message reception or holding a previously received message. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted. This means that regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is overwritten with the MAB contents. Therefore, the contents of all registers in the buffer must be assumed to have been modified when any message is received. When a message is moved into either of the receive buffers, the associated RXFUL bit is set. This bit must be cleared by the MCU when it has completed processing the message in the buffer in order to allow a new message to be received into the buffer. This bit provides a positive lockout to ensure that the firmware has finished with the message before the module attempts to load a new message into the receive buffer. If the receive interrupt is enabled, an interrupt will be generated to indicate that a valid message has been received. Once a message is loaded into any matching buffer, user firmware may determine exactly what filter caused this reception by checking the filter hit bits in the RXBnCON or BnCON registers. In Mode 0, FILHIT<2:0> of RXBnCON serve as filter hit bits. In Mode 1 and 2, FILHIT<4:0> bits of BnCON serve as filter hit bits. The same registers also indicate whether the current message is an RTR frame or not. A received message is considered a standard identifier message if the EXID/EXIDE bit in the RXBnSIDL or the BnSIDL register is cleared. Conversely, a set EXID bit indicates an extended identifier message. If the received message is a standard identifier message, user firmware needs to read the SIDL and SIDH registers. In the case of an extended identifier message, firmware should read the SIDL, SIDH, EIDL and EIDH registers. If the RXBnDLC or BnDLC register contain non-zero data count, user firmware should also read the corresponding number of data bytes by accessing the RXBnDm or the BnDm registers. When a received message is an RTR, and if the current buffer is not configured for automatic RTR handling, user firmware must take appropriate action and respond manually. Each receive buffer contains RXM bits to set special Receive modes. In Mode 0, RXM<1:0> bits in RXBnCON define a total of four Receive modes. In Mode 1 and 2, RXM1 bit, in combination with the EXID mask and filter bit, define the same four receive modes. Normally, these bits are set to `00' to enable reception of all valid messages as determined by the appropriate acceptance filters. In this case, the determination of whether or not to receive standard or extended messages is determined by the EXIDE bit in the acceptance filter register. In Mode 0, if the RXM bits are set to `01' or `10', the receiver will accept only messages with standard or extended identifiers, respectively. If an acceptance filter has the EXIDE bit set, such that it does not correspond with the RXM mode, that acceptance filter is rendered useless. In Mode 1 and 2, setting EXID in the SIDL Mask register will ensure that only standard or extended identifiers are received. These two modes of RXM bits can be used in systems where it is known that only standard or extended messages will be on the bus. If the RXM bits are set to `11' (RXM1 = 1 in Mode 1 and 2), the buffer will receive all messages regardless of the values of the acceptance filters. Also, if a message has an error before the end of frame, that portion of the message assembled in the MAB before the error frame will be loaded into the buffer. This mode may serve as a valuable debugging tool for a given CAN network. It should not be used in an actual system environment as the actual system will always have some bus errors and all nodes on the bus are expected to ignore them. In Mode 1 and 2, when a programmable buffer is configured as a transmit buffer and one or more acceptance filters are associated with it, all incoming messages matching this acceptance filter criteria will be discarded. To avoid this scenario, user firmware must make sure that there are no acceptance filters associated with a buffer configured as a transmit buffer. 27.7.2 RECEIVE PRIORITY When in Mode 0, RXB0 is the higher priority buffer and has two message acceptance filters associated with it. RXB1 is the lower priority buffer and has four acceptance filters associated with it. The lower number of acceptance filters makes the match on RXB0 more restrictive and implies a higher priority for that buffer. Additionally, the RXB0CON register can be configured such that if RXB0 contains a valid message and another valid message is received, an overflow error will not occur and the new message will be moved into RXB1 regardless of the acceptance criteria of RXB1. There are also two programmable acceptance filter masks available, one for each receive buffer (see Section 27.5 "CAN Message Buffers"). In Mode 1 and 2, there are a total of 16 acceptance filters available and each can be dynamically assigned to any of the receive buffers. A buffer with a lower number has higher priority. Given this, if an incoming message matches with two or more receive buffer acceptance criteria, the buffer with the lower number will be loaded with that message. 2011 Microchip Technology Inc. Preliminary DS39977C-page 447 PIC18F66K80 FAMILY 27.7.3 ENHANCED FIFO MODE 27.7.4 TIME-STAMPING When configured for Mode 2, two of the dedicated receive buffers in combination with one or more programmable transmit/receive buffers, are used to create a maximum of an 8 buffers deep FIFO buffer. In this mode, there is no direct correlation between filters and receive buffer registers. Any filter that has been enabled can generate an acceptance. When a message has been accepted, it is stored in the next available receive buffer register and an internal Write Pointer is incremented. The FIFO can be a maximum of 8 buffers deep. The entire FIFO must consist of contiguous receive buffers. The FIFO head begins at RXB0 buffer and its tail spans toward B5. The maximum length of the FIFO is limited by the presence or absence of the first transmit buffer starting from B0. If a buffer is configured as a transmit buffer, the FIFO length is reduced accordingly. For instance, if B3 is configured as a transmit buffer, the actual FIFO will consist of RXB0, RXB1, B0, B1 and B2, a total of 5 buffers. If B0 is configured as a transmit buffer, the FIFO length will be 2. If none of the programmable buffers are configured as a transmit buffer, the FIFO will be 8 buffers deep. A system that requires more transmit buffers should try to locate transmit buffers at the very end of B0-B5 buffers to maximize available FIFO length. When a message is received in FIFO mode, the interrupt flag code bits (EICODE<4:0>) in the CANSTAT register will have a value of `10000', indicating the FIFO has received a message. FIFO Pointer bits, FP<3:0> in the CANCON register, point to the buffer that contains data not yet read. The FIFO Pointer bits, in this sense, serve as the FIFO Read Pointer. The user should use the FP bits and read corresponding buffer data. When receive data is no longer needed, the RXFUL bit in the current buffer must be cleared, causing FP<3:0> to be updated by the module. To determine whether FIFO is empty or not, the user may use the FP<3:0> bits to access the RXFUL bit in the current buffer. If RXFUL is cleared, the FIFO is considered to be empty. If it is set, the FIFO may contain one or more messages. In Mode 2, the module also provides a bit called FIFO High Water Mark (FIFOWM) in the ECANCON register. This bit can be used to cause an interrupt whenever the FIFO contains only one or four empty buffers. The FIFO high water mark interrupt can serve as an early warning to a full FIFO condition. The CAN module can be programmed to generate a time-stamp for every message that is received. When enabled, the module generates a capture signal for CCP1, which in turn captures the value of either Timer1 or Timer3. This value can be used as the message time-stamp. To use the time-stamp capability, the CANCAP bit (CIOCON<4>) must be set. This replaces the capture input for CCP1 with the signal generated from the CAN module. In addition, CCP1CON<3:0> must be set to `0011' to enable the CCP Special Event Trigger for CAN events. 27.8 Message Acceptance Filters and Masks The message acceptance filters and masks are used to determine if a message in the Message Assembly Buffer should be loaded into any of the receive buffers. Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values. If there is a match, that message will be loaded into the appropriate receive buffer. The filter masks are used to determine which bits in the identifier are examined with the filters. A truth table is shown below in Table 27-1 that indicates how each bit in the identifier is compared to the masks and filters to determine if a message should be loaded into a receive buffer. The mask essentially determines which bits to apply the acceptance filters to. If any mask bit is set to a zero, then that bit will automatically be accepted regardless of the filter bit. TABLE 27-1: Mask bit n 0 1 1 1 1 FILTER/MASK TRUTH TABLE Filter bit n x 0 0 1 1 Message Identifier bit n001 x 0 1 0 1 Accept or Reject bit n Accept Accept Reject Reject Accept Legend: x = don't care In Mode 0, acceptance filters, RXF0 and RXF1, and filter mask, RXM0, are associated with RXB0. Filters, RXF2, RXF3, RXF4 and RXF5, and mask, RXM1, are associated with RXB1. DS39977C-page 448 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY In Mode 1 and 2, there are an additional 10 acceptance filters, RXF6-RXF15, creating a total of 16 available filters. RXF15 can be used either as an acceptance filter or acceptance mask register. Each of these acceptance filters can be individually enabled or disabled by setting or clearing the RXFENn bit in the RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive buffers. Actual association is made by setting the appropriate bits in the RXFBCONn register. Each RXFBCONn register contains a nibble for each filter. This nibble can be used to associate a specific filter to any of available receive buffers. User firmware may associate more than one filter to any one specific receive buffer. In addition to dynamic filter to buffer association, in Mode 1 and 2, each filter can also be dynamically associated to available Acceptance Mask registers. The FILn_m bits in the MSELn register can be used to link a specific acceptance filter to an acceptance mask register. As with filter to buffer association, one can also associate more than one mask to a specific acceptance filter. When a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the FILHIT bit(s). In Mode 0 for RXB1, the RXB1CON register contains the FILHIT<2:0> bits. They are coded as follows: * * * * * * 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 (RXF0) Note: The coding of the RXB0DBEN bit enables these three bits to be used similarly to the FILHIT bits and to distinguish a hit on filter, RXF0 and RXF1, in either RXB0 or after a rollover into RXB1. * * * * 111 = Acceptance Filter 1 (RXF1) 110 = Acceptance Filter 0 (RXF0) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 (RXF0) If the RXB0DBEN bit is clear, there are six codes corresponding to the six filters. If the RXB0DBEN bit is set, there are six codes corresponding to the six filters, plus two additional codes corresponding to RXF0 and RXF1 filters, that rollover into RXB1. In Mode 1 and 2, each buffer control register contains 5 bits of filter hit bits (FILHIT<4:0>). A binary value of `0' indicates a hit from RXF0 and 15 indicates RXF15. If more than one acceptance filter matches, the FILHIT bits will encode the binary value of the lowest numbered filter that matched. In other words, if filter RXF2 and filter RXF4 match, FILHIT will be loaded with the value for RXF2. This essentially prioritizes the acceptance filters with a lower number filter having higher priority. Messages are compared to filters in ascending order of filter number. The mask and filter registers can only be modified when the PIC18F66K80 family devices are in Configuration mode. `000' and `001' can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to rollover into RXB1. FIGURE 27-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Mask Register RXMn0 RXFn1 RXMn1 RxRqst Acceptance Filter Register RXFn0 RXFnn RXMnn Message Assembly Buffer Identifier 2011 Microchip Technology Inc. Preliminary DS39977C-page 449 PIC18F66K80 FAMILY 27.9 Baud Rate Setting All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter's clock. As oscillators and transmission time may vary from node to node, the receiver must have some type of Phase Lock Loop (PLL) synchronized to data transmission edges to synchronize and maintain the receiver clock. Since the data is NRZ coded, it is necessary to include bit stuffing to ensure that an edge occurs at least every six bit times to maintain the Digital Phase Lock Loop (DPLL) synchronization. The bit timing of the PIC18F66K80 family is implemented using a DPLL that is configured to synchronize to the incoming data and provides the nominal timing for the transmitted data. The DPLL breaks each bit time into multiple segments made up of minimal periods of time called the Time Quanta (TQ). Bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network transmission delay compensation and sample point positioning, are defined by the programmable bit timing logic of the DPLL. All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same master oscillator clock frequency. For the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each segment. The "Nominal Bit Rate" is the number of bits transmitted per second, assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. The nominal bit rate is defined to be a maximum of 1 Mb/s. The "Nominal Bit Time" is defined as: The Nominal Bit Time can be thought of as being divided into separate, non-overlapping time segments. These segments (Figure 27-4) include: * * * * Synchronization Segment (Sync_Seg) Propagation Time Segment (Prop_Seg) Phase Buffer Segment 1 (Phase_Seg1) Phase Buffer Segment 2 (Phase_Seg2) The time segments (and thus, the Nominal Bit Time) are, in turn, made up of integer units of time called Time Quanta or TQ (see Figure 27-4). By definition, the Nominal Bit Time is programmable from a minimum of 8 TQ to a maximum of 25 TQ. Also by definition, the minimum Nominal Bit Time is 1 s, corresponding to a maximum 1 Mb/s rate. The actual duration is given by the following relationship. EQUATION 27-2: Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) The Time Quantum is a fixed unit derived from the oscillator period. It is also defined by the programmable baud rate prescaler, with integer values from 1 to 64, in addition to a fixed divide-by-two for clock generation. Mathematically, this is: EQUATION 27-3: TQ (s) = (2 * (BRP + 1))/FOSC (MHz) or TQ (s) = (2 * (BRP + 1)) * TOSC (s) EQUATION 27-1: TBIT = 1/Nominal Bit Rate where FOSC is the clock frequency, TOSC is the corresponding oscillator period and BRP is an integer (0 through 63) represented by the binary values of BRGCON1<5:0>. The equation above refers to the effective clock frequency used by the microcontroller. If, for example, a 10 MHz crystal in HS mode is used, then FOSC = 10 MHz and TOSC = 100 ns. If the same 10 MHz crystal is used in HS-PLL mode, then the effective frequency is FOSC = 40 MHz and TOSC = 25 ns. FIGURE 27-4: Input Signal Bit Time Intervals TQ BIT TIME PARTITIONING Sync Propagation Segment Segment Phase Segment 1 Phase Segment 2 Sample Point Nominal Bit Time DS39977C-page 450 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.9.1 EXTERNAL CLOCK, INTERNAL CLOCK AND MEASURABLE JITTER IN HS-PLL BASED OSCILLATORS The CAN protocol uses a bit-stuffing technique that inserts a bit of a given polarity following five bits with the opposite polarity. This gives a total of 10 bits transmitted without resynchronization (compensation for jitter or phase error). Given the random nature of the added jitter error, it can be shown that the total error caused by the jitter tends to cancel itself over time. For a period of 10 bits, it is necessary to add only two jitter intervals to correct for jitter induced error: one interval in the beginning of the 10-bit period and another at the end. The overall effect is shown in Figure 27-5. The microcontroller clock frequency generated from a PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced microcontrollers, Microchip specifies phase jitter (Pjitter) as being 2% (Gaussian distribution, within 3 standard deviations, see Parameter F13 in Table 31-7) and Total Jitter (Tjitter) as being 2 * Pjitter. FIGURE 27-5: EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK AND CAN BIT TIME Nominal Clock Clock with Jitter Phase Skew (Jitter) CAN Bit Time with Jitter CAN Bit Jitter Once these considerations are taken into account, it is possible to show that the relation between the jitter and the total frequency error can be defined as: T jitter 2 P jitter f = ----------------------- = ----------------------10 NBT 10 NBT For example, assume a CAN bit rate of 125 Kb/s, which gives an NBT of 8 s. For a 16 MHz clock generated from a 4x PLL, the jitter at this clock frequency is: 1 0.02 2% ------------------- = ----------------- = 1.25ns 6 16 MHz 16 10 where jitter is expressed in terms of time and NBT is the Nominal Bit Time. and resultant frequency error is: 2 1.25 10 -5 -------------------------------------- = 3.125 10 = 0.0031% -6 10 8 10 -9 2011 Microchip Technology Inc. Preliminary DS39977C-page 451 PIC18F66K80 FAMILY Table 27-2 shows the relation between the clock generated by the PLL and the frequency error from jitter (measured jitter-induced error of 2%, Gaussian distribution, within 3 standard deviations), as a percentage of the nominal clock frequency. This is clearly smaller than the expected drift of a crystal oscillator, typically specified at 100 ppm or 0.01%. If we add jitter to oscillator drift, we have a total frequency drift of 0.0132%. The total oscillator frequency errors for common clock frequencies and bit rates, including both drift and jitter, are shown in Table 27-3. TABLE 27-2: PLL Output FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS Frequency Error at Various Nominal Bit Times (Bit Rates) Pjitter Tjitter 8 s (125 Kb/s) 4 s (250 Kb/s) 2 s (500 Kb/s) 1 s (1 Mb/s) 40 MHz 24 MHz 16 MHz 0.5 ns 0.83 ns 1.25 ns 1 ns 1.67 ns 2.5 ns 0.00125% 0.00209% 0.00313% 0.00250% 0.00418% 0.00625% 0.005% 0.008% 0.013% 0.01% 0.017% 0.025% TABLE 27-3: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS (100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER) Frequency Error at Various Nominal Bit Times (Bit Rates) 8 s (125 Kb/s) 4 s (250 Kb/s) 2 s (500 Kb/s) 1 s (1 Mb/s) Nominal PLL Output 40 MHz 24 MHz 16 MHz 0.01125% 0.01209% 0.01313% 0.01250% 0.01418% 0.01625% 0.015% 0.018% 0.023% 0.02% 0.027% 0.035% DS39977C-page 452 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.9.2 TIME QUANTA 27.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 27-6. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. EXAMPLE 27-6: CALCULATING TQ, NOMINAL BIT RATE AND NOMINAL BIT TIME 27.9.4 PROPAGATION SEGMENT TQ (s) = (2 * (BRP + 1))/FOSC (MHz) TBIT (s) = TQ (s) * number of TQ per bit interval Nominal Bit Rate (bits/s) = 1/TBIT This part of the bit time is used to compensate for physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The length of the propagation segment can be programmed from 1 TQ to 8 TQ by setting the PRSEG<2:0> bits. This frequency (FOSC) refers to the effective frequency used. If, for example, a 10 MHz external signal is used along with a PLL, then the effective frequency will be 4 x 10 MHz which equals 40 MHz. CASE 1: For FOSC = 16 MHz, BRP<5:0> = 00h and Nominal Bit Time = 8 TQ: TQ = (2 * 1)/16 = 0.125 s (125 ns) TBIT = 8 * 0.125 = 1 s (10-6s) Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s) CASE 2: For FOSC = 20 MHz, BRP<5:0> = 01h and Nominal Bit Time = 8 TQ: TQ = (2 * 2)/20 = 0.2 s (200 ns) TBIT = 8 * 0.2 = 1.6 s (1.6 * 10-6s) Nominal Bit Rate = 1/1.6 * 10-6s = 625,000 bits/s (625 Kb/s) 27.9.5 PHASE BUFFER SEGMENTS The phase buffer segments are used to optimally locate the sampling point of the received bit within the nominal bit time. The sampling point occurs between Phase Segment 1 and Phase Segment 2. These segments can be lengthened or shortened by the resynchronization process. The end of Phase Segment 1 determines the sampling point within a bit time. Phase Segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase Segment 2 provides a delay before the next transmitted data transition and is also programmable from 1 TQ to 8 TQ in duration. However, due to IPT requirements, the actual minimum length of Phase Segment 2 is 2 TQ, or it may be defined to be equal to the greater of Phase Segment 1 or the Information Processing Time (IPT). The sampling point should be as late as possible or approximately 80% of the bit time. 27.9.6 SAMPLE POINT CASE 3: For FOSC = 25 MHz, BRP<5:0> = 3Fh and Nominal Bit Time = 25 TQ: TQ = (2 * 64)/25 = 5.12 s TBIT = 25 * 5.12 = 128 s (1.28 * 10-4s) Nominal Bit Rate = 1/1.28 * 10-4 = 7813 bits/s (7.8 Kb/s) The sample point is the point of time at which the bus level is read and the value of the received bit is determined. The sampling point occurs at the end of Phase Segment 1. If the bit timing is slow and contains many TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is determined to be the value of the majority decision of three values. The three samples are taken at the sample point and twice before, with a time of TQ/2 between each sample. 27.9.7 INFORMATION PROCESSING TIME The frequencies of the oscillators in the different nodes must be coordinated in order to provide a system wide specified nominal bit time. This means that all oscillators must have a TOSC that is an integral divisor of TQ. It should also be noted that although the number of TQ is programmable from 4 to 25, the usable minimum is 8 TQ. There is no assurance that a bit time of less than 8 TQ in length will operate correctly. The Information Processing Time (IPT) is the time segment starting at the sample point that is reserved for calculation of the subsequent bit level. The CAN specification defines this time to be less than or equal to 2 TQ. The PIC18F66K80 family devices define this time to be 2 TQ. Thus, Phase Segment 2 must be at least 2 TQ long. 2011 Microchip Technology Inc. Preliminary DS39977C-page 453 PIC18F66K80 FAMILY 27.10 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg). The circuit will then adjust the values of Phase Segment 1 and Phase Segment 2 as necessary. There are two mechanisms used for synchronization. The phase error of an edge is given by the position of the edge relative to Sync_Seg, measured in TQ. The phase error is defined in magnitude of TQ as follows: * e = 0 if the edge lies within Sync_Seg. * e > 0 if the edge lies before the sample point. * e < 0 if the edge lies after the sample point of the previous bit. If the magnitude of the phase error is less than, or equal to, the programmed value of the Synchronization Jump Width, the effect of a resynchronization is the same as that of a hard synchronization. If the magnitude of the phase error is larger than the Synchronization Jump Width and if the phase error is positive, then Phase Segment 1 is lengthened by an amount equal to the Synchronization Jump Width. If the magnitude of the phase error is larger than the resynchronization jump width and if the phase error is negative, then Phase Segment 2 is shortened by an amount equal to the Synchronization Jump Width. 27.10.1 HARD SYNCHRONIZATION Hard synchronization is only done when there is a recessive to dominant edge during a bus Idle condition, indicating the start of a message. After hard synchronization, the bit time counters are restarted with Sync_Seg. Hard synchronization forces the edge, which has occurred to lie within the synchronization segment of the restarted bit time. Due to the rules of synchronization, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 27.10.3 SYNCHRONIZATION RULES 27.10.2 RESYNCHRONIZATION As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened. The amount of lengthening or shortening of the phase buffer segments has an upper bound given by the Synchronization Jump Width (SJW). The value of the SJW will be added to Phase Segment 1 (see Figure 27-6) or subtracted from Phase Segment 2 (see Figure 27-7). The SJW is programmable between 1 TQ and 4 TQ. Clocking information will only be derived from recessive to dominant transitions. The property, that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. * Only one synchronization within one bit time is allowed. * An edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge. * All other recessive to dominant edges fulfilling rules 1 and 2 will be used for resynchronization, with the exception that a node transmitting a dominant bit will not perform a resynchronization as a result of a recessive to dominant edge with a positive phase error. FIGURE 27-6: Input Signal Bit Time Segments TQ Sync LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Prop Segment Phase Segment 1 SJW Phase Segment 2 Sample Point Nominal Bit Length Actual Bit Length DS39977C-page 454 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 27-7: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Sync Prop Segment Phase Segment 1 Phase Segment 2 SJW TQ Actual Bit Length Sample Point Nominal Bit Length 27.11 Programming Time Segments Some requirements for programming of the time segments: * Prop_Seg + Phase_Seg 1 Phase_Seg 2 * Phase_Seg 2 Sync Jump Width. For example, assume that a 125 kHz CAN baud rate is desired, using 20 MHz for FOSC. With a TOSC of 50 ns, a baud rate prescaler value of 04h gives a TQ of 500 ns. To obtain a Nominal Bit Rate of 125 kHz, the Nominal Bit Time must be 8 s or 16 TQ. Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg and 7 TQ for Phase Segment 1 would place the sample point at 10 TQ after the transition. This leaves 6 TQ for Phase Segment 2. By the rules above, the Sync Jump Width could be the maximum of 4 TQ. However, normally a large SJW is only necessary when the clock generation of the different nodes is inaccurate or unstable, such as using ceramic resonators. Typically, an SJW of 1 is enough. 27.12 Oscillator Tolerance As a rule of thumb, the bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 Kbit/sec. For the full bus speed range of the CAN protocol, a quartz oscillator is required. Refer to ISO11898-1 for oscillator tolerance requirements. 2011 Microchip Technology Inc. Preliminary DS39977C-page 455 PIC18F66K80 FAMILY 27.13 Bit Timing Configuration Registers The Baud Rate Control registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18F66K80 family devices are in Configuration mode. 27.14.2 ACKNOWLEDGE ERROR In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which was sent out as a recessive bit) contains a dominant bit. If not, no other node has received the frame correctly. An Acknowledge error has occurred, an error frame is generated and the message will have to be repeated. 27.13.1 BRGCON1 27.14.3 FORM ERROR The BRP bits control the baud rate prescaler. The SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. 27.13.2 BRGCON2 If a node detects a dominant bit in one of the four segments, including End-of-Frame (EOF), interframe space, Acknowledge delimiter or CRC delimiter, then a form error has occurred and an error frame is generated. The message is repeated. The PRSEG bits set the length of the propagation segment in terms of TQ. The SEG1PH bits set the length of Phase Segment 1 in TQ. The SAM bit controls how many times the RXCAN pin is sampled. Setting this bit to a `1' causes the bus to be sampled three times: twice at TQ/2 before the sample point and once at the normal sample point (which is at the end of Phase Segment 1). The value of the bus is determined to be the value read during at least two of the samples. If the SAM bit is set to a `0', then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the length of Phase Segment 2 is determined. If this bit is set to a `1', then the length of Phase Segment 2 is determined by the SEG2PH bits of BRGCON3. If the SEG2PHTS bit is set to a `0', then the length of Phase Segment 2 is the greater of Phase Segment 1 and the information processing time (which is fixed at 2 TQ for the PIC18F66K80 family). 27.14.4 BIT ERROR A bit error occurs if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual bus level and comparing it to the just transmitted bit. In the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the Acknowledge slot, no bit error is generated because normal arbitration is occurring. 27.14.5 STUFF BIT ERROR lf, between the Start-of-Frame (SOF) and the CRC delimiter, six consecutive bits with the same polarity are detected, the bit stuffing rule has been violated. A stuff bit error occurs and an error frame is generated. The message is repeated. 27.14.6 ERROR STATES 27.13.3 BRGCON3 The PHSEG2<2:0> bits set the length (in TQ) of Phase Segment 2 if the SEG2PHTS bit is set to a `1'. If the SEG2PHTS bit is set to a `0', then the PHSEG2<2:0> bits have no effect. 27.14 Error Detection The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. 27.14.1 CRC ERROR With the Cyclic Redundancy Check (CRC), the transmitter calculates special check bits for the bit sequence, from the start of a frame until the end of the data field. This CRC sequence is transmitted in the CRC field. The receiving node also calculates the CRC sequence using the same formula and performs a comparison to the received sequence. If a mismatch is detected, a CRC error has occurred and an error frame is generated. The message is repeated. Detected errors are made public to all other nodes via error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each CAN node is in one of the three error states; "error-active", "error-passive" or "bus-off", according to the value of the internal error counters. The error-active state is the usual state where the bus node can transmit messages and activate error frames (made of dominant bits) without any restrictions. In the error-passive state, messages and passive error frames (made of recessive bits) may be transmitted. The bus-off state makes it temporarily impossible for the node to participate in the bus communication. During this state, messages can neither be received nor transmitted. 27.14.7 ERROR MODES AND ERROR COUNTERS The PIC18F66K80 family devices contain two error counters: the Receive Error Counter (RXERRCNT) and the Transmit Error Counter (TXERRCNT). The values of both counters can be read by the MCU. These counters are incremented or decremented in accordance with the CAN bus specification. DS39977C-page 456 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY The PIC18F66K80 family devices are error-active if both error counters are below the error-passive limit of 128. They are error-passive if at least one of the error counters equals or exceeds 128. They go to bus-off if the transmit error counter equals or exceeds the busoff limit of 256. The devices remain in this state until the bus-off recovery sequence is finished. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure 27-8). Note that the CAN module, after going bus-off, will recover back to error-active without any intervention by the MCU if the bus remains Idle for 128 x 11 bit times. If this is not desired, the error Interrupt Service Routine should address this. The current Error mode of the CAN module can be read by the MCU via the COMSTAT register. Additionally, there is an Error State Warning flag bit, EWARN, which is set if at least one of the error counters equals or exceeds the error warning limit of 96. EWARN is reset if both error counters are less than the error warning limit. FIGURE 27-8: ERROR MODES STATE DIAGRAM Reset ErrorActive 128 occurrences of 11 consecutive "recessive" bits RXERRCNT < 128 or TXERRCNT < 128 RXERRCNT 128 or TXERRCNT 128 ErrorPassive TXERRCNT > 255 BusOff 27.15 CAN Interrupts The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The PIR5 register contains interrupt flags. The PIE5 register contains the enables for the 8 main interrupts. A special set of read-only bits in the CANSTAT register, the ICODE bits, can be used in combination with a jump table for efficient handling of interrupts. All interrupts have one source, with the exception of the error interrupt and buffer interrupts in Mode 1 and 2. Any of the error interrupt sources can set the error interrupt flag. The source of the error interrupt can be determined by reading the Communication Status register, COMSTAT. In Mode 1 and 2, there are two interrupt enable/disable and flag bits - one for all transmit buffers and the other for all receive buffers. The interrupts can be broken up into two categories: receive and transmit interrupts. The receive related interrupts are: * * * * * * * * * Receive Interrupts Wake-up Interrupt Receiver Overrun Interrupt Receiver Warning Interrupt Receiver Error-Passive Interrupt Transmit Interrupts Transmitter Warning Interrupt Transmitter Error-Passive Interrupt Bus-Off Interrupt The transmit related interrupts are: 2011 Microchip Technology Inc. Preliminary DS39977C-page 457 PIC18F66K80 FAMILY 27.15.1 INTERRUPT CODE BITS TABLE 27-4: ICODE Interrupt <2:0> 000 001 010 011 100 101 110 111 VALUES FOR ICODE<2:0> Boolean Expression To simplify the interrupt handling process in user firmware, the ECAN module encodes a special set of bits. In Mode 0, these bits are ICODE<3:1> in the CANSTAT register. In Mode 1 and 2, these bits are EICODE<4:0> in the CANSTAT register. Interrupts are internally prioritized such that the higher priority interrupts are assigned lower values. Once the highest priority interrupt condition has been cleared, the code for the next highest priority interrupt that is pending (if any) will be reflected by the ICODE bits (see Table 27-4). Note that only those interrupt sources that have their associated interrupt enable bit set will be reflected in the ICODE bits. In Mode 2, when a receive message interrupt occurs, the EICODE bits will always consist of `10000'. User firmware may use FIFO Pointer bits to actually access the next available buffer. None Error TXB2 TXB1 TXB0 RXB1 RXB0 ERR*WAK*TX0*TX1*TX2*RX0*RX1 ERR ERR*TX0*TX1*TX2 ERR*TX0*TX1 ERR*TX0 ERR*TX0*TX1*TX2*RX0*RX1 ERR*TX0*TX1*TX2*RX0 27.15.2 TRANSMIT INTERRUPT Wake on ERR*TX0*TX1*TX2*RX0*RX1*WAK Interrupt RX0 = RXB0IF * RXB0IE RX1 = RXB1IF * RXB1IE WAK = WAKIF * WAKIE When the transmit interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. In Mode 0, there are separate interrupt enable/ disable and flag bits for each of the three dedicated transmit buffers. The TXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU, resetting the TXBnIF bit to a `0'. In Mode 1 and 2, all transmit buffers share one interrupt enable/disable bit and one flag bit. In Mode 1 and 2, TXBnIE in PIE5 and TXBnIF in PIR5 indicate when a transmit buffer has completed transmission of its message. TXBnIF, TXBnIE and TXBnIP in PIR5, PIE5 and IPR5, respectively, are not used in Mode 1 and 2. Individual transmit buffer interrupts can be enabled or disabled by setting or clearing TXBnIE and B0IE register bits. When a shared interrupt occurs, user firmware must poll the TXREQ bit of all transmit buffers to detect the source of interrupt. Legend: ERR = ERRIF * ERRIE TX0 = TXB0IF * TXB0IE TX1 = TXB1IF * TXB1IE TX2 = TXB2IF * TXB2IE 27.15.4 MESSAGE ERROR INTERRUPT When an error occurs during transmission or reception of a message, the message error flag, IRXIF, will be set and if the IRXIE bit is set, an interrupt will be generated. This is intended to be used to facilitate baud rate determination when used in conjunction with Listen Only mode. 27.15.5 BUS ACTIVITY WAKE-UP INTERRUPT 27.15.3 RECEIVE INTERRUPT When the receive interrupt is enabled, an interrupt will be generated when a message has been successfully received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving the End-of-Frame (EOF) field. In Mode 0, the RXBnIF bit is set to indicate the source of the interrupt. The interrupt is cleared by the MCU, resetting the RXBnIF bit to a `0'. In Mode 1 and 2, all receive buffers share RXBnIE, RXBnIF and RXBnIP in PIE5, PIR5 and IPR5, respectively. Bits, RXBnIE, RXBnIF and RXBnIP, are not used. Individual receive buffer interrupts can be controlled by the TXBnIE and BIE0 registers. In Mode 1, when a shared receive interrupt occurs, user firmware must poll the RXFUL bit of each receive buffer to detect the source of interrupt. In Mode 2, a receive interrupt indicates that the new message is loaded into FIFO. FIFO can be read by using FIFO Pointer bits, FP. When the PIC18F66K80 family devices are in Sleep mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated and the WAKIF bit will be set when activity is detected on the CAN bus. This interrupt causes the PIC18F66K80 family devices to exit Sleep mode. The interrupt is reset by the MCU, clearing the WAKIF bit. 27.15.6 ERROR INTERRUPT When the CAN module error interrupt (ERRIE in PIE5) is enabled, an interrupt is generated if an overflow condition occurs, or if the error state of the transmitter or receiver has changed. The error flags in COMSTAT will indicate one of the following conditions. DS39977C-page 458 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 27.15.6.1 Receiver Overflow 27.15.6.3 Transmitter Warning An overflow condition occurs when the MAB has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated RXBnOVFL bit in the COMSTAT register will be set to indicate the overflow condition. This bit must be cleared by the MCU. The transmit error counter has reached the MCU warning limit of 96. 27.15.6.4 Receiver Bus Passive This will occur when the device has gone to the errorpassive state because the receive error counter is greater or equal to 128. 27.15.6.2 Receiver Warning 27.15.6.5 Transmitter Bus Passive The receive error counter has reached the MCU warning limit of 96. This will occur when the device has gone to the errorpassive state because the transmit error counter is greater or equal to 128. 27.15.6.6 Bus-Off The transmit error counter has exceeded 255 and the device has gone to bus-off state. 2011 Microchip Technology Inc. Preliminary DS39977C-page 459 PIC18F66K80 FAMILY NOTES: DS39977C-page 460 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 28.0 SPECIAL FEATURES OF THE CPU 28.1 Configuration Bits The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location, 300000h. The user will note that address, 300000h, is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Software programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 7.5 "Writing to Flash Program Memory". The PIC18F66K80 family of devices includes several features intended to maximize reliability and minimize cost through elimination of external components. These include: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) and On-chip Regulator * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 3.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F66K80 family of devices has a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator (LF-INTOSC) also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two-Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. 2011 Microchip Technology Inc. Preliminary DS39977C-page 461 PIC18F66K80 FAMILY TABLE 28-1: File Name 300000h CONFIG1L 300001h CONFIG1H 300002h CONFIG2L 300003h CONFIG2H CONFIGURATION BITS AND DEVICE IDs Bit 7 -- IESO -- -- Bit 6 XINST FCMEN WDTPS4 -- -- -- CPB -- WRTB -- EBTRB DEV1 DEV9 Bit 5 -- -- WDTPS3 -- -- -- -- -- WRTC -- -- DEV0 DEV8 Bit 4 Bit 3 Bit 2 Bit 1 -- FOSC1 BOREN0 T0CKMX -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4 (1) Bit 0 RETEN FOSC0 PWRTEN CANMX STVREN CP0 -- WRT0 -- EBTR0 -- REV0 DEV3 Default/ Unprogrammed Value -1-1 11-1 00-0 1000 -111 1111 -111 1111 1--- 1qq1 1--1 ---1 ---- 1111 11-- ------- 1111 111- ------- 1111 -1-- ---xxxx xxxx xxxx xxxx SOSCSEL1 SOSCSEL0 INTOSCSEL PLLCFG BORV1 WDTPS2 -- BBSIZ0 -- -- -- -- -- -- REV4 DEV7 FOSC3 BORV0 WDTPS1 -- CP3 -- WRT3 -- EBTR3 -- REV3 DEV6 FOSC2 BOREN1 WDTPS0 (1,3) BORPWR1 BORWPR0 WDTEN1 WDTEN0 300005h CONFIG3H MCLRE 300006h CONFIG4L DEBUG 300008h CONFIG5L 300009h CONFIG5H 30000Ah CONFIG6L 30000Bh CONFIG6H 30000Ch CONFIG7L 30000Dh CONFIG7H 3FFFFEh DEVID1(2) 3FFFFFh DEVID2(2) Legend: Note 1: 2: 3: -- CPD -- WRTD -- -- DEV2 DEV10 MSSPMSK T3CKMX -- CP2 -- WRT2 -- EBTR2 -- REV2 DEV5 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Implemented only on the 64-pin devices (PIC18F6XK80). See Register 28-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. Maintain as `0' on 28-pin, 40-pin and 44-pin devices. DS39977C-page 462 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-1: U-0 -- bit 7 Legend: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/P-1 XINST U-0 -- R/P-1 R/P-1 R/P-1 INTOSCSEL U-0 -- R/P-1 RETEN bit 0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SOSCSEL1 SOSCSEL0 R = Readable bit -n = Value at POR bit 7 bit 6 Unimplemented: Read as `0' XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode) Unimplemented: Read as `0' SOSCSEL<1:0>: SOSC Power Selection and Mode Configuration bits 11 = High-power SOSC circuit is selected 10 = Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled 01 = Low-power SOSC circuit is selected 00 = Reserved INTOSCSEL: LF-INTOSC Low-power Enable bit 1 = LF-INTOSC in High-Power mode during Sleep 0 = LF-INTOSC in Low-Power mode during Sleep Unimplemented: Read as `0' RETEN: VREG Sleep Enable bit 1 = Ultra low-power regulator is disabled. Regulator power in Sleep mode is controlled by REGSLP (WDTCON<7>). 0 = Ultra low-power regulator is enabled. Regulator power in Sleep mode is controlled by SRETEN (WDTCON<4>). bit 5 bit 4-3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS39977C-page 463 PIC18F66K80 FAMILY REGISTER 28-2: R/P-0 IESO bit 7 Legend: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 U-0 -- U-0 PLLCFG(1) R/P-1 FOSC3(2) R/P-0 FOSC2(2) R/P-0 FOSC1(2) R/P-0 FOSC0(2) bit 0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FCMEN R = Readable bit -n = Value at POR bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled Unimplemented: Read as `0' PLLCFG: 4X PLL Enable bit(1) 1 = Oscillator is multiplied by 4 0 = Oscillator is used directly FOSC<3:0>: Oscillator Selection bits(2) 1101 = EC1, EC oscillator (low power, DC-160 kHz) 1100 = EC1IO, EC oscillator with CLKOUT function on RA6 (low power, DC-160 kHz) 1011 = EC2, EC oscillator (medium power, 160 kHz-16 MHz) 1010 = EC2IO, EC oscillator with CLKOUT function on RA6 (medium power, 160 kHz-16 MHz) 0101 = EC3, EC oscillator (high power, 16 MHz-64 MHz) 0100 = EC3IO, EC oscillator with CLKOUT function on RA6 (high power, 16 MHz-64 MHz) 0011 = HS1, HS oscillator (medium power, 4 MHz-16 MHz) 0010 = HS2, HS oscillator (high power, 16 MHz-25 MHz) 0001 = XT oscillator 0000 = LP oscillator 0111 = RC, external RC oscillator 0110 = RCIO, external RC oscillator with CKLOUT function on RA6 1000 = INTIO2, internal RC oscillator 1001 = INTIO1, internal RC oscillator with CLKOUT function on RA6 bit 6 bit 5 bit 4 bit 3-0 Note 1: 2: Not valid for the INTIOx PLL mode. INTIO + PLL can be enabled only by the PLLEN bit (OSCTUNE<6>). Other PLL modes can be enabled by either the PLLEN bit or the PLLCFG (CONFIG1H<4>) bit. DS39977C-page 464 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-3: U-0 -- bit 7 Legend: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/P-1 R/P-1 (1) R/P-1 (1) R/P-1 BORV0 (1) R/P-1 BOREN1 (2) R/P-1 BOREN0 (2) R/P-1 PWRTEN(2) bit 0 BORPWR1 BORPWR0 BORV1 (1) P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 bit 6-5 Unimplemented: Read as `0' BORPWR<1:0>: BORMV Power-Level bits(1) 11 = ZPBORVMV instead of BORMV is selected 10 = BORMV is set to a high-power level 01 = BORMV is set to a medium power level 00 = BORMV is set to a low-power level BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = BVDD is set to 1.8V 10 = BVDD is set to 2.0V 01 = BVDD is set to 2.7V 00 = BVDD is set to 3.0V BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset is disabled in hardware and software PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 bit 2-1 bit 0 Note 1: 2: For the specifications, see Section 31.1 "DC Characteristics: Supply Voltage PIC18F66K80 Family (Industrial/Extended)". The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. 2011 Microchip Technology Inc. Preliminary DS39977C-page 465 PIC18F66K80 FAMILY REGISTER 28-4: U-0 -- bit 7 Legend: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) R/P-1 R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN1 R/P-1 WDTEN0 bit 0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WDTPS4 R = Readable bit -n = Value at POR bit 7 bit 6-2 Unimplemented: Read as `0' WDTPS<4:0>: Watchdog Timer Postscale Select bits 11111 = Reserved 10100 = 1:1,048,576 (4,194.304s) 10011 = 1:524,288 (2,097.152s) 10010 = 1:262,144 (1,048.576s) 10001 = 1:131,072 (524.288s) 10000 = 1:65,536 (262.144s) 01111 = 1:32,768 (131.072s) 01110 = 1:16,384 (65.536s) 01101 = 1:8,192 (32.768s) 01100 = 1:4,096 (16.384s) 01011 = 1:2,048 (8.192s) 01010 = 1:1,024 (4.096s) 01001 = 1:512 (2.048s) 01000 = 1:256 (1.024s) 00111 = 1:128 (512 ms) 00110 = 1:64 (256 ms) 00101 = 1:32 (128 ms) 00100 = 1:16 (64 ms) 00011 = 1:8 (32 ms) 00010 = 1:4 (16 ms) 00001 = 1:2 (8 ms) 00000 = 1:1 (4 ms) WDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware; SWDTEN bit is disabled 10 = WDT is controlled by the SWDTEN bit setting 01 = WDT is enabled only while the device is active and is disabled in Sleep mode; SWDTEN bit is disabled 00 = WDT is disabled in hardware; SWDTEN bit is disabled bit 1-0 DS39977C-page 466 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-5: R/P-1 MCLRE bit 7 Legend: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 -- U-0 -- U-0 -- R/P-1 MSSPMSK R/P-1 T3CKMX(1) R/P-1 T0CKMX(1) R/P-1 CANMX bit 0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RE3 input pin is disabled 0 = RE3 input pin is enabled; MCLR is disabled Unimplemented: Read as `0' MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode is enabled 0 = 5-Bit Address Masking mode is enabled T3CKMX: Timer3 Clock Input MUX bit(1) 1 = Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages 0 = Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages T0CKMX: Timer0 Clock Input MUX bit(1) 1 = Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages 0 = Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages CANMX: ECAN MUX bit 1 = CANTX and CANRX pins are located on RB2 and RB3, respectively 0 = CANTX and CANRX pins are located on RC6 and RC7, respectively (28-pin and 40/44-pin packages) or on RE4 and RE5, respectively (64-pin package) bit 6-4 bit 3 bit 2 bit 1 bit 0 Note 1: Implemented only on the 64-pin devices (PIC18F6XK80). Maintain as `0' on 28-pin, 40-pin and 44-pin devices. 2011 Microchip Technology Inc. Preliminary DS39977C-page 467 PIC18F66K80 FAMILY REGISTER 28-6: R/P-1 DEBUG bit 7 Legend: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) U-0 -- U-0 -- R/P-0 BBSIZ0 U-0 -- U-0 -- U-0 -- R/P-1 STVREN bit 0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug Unimplemented: Read as `0' BBSIZ0: Boot Block Size Select bit 1 = 2 kW boot block size 0 = 1 kW boot block size Unimplemented: Read as `0' STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause a Reset 0 = Stack full/underflow will not cause a Reset bit 6-5 bit 4 bit 3-1 bit 0 DS39977C-page 468 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-7: U-0 -- bit 7 Legend: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 -- U-0 -- U-0 -- R/C-1 CP3 R/C-1 CP2 R/C-1 CP1 R/C-1 CP0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7-4 bit 3 Unimplemented: Read as `0' CP3: Code Protection bit 1 = Block 3 is not code-protected(1) 0 = Block 3 is code-protected(1) CP2: Code Protection bit 1 = Block 2 is not code-protected(1) 0 = Block 2 is code-protected(1) CP1: Code Protection bit 1 = Block 1 is not code-protected(1) 0 = Block 1 is code-protected(1) CP0: Code Protection bit 1 = Block 0 is not code-protected(1) 0 = Block 0, is code-protected(1) bit 2 bit 1 bit 0 Note 1: For the memory size of the blocks, see Figure 28-6. 2011 Microchip Technology Inc. Preliminary DS39977C-page 469 PIC18F66K80 FAMILY REGISTER 28-8: R/C-1 CPD bit 7 Legend: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected CPB: Boot Block Code Protection bit 1 = Boot block is not code-protected(1) 0 = Boot block is code-protected(1) Unimplemented: Read as `0' bit 6 bit 5-0 Note 1: For the memory size of the blocks, see Figure 28-6. The boot block size changes with BBSIZ0. DS39977C-page 470 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-9: U-0 -- bit 7 Legend: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 -- U-0 -- U-0 -- R/C-1 WRT3 R/C-1 WRT2 R/C-1 WRT1 R/C-1 WRT0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7-4 bit 3 Unimplemented: Read as `0' WRT3: Write Protection bit 1 = Block 3 is not write-protected(1) 0 = Block 3 is write-protected(1) WRT2: Write Protection bit 1 = Block 2 is not write-protected(1) 0 = Block 2 is write-protected(1) WRT1: Write Protection bit 1 = Block 1 is not write-protected(1) 0 = Block 1 is write-protected(1) WRT0: Write Protection bit 1 = Block 0 is not write-protected(1) 0 = Block 0 is write-protected(1) bit 2 bit 1 bit 0 Note 1: For the memory size of the blocks, see Figure 28-6. 2011 Microchip Technology Inc. Preliminary DS39977C-page 471 PIC18F66K80 FAMILY REGISTER 28-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 WRTD bit 7 Legend: R/C-1 WRTB R-1 WRTC(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected WRTB: Boot Block Write Protection bit 1 = Boot block is not write-protected(2) 0 = Boot block is write-protected(2) WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers are not write-protected(2) 0 = Configuration registers are write-protected(2) Unimplemented: Read as `0' bit 6 bit 5 bit 4-0 Note 1: 2: This bit is read-only in normal execution mode; it can be written only in Program mode. For the memory size of the blocks, see Figure 28-6. DS39977C-page 472 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 -- bit 7 Legend: U-0 -- U-0 -- U-0 -- R/C-1 EBTR3 R/C-1 EBTR2 R/C-1 EBTR1 R/C-1 EBTR0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7-4 bit 3 Unimplemented: Read as `0' EBTR3: Table Read Protection bit 1 = Block 3 is not protected from table reads executed in other blocks(1) 0 = Block 3 is protected from table reads executed in other blocks(1) EBTR2: Table Read Protection bit 1 = Block 2 is not protected from table reads executed in other blocks(1) 0 = Block 2 is protected from table reads executed in other blocks(1) EBTR1: Table Read Protection bit 1 = Block 1 is not protected from table reads executed in other blocks(1) 0 = Block 1 is protected from table reads executed in other blocks(1) EBTR0: Table Read Protection bit 1 = Block 0 is not protected from table reads executed in other blocks(1) 0 = Block 0 is protected from table reads executed in other blocks(1) bit 2 bit 1 bit 0 Note 1: For the memory size of the blocks, see Figure 28-6. 2011 Microchip Technology Inc. Preliminary DS39977C-page 473 PIC18F66K80 FAMILY REGISTER 28-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 -- bit 7 Legend: R/C-1 EBTRB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R = Readable bit -n = Value at POR bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Boot Block Table Read Protection bit 1 = Boot block is not protected from table reads executed in other blocks(1) 0 = Boot block is protected from table reads executed in other blocks(1) Unimplemented: Read as `0' bit 5-0 Note 1: For the memory size of the blocks, see Figure 28-6. DS39977C-page 474 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY REGISTER 28-13: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F66K80 FAMILY R DEV2 bit 7 Legend: R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0 R = Readable bit -n = Value at POR bit 7-5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DEV<2:0>: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number: 000 = PIC18F46K80, PIC18LF26K80 001 = PIC18F26K80, PIC18LF65K80 010 = PIC18F65K80, PIC18LF45K80 011 = PIC18F45K80, PIC18LF25K80 100 = PIC18F25K80 110 = PIC18LF66K80 111 = PIC18F66K80, PIC18LF46K80 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. bit 4-0 REGISTER 28-14: DEVID2: DEVICE ID REGISTER 2 FOR THE PIC18F66K80 FAMILY R DEV10(1) bit 7 Legend: R DEV9(1) R DEV8(1) R DEV7(1) R DEV6(1) R DEV5(1) R DEV4(1) R DEV3(1) bit 0 R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence. 2011 Microchip Technology Inc. Preliminary DS39977C-page 475 PIC18F66K80 FAMILY 28.2 Watchdog Timer (WDT) For the PIC18F66K80 family of devices, the WDT is driven by the LF-INTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LF-INTOSC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 4,194 seconds (about one hour). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. The WDT can be operated in one of four modes as determined by WDTEN<1:0> (CONFIG2H<1:0>. The four modes are: * WDT Enabled * WDT Disabled * WDT under Software Control, SWDTEN (WDTCON<0>) * WDT - Enabled during normal operation - Disabled during Sleep Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 28-1: WDT BLOCK DIAGRAM WDT Enabled, SWDTEN Disabled WDT Controlled with SWDTEN bit Setting WDT Enabled only while Device Active, Disabled WDT Disabled in Hardware, SWDTEN Disabled WDTEN1 WDTEN0 INTOSC Source Change on IRCF bits CLRWDT Enable WDT WDT Counter 128 Wake-up from Power-Manage Modes Programmable Postscaler Reset 1:1 to 1:1,048,576 4 WDT Reset All Device Resets WDTPS<3:0> Sleep SWDTEN WDTEN<1:0> INTOSC Source Enable WDT DS39977C-page 476 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 28.2.1 CONTROL REGISTER Register 28-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT Enable Configuration bit, but only if the Configuration bit has disabled the WDT. REGISTER 28-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER R/W-0 REGSLP(3) bit 7 Legend: U-0 -- R-x ULPLVL R/W-0 SRETEN(2) U-0 -- R/W-x ULPEN R/W-x ULPSINK R/W-0 SWDTEN(1) bit 0 R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGSLP: Regulator Voltage Sleep Enable bit(3) 1 = Regulator goes into Low-Power mode when device's Sleep mode is enabled 0 = Regulator stays in normal mode when device's Sleep mode is activated Unimplemented: Read as `0' ULPLVL: Ultra Low-Power Wake-up Output bit Not valid unless ULPEN = 1. 1 = Voltage on RA0 pin > ~ 0.5V 0 = Voltage on RA0 pin < ~ 0.5V. SRETEN: Regulator Voltage Sleep Disable bit(2) 1 = If RETEN (CONFIG1L<0>) = 0 and the regulator is enabled, the device goes into Ultra Low-Power mode in Sleep 0 = The regulator is on when device's Sleep mode is enabled and the Low-Power mode is controlled by REGSLP Unimplemented: Read as `0' ULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = Ultra low-power wake-up module is enabled; ULPLVL bit indicates comparator output 0 = Ultra low-power wake-up module is disabled ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit Not valid unless ULPEN = 1. 1 = Ultra low-power wake-up current sink is enabled 0 = Ultra low-power wake-up current sink is disabled SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled. This bit is available only when RETEN = 0. This bit is disabled on PIC18LF devices. TABLE 28-2: Name SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCON WDTCON Legend: IPEN REGSLP SBOREN -- CM ULPLVL RI SRETEN TO -- PD ULPEN POR ULPSINK BOR SWDTEN -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. 2011 Microchip Technology Inc. Preliminary DS39977C-page 477 PIC18F66K80 FAMILY 28.3 On-Chip Voltage Regulator FIGURE 28-2: 5V(1) PIC18F66K80 All of the PIC18F66K80 family devices power their core digital logic at a nominal 3.3V. For designs that are required to operate at a higher typical voltage, such as 5V, all family devices incorporate two on-chip regulators that allows the device to run its core logic from VDD. Those regulators are: * Normal on-chip regulator * Ultra Low-Power, on-chip regulator The hardware configuration of these regulators are the same and are explained in Section 28.3.1. The regulators' only differences relate to when the device enters Sleep, as explained in Section 28.3.3. CF CONNECTIONS FOR THE F AND LF PARTS VDD VDDCORE/VCAP VSS 3.3V(1) PIC18LF66K80 28.3.1 REGULATOR ENABLE MODE (PIC18FXXKXX DEVICES) VDD On PIC18FXXKXX devices, the regulator is enabled and a low-ESR filter capacitor must be connected to the VDDCORE/VCAP pin (see Figure 28-2). This helps maintain the regulator's stability. The recommended value for the filter capacitor is given in Section 31.1 DC Characteristics. VDDCORE/VCAP (2) 0.1 F Capacitor VSS 28.3.2 REGULATOR DISABLE MODE (PIC18LFXXKXX DEVICES) Note 1: On PIC18LFXXKXX devices, the regulator is disabled and the power to the core is supplied directly by VDD. The voltage levels for VDD must not exceed the specified VDDCORE levels. A 0.1 F capacitor should be connected to the VDDCORE/VCAP pin. On the PIC18FXXKXX devices, the overall voltage budget is very tight. The regulator should operate the device down to 1.8V. When VDD drops below 3.3V, the regulator no longer regulates, but the output voltage follows the input until VDD reaches 1.8V. Below this voltage, the output of the regulator output may drop to 0V. 2: These are typical operating voltages. For the full operating ranges of VDD and VDDCORE, see Section 31.1 DC Characteristics. When the regulator is disabled, VDDCORE/VCAP must be connected to a 0.1 F capacitor. DS39977C-page 478 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 28.3.3 OPERATION OF REGULATOR IN SLEEP The various modes of regulator operation are shown in Table 28-3. When the ultra low-power regulator is in Sleep mode, the internal reference voltages in the chip will be shut off and any interrupts referring to the internal reference will not wake up the device. If the BOR or LVD is enabled, the regulator will keep the internal references on and the lowest possible current will not be achieved. When using the ultra low-power regulator in Sleep mode, the device will take about 250 s to start executing code after it wakes up. The difference in the two regulators' operation arises with Sleep mode. The ultra low-power regulator gives the device the lowest current in the Regulator Enabled mode. The on-chip regulator can go into a lower power mode when the device goes to Sleep by setting the REGSLP bit (WDTCON<7>). This puts the regulator in a standby mode so that the device consumes much less current. The on-chip regulator can also go into the Ultra LowPower mode, which consumes the lowest current possible with the regulator enabled. This mode is controlled by the RETEN bit (CONFIG1L<0>) and SRETEN bit (WDTCON<4>). TABLE 28-3: Device SLEEP MODE REGULATOR SETTINGS(1) Power Mode REGSLP WDTCON<7> 0 1 0 1 x x x SRETEN WDTCON<4> x x 0 0 1 RETEN CONFIG1L<0> 1 1 0 0 0 0 1 PIC18FXXK80 PIC18FXXK80 PIC18FXXK80 PIC18FXXK80 PIC18FXXK80 PIC18LFXXK80 PIC18LFXXK80 Note 1: 2: Normal Operation (Sleep) Low-Power mode (Sleep) Normal Operation (Sleep) Low-Power mode (Sleep) Ultra Low-Power mode (Sleep) Reserved(2) Regulator Bypass mode (Sleep)(2) Don't Care x x -- Indicates that VIT status is invalid. The Ultra Low-Power regulator should be disabled (RETEN = 1, ULP disabled) on PIC18LFXXK80 devices to obtain the lowest possible Sleep current. 2011 Microchip Technology Inc. Preliminary DS39977C-page 479 PIC18F66K80 FAMILY 28.4 Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTOSC (LF-INTOSC, MF-INTOSC, HF-INTOSC) oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. Two-Speed Start-up should be enabled only if the primary oscillator mode is LP, XT or HS (Crystal-Based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up should be disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF<2:0>, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:0> bits prior to entering Sleep mode. In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. 28.4.1 SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP While using the INTOSC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power-managed modes, including multiple SLEEP instructions (refer to Section 4.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS<1:0> bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. FIGURE 28-3: INTOSC Multiplexer OSC1 TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 TOST(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter PC TPLL(1) 1 2 n-1 n Clock Transition(2) PC + 2 OSTS bit Set PC + 4 PC + 6 Wake from Interrupt Event Note 1: 2: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC. DS39977C-page 480 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 28.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the LF-INTOSC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 28-4) is accomplished by creating a sample clock signal, which is the output from the LF-INTOSC divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor (CM) latch. The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF<2:0>, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF<2:0> bits prior to entering Sleep mode. The FSCM will detect only failures of the primary or secondary clock sources. If the internal oscillator block fails, no failure would be detected nor would any action be possible. 28.5.1 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTOSC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTOSC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. FIGURE 28-4: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock S Q INTOSC Source / 64 488 Hz (2.048 ms) C Q (32 s) 28.5.2 EXITING FAIL-SAFE OPERATION Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 28-5). This causes the following: * The FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>) * The device clock source switches to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition) * The WDT is reset During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 4.1.4 "Multiple Sleep Commands" and Section 28.4.1 "Special Considerations for Using Two-Speed Start-up" for more details. The Fail-Safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as the OST or PLL timer). The INTOSC multiplexer provides the device clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power-managed mode is entered. 2011 Microchip Technology Inc. Preliminary DS39977C-page 481 PIC18F66K80 FAMILY FIGURE 28-5: Sample Clock Device Clock Output CM Output (Q) OSCFIF Oscillator Failure FSCM TIMING DIAGRAM Failure Detected CM Test Note: CM Test CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 28.5.3 FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Clock Monitoring of the power-managed clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (when the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTOSC returns to its role as the FSCM source. Note: 28.5.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is EC, RC or INTOSC modes, monitoring can begin immediately following these events. The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, also prevents the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 28.4.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new powermanaged mode is selected, the primary clock is disabled. DS39977C-page 482 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 28.6 Program Verification and Code Protection Each of the blocks has three code protection bits associated with them. They are: * Code-Protect bit (CPx) * Write-Protect bit (WRTx) * External Block Table Read bit (EBTRx) Figure 28-6 shows the program memory organization for 48, 64, 96 and 128 Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 28-4. The user program memory is divided into four blocks. One of these is a boot block of 1 or 2 Kbytes. The remainder of the memory is divided into blocks on binary boundaries. FIGURE 28-6: 000000h 01FFFFh CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F66K80 FAMILY Code Memory Device/Memory Size(1) PIC18FX6K80 PIC18FX5K80 Address BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Unimplemented Read as `0' Boot Block Boot Block Boot Block Boot Block 2 kW 2 kW Block 0 Block 0 7 kW 3 kW Block 0 Block 0 6 kW 2 kW Block 1 4 kW Block 1 8 kW Block 1 8 kW Block 2 4 kW Block 3 4 kW Block 2 8 kW Block 3 8 kW Block 2 8 kW Block 3 8 kW Block 1 4 kW Block 2 4 kW Block 3 4 kW 0000h 0800h 1000h 1FFFh 2000h 3FFFh 4000h 5FFFh 6000h 7FFFh 8000h BFFFh C000h FFFFh 10000h 13FFFh 14000h 17FFFh 18000h 1BFFFh 1C000h 1FFFFh 200000h Configuration and ID Space 3FFFFFh Note 1: 2: Sizes of memory areas are not to scale. Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>). 2011 Microchip Technology Inc. Preliminary DS39977C-page 483 PIC18F66K80 FAMILY TABLE 28-4: File Name SUMMARY OF CODE PROTECTION REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L 300009h CONFIG5H 30000Ah CONFIG6L 30000Bh CONFIG6H 30000Ch CONFIG7L 30000Dh CONFIG7H -- CPD -- WRTD -- -- -- CPB -- WRTB -- EBTRB -- -- -- WRTC -- -- -- -- -- -- -- -- CP3 -- WRT3 -- EBTR3 -- CP2 -- WRT2 -- EBTR2 -- CP1 -- WRT1 -- EBTR1 -- CP0 -- WRT0 -- EBTR0 -- Legend: Shaded cells are unimplemented. 28.6.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to, or written from, any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPx bits have no direct effect. CPx bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTx Configuration bit is `0'. The EBTRx bits control table reads. For a block of user memory with the EBTRx bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures 28-7 through 28-9 illustrate table write and table read protection. Note: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. Refer to the device programming specification for more information. FIGURE 28-7: TABLE WRITE (WRTx) DISALLOWED Program Memory Configuration Bit Settings Register Values 000000h 0007FFh 000800h TBLPTR = 0008FFh PC = 003FFEh 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh TBLWT* WRTB, EBTRB = 11 WRT0, EBTR0 = 01 TBLWT* WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes are disabled to Blockn whenever WRTx = 0. DS39977C-page 484 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 28-8: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Program Memory Configuration Bit Settings Register Values 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh WRT2, EBTR2 = 11 Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. The TABLAT register returns a value of `0'. FIGURE 28-9: EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED Program Memory Configuration Bit Settings Register Values 000000h 0007FFh 000800h TBLPTR = 0008FFh PC = 003FFEh TBLRD* WRTB, EBTRB = 11 WRT0, EBTR0 = 10 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Blockn, even when EBTRBx = 0. The TABLAT register returns the value of the data at the location, TBLPTR. 2011 Microchip Technology Inc. Preliminary DS39977C-page 485 PIC18F66K80 FAMILY 28.6.2 DATA EEPROM CODE PROTECTION 28.8 In-Circuit Serial Programming The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 28.6.3 CONFIGURATION REGISTER PROTECTION The PIC18F66K80 family of devices can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For the various programming modes, see the programming specification The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 28.9 In-Circuit Debugger 28.7 ID Locations Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program/verify. The ID locations can be read when the device is code-protected. When the DEBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 28-5 shows which resources are required by the background debugger. TABLE 28-5: I/O Pins: Stack: DEBUGGER RESOURCES RB6, RB7 Two levels 512 bytes 10 bytes Program Memory: Data Memory: To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/RE3, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third-party development tool companies. DS39977C-page 486 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 29.0 INSTRUCTION SET SUMMARY The PIC18F66K80 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 29-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 29-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 29.1.1 "Standard Instruction Set" provides a description of each instruction. 29.1 Standard Instruction Set The standard PIC18 MCU instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 29-2 lists byte-oriented, bit-oriented, literal and control operations. Table 29-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator, `f', specifies which file register is to be used by the instruction. The destination designator, `d', specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The bit field designator, `b', selects the number of the bit affected by the operation, while the file register designator, `f', represents the number of the file in which the bit is located. 2011 Microchip Technology Inc. Preliminary DS39977C-page 487 PIC18F66K80 FAMILY TABLE 29-1: Field a OPCODE FIELD DESCRIPTIONS Description bbb BSR C, DC, Z, OV, N d dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr] RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. Destination select bit: d = 0: store result in WREG d = 1: store result in file register f Destination: either the WREG register or the specified register file location. 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). 12-bit register file address (000h to FFFh). This is the source address. 12-bit register file address (000h to FFFh). This is the destination address. Global Interrupt Enable bit. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: No Change to register (such as TBLPTR with table reads and writes) Post-Increment register (such as TBLPTR with table reads and writes) Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Power-Down bit. Product of Multiply High Byte. Product of Multiply Low Byte. Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) 21-bit Table Pointer (points to a Program Memory location). 8-bit Table Latch. Time-out bit. Top-of-Stack. Unused or Unchanged. Watchdog Timer. Working register (accumulator). Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 7-bit offset value for Indirect Addressing of register files (source). 7-bit offset value for Indirect Addressing of register files (destination). Optional argument. Indicates an Indexed Address. The contents of text. Specifies bit n of the register indicated by the pointer expr. Assigned to. Register bit field. In the set of. User-defined term (font is Courier New). DS39977C-page 488 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 OPCODE 10 d 9 87 a f (FILE #) 0 ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 15 1111 12 11 f (Source FILE #) 12 11 f (Destination FILE #) 0 MOVFF MYREG1, MYREG2 OPCODE 0 f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B OPCODE b (BIT #) a b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE 8 7 k (literal) 0 MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 87 n<7:0> (literal) 12 11 n<19:8> (literal) 0 GOTO Label 0 n = 20-bit immediate value 15 OPCODE 15 1111 87 S n<7:0> (literal) 12 11 n<19:8> (literal) S = Fast bit 0 CALL MYFUNC 0 15 OPCODE 15 11 10 n<10:0> (literal) 87 OPCODE n<7:0> (literal) 0 BRA MYFUNC 0 BC MYFUNC 2011 Microchip Technology Inc. Preliminary DS39977C-page 489 PIC18F66K80 FAMILY TABLE 29-2: Mnemonic, Operands PIC18F66K80 FAMILY INSTRUCTION SET 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF f, d, a SUBWFB f, d, a SWAPF TSTFSZ XORWF Note 1: f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f, Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 None 1, 2 None C, DC, Z, OV, N 1, 2 C, Z, N Z, N C, Z, N Z, N 1, 2 None C, DC, Z, OV, N 0101 11da 0101 10da ffff C, DC, Z, OV, N 1, 2 ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N 1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da 4 1, 2 2: 3: 4: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39977C-page 490 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 29-2: Mnemonic, Operands PIC18F66K80 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL f, b, a f, b, a f, b, a f, b, a f, b, a n n n n n n n n n n, s Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call Subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to Address 1st word 2nd word No Operation No Operation Pop Top of Return Stack (TOS) Push Top of Return Stack (TOS) Relative Call Software Device Reset Return from Interrupt Enable Return with Literal in WREG Return from Subroutine Go into Standby mode 1 1 1 (2 or 3) 1 (2 or 3) 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1001 1000 1011 1010 0111 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 bbba bbba bbba bbba bbba 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None None None None None None TO, PD C None 1, 2 1, 2 3, 4 3, 4 1, 2 CONTROL OPERATIONS CLRWDT -- -- DAW n GOTO NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n s k RETLW RETURN s -- SLEEP Note 1: 0000 1100 0000 0000 0000 0000 None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 2: 3: 4: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 2011 Microchip Technology Inc. Preliminary DS39977C-page 491 PIC18F66K80 FAMILY TABLE 29-2: Mnemonic, Operands LITERAL OPERATIONS PIC18F66K80 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: k k k f, k k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 1010 1011 1100 1101 1110 1111 C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None DATA MEMORY PROGRAM MEMORY OPERATIONS 2 Table Read Table Read with Post-Increment Table Read with Post-Decrement Table Read with Pre-Increment 2 Table Write Table Write with Post-Increment Table Write with Post-Decrement Table Write with Pre-Increment 2: 3: 4: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39977C-page 492 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 29.1.1 ADDLW STANDARD INSTRUCTION SET ADD Literal to W ADDWF ADD W to f Syntax: Operands: Operation: Status Affected: Encoding: Description: ADDLW k Syntax: Operands: ADDWF 0 f 255 d [0,1] a [0,1] f {,d {,a}} 0 k 255 (W) + k W N, OV, C, DC, Z 0000 1111 kkkk kkkk Operation: Status Affected: Encoding: Description: (W) + (f) dest N, OV, C, DC, Z 0010 01da ffff ffff The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1 Q2 Read literal `k' ADDLW Words: Cycles: Q Cycle Activity: Q1 Decode Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q3 Process Data 15h Q4 Write to W Example: Before Instruction W = 10h After Instruction W= 25h Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' ADDWF Q3 Process Data REG, 0, 0 Q4 Write to destination Example: Before Instruction W = REG = After Instruction W = REG = 17h 0C2h 0D9h 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). 2011 Microchip Technology Inc. Preliminary DS39977C-page 493 PIC18F66K80 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: Operands: ADDWFC 0 f 255 d [0,1] a [0,1] f {,d {,a}} Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode ANDLW k 0 k 255 (W) .AND. k W N, Z 0000 1011 kkkk kkkk Operation: Status Affected: Encoding: Description: (W) + (f) + (C) dest N,OV, C, DC, Z 0010 00da ffff ffff The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2 Read literal `k' ANDLW Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q3 Process Data 05Fh Q4 Write to W Example: Before Instruction W = After Instruction W = A3h 03h Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' ADDWFC 1 02h 4Dh 0 02h 50h Q3 Process Data REG, 0, 1 Q4 Write to destination Example: Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W = DS39977C-page 494 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: Operands: ANDWF 0 f 255 d [0,1] a [0,1] f {,d {,a}} Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff BC n -128 n 127 if Carry bit is `1', (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn Operation: Status Affected: Encoding: Description: (W) .AND. (f) dest N, Z 0001 01da Description: The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode If the Carry bit is '1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' ANDWF Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BC 5 Q4 Write to PC No operation Q4 No operation Q3 Process Data REG, 0, 0 Q4 Write to destination Example: Example: Before Instruction W = REG = After Instruction W = REG = 17h C2h 02h C2h Before Instruction PC After Instruction If Carry PC If Carry PC = = = = = address (HERE) 1; address (HERE + 12) 0; address (HERE + 2) 2011 Microchip Technology Inc. Preliminary DS39977C-page 495 PIC18F66K80 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: Operands: BCF f, b {,a} Syntax: Operands: Operation: Status Affected: Encoding: BN n 0 f 255 0b7 a [0,1] 0 f None 1001 bbba ffff ffff -128 n 127 if Negative bit is `1', (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn Operation: Status Affected: Encoding: Description: Description: Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If the Negative bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' BCF Q3 Process Data FLAG_REG, Q4 Write register `f' 7, 0 Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BN Jump Q4 Write to PC No operation Q4 No operation Example: Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h Example: Before Instruction PC After Instruction If Negative PC If Negative PC = = = = = address (HERE) 1; address (Jump) 0; address (HERE + 2) DS39977C-page 496 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: Operands: Operation: Status Affected: Encoding: Description: BNC n Syntax: Operands: Operation: Status Affected: 0011 nnnn nnnn BNN n -128 n 127 if Carry bit is `0', (PC) + 2 + 2n PC None 1110 -128 n 127 if Negative bit is `0', (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn Encoding: Description: If the Carry bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If the Negative bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BNC Jump Q4 Write to PC No operation Q4 No operation Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BNN Jump Q4 Write to PC No operation Q4 No operation Example: Example: Before Instruction PC After Instruction If Carry PC If Carry PC = = = = = address (HERE) 0; address (Jump) 1; address (HERE + 2) Before Instruction PC After Instruction If Negative PC If Negative PC = = = = = address (HERE) 0; address (Jump) 1; address (HERE + 2) 2011 Microchip Technology Inc. Preliminary DS39977C-page 497 PIC18F66K80 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: Operands: Operation: Status Affected: Encoding: Description: BNOV n Syntax: Operands: Operation: Status Affected: 0101 nnnn nnnn BNZ n -128 n 127 if Overflow bit is `0', (PC) + 2 + 2n PC None 1110 -128 n 127 if Zero bit is `0', (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn Encoding: Description: If the Overflow bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If the Zero bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BNOV Jump Q4 Write to PC No operation Q4 No operation Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BNZ Jump Q4 Write to PC No operation Q4 No operation Example: Example: Before Instruction PC After Instruction If Overflow PC If Overflow PC = = = = = address (HERE) 0; address (Jump) 1; address (HERE + 2) Before Instruction PC After Instruction If Zero PC If Zero PC = = = = = address (HERE) 0; address (Jump) 1; address (HERE + 2) DS39977C-page 498 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: Operands: Operation: Status Affected: Encoding: Description: BRA n Syntax: Operands: BSF f, b {,a} -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn 0 f 255 0b7 a [0,1] 1 f Operation: Status Affected: Encoding: Description: Add the 2's complement number, `2n', to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC No operation None 1000 bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode No operation Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' BSF Example: HERE BRA Jump Before Instruction PC After Instruction PC = = address (HERE) address (Jump) Q3 Process Data Q4 Write register `f' Example: FLAG_REG, 7, 1 Before Instruction FLAG_REG After Instruction FLAG_REG = = 0Ah 8Ah 2011 Microchip Technology Inc. Preliminary DS39977C-page 499 PIC18F66K80 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: Operands: BTFSC f, b {,a} 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff Syntax: Operands: BTFSS f, b {,a} 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE FALSE TRUE BTFSC : : Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE FALSE TRUE BTFSS : : FLAG, 1, 0 FLAG, 1, 0 Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC = = = = = address (HERE) 0; address (TRUE) 1; address (FALSE) Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC = = = = = address (HERE) 0; address (FALSE) 1; address (TRUE) DS39977C-page 500 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: Operands: BTG f, b {,a} 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff Syntax: Operands: Operation: Status Affected: Encoding: Description: BOV n -128 n 127 if Overflow bit is `1', (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn Operation: Status Affected: Encoding: Description: Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If the Overflow bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' BTG Q3 Process Data PORTC, 4, 0 Q4 Write register `f' Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BOV Jump Q4 Write to PC No operation Q4 No operation Example: Before Instruction: 0111 0101 [75h] PORTC = After Instruction: PORTC = 0110 0101 [65h] Example: Before Instruction PC After Instruction If Overflow PC If Overflow PC = = = = = address (HERE) 1; address (Jump) 0; address (HERE + 2) 2011 Microchip Technology Inc. Preliminary DS39977C-page 501 PIC18F66K80 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: Operands: Operation: Status Affected: Encoding: Description: BZ n Syntax: Operands: Operation: CALL k {,s} 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>; if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 -128 n 127 if Zero bit is `1', (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE Q3 Process Data No operation Q3 Process Data BZ Jump Q4 Write to PC No operation Q4 No operation Subroutine call of entire 2-Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Read literal `k'<7:0>, No operation HERE Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Push PC to stack No operation CALL Example: Before Instruction PC After Instruction If Zero PC If Zero PC No operation Example: Q4 Read literal 'k'<19:8>, Write to PC No operation = = = = = address (HERE) 1; address (Jump) 0; address (HERE + 2) THERE,1 Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS = address (HERE) address (THERE) address (HERE + 4) W BSR STATUS DS39977C-page 502 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: Operands: Operation: Status Affected: Encoding: Description: CLRF f {,a} Syntax: Operands: Operation: CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. 0 f 255 a [0,1] 000h f, 1Z Z 0110 101a ffff ffff Status Affected: Encoding: Description: Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 No operation CLRWDT Q3 Process Data Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' CLRF Example: Q3 Process Data FLAG_REG,1 Q4 Write register `f' Example: Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD = = = = = ? 00h 0 1 1 Before Instruction FLAG_REG After Instruction FLAG_REG = = 5Ah 00h 2011 Microchip Technology Inc. Preliminary DS39977C-page 503 PIC18F66K80 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: Operands: COMF f {,d {,a}} Syntax: Operands: Operation: CPFSEQ 0 f 255 a [0,1] f {,a} 0 f 255 d [0,1] a [0,1] f dest N, Z 0001 11da ffff ffff Operation: Status Affected: Encoding: Description: (f) - (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff Status Affected: Encoding: Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' COMF Q3 Process Data REG, 0, 0 Q4 Write to destination Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation Example: Before Instruction REG = After Instruction REG = W = 13h 13h ECh Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL CPFSEQ REG, 0 : : HERE ? ? Before Instruction PC Address W REG After Instruction If REG PC If REG PC = = = = = = W; Address (EQUAL) W; Address (NEQUAL) DS39977C-page 504 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: Operands: Operation: CPFSGT 0 f 255 a [0,1] f {,a} Syntax: Operands: Operation: CPFSLT 0 f 255 a [0,1] f {,a} (f) -W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff (f) -W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff Status Affected: Encoding: Description: Status Affected: Encoding: Description: Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation Q Cycle Activity: Q1 Decode If skip: Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NGREATER GREATER Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NLESS LESS CPFSLT REG, 1 : : CPFSGT REG, 0 : : Before Instruction PC W After Instruction If REG PC If REG PC = = = = Address (HERE) ? W; Address (GREATER) W; Address (NGREATER) Before Instruction PC W After Instruction If REG PC If REG PC = = < = = Address (HERE) ? W; Address (LESS) W; Address (NLESS) 2011 Microchip Technology Inc. Preliminary DS39977C-page 505 PIC18F66K80 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: Operands: Operation: DAW None If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>; C =1 else (W<7:4>) W<7:4> Syntax: Operands: DECF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z 0000 01da ffff ffff Operation: Status Affected: Encoding: Description: Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Status Affected: Encoding: Description: C 0000 0000 0000 0111 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Words: Q2 Read register W DAW 1 1 Q2 Read register `f' DECF Q3 Process Data Q4 Write W Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = DC = After Instruction W = C = DC = Example 2: Before Instruction W = C = DC = After Instruction W = C = DC = Q3 Process Data CNT, 1, 0 Q4 Write to destination A5h 0 0 05h 1 0 Example: Before Instruction CNT = Z = After Instruction CNT = Z = 01h 0 00h 1 CEh 0 0 34h 1 0 DS39977C-page 506 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: Operands: DECFSZ f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff Syntax: Operands: DCFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 Write to destination Q4 No operation Q4 No operation No operation CNT, 1, 1 LOOP Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 Write to destination Q4 No operation Q4 No operation No operation Q Cycle Activity: Q1 Decode If skip: Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE CONTINUE DECFSZ GOTO Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE ZERO NZERO DCFSNZ : : TEMP, 1, 0 Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC = = = = = ? TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) 2011 Microchip Technology Inc. Preliminary DS39977C-page 507 PIC18F66K80 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Syntax: Operands: INCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z 0010 10da ffff ffff Operation: Status Affected: Encoding: Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 2 2 Q2 Read literal `k'<7:0>, No operation Q3 No operation No operation Q4 Read literal `k'<19:8>, Write to PC No operation No operation Example: Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' INCF GOTO THERE After Instruction PC = Address (THERE) Q3 Process Data CNT, 1, 0 Q4 Write to destination Example: Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC = FFh 0 ? ? 00h 1 1 1 DS39977C-page 508 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: Operands: INCFSZ f {,d {,a}} Syntax: Operands: INFSNZ f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. (default) If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 Write to destination Q4 No operation Q4 No operation No operation CNT, 1, 0 Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 Write to destination Q4 No operation Q4 No operation No operation Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NZERO ZERO INCFSZ : : Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE ZERO NZERO INFSNZ REG, 1, 0 Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) 2011 Microchip Technology Inc. Preliminary DS39977C-page 509 PIC18F66K80 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: Operands: Operation: Status Affected: Encoding: Description: IORLW k 0 k 255 (W) .OR. k W N, Z 0000 1001 kkkk kkkk Syntax: Operands: IORWF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z 0001 00da ffff ffff Operation: Status Affected: Encoding: Description: The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. 1 1 Q2 Read literal `k' IORLW Words: Cycles: Q Cycle Activity: Q1 Decode Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q3 Process Data 35h Q4 Write to W Example: Before Instruction W = After Instruction W = 9Ah BFh Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' IORWF Q3 Process Data RESULT, 0, 1 Q4 Write to destination Example: Before Instruction RESULT = W = After Instruction RESULT = W = 13h 91h 13h 93h DS39977C-page 510 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY LFSR Load FSR MOVF Move f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode LFSR f, k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Syntax: Operands: MOVF f {,d {,a}} 0 f 255 d [0,1] a [0,1] f dest N, Z 0101 00da ffff ffff Operation: Status Affected: Encoding: Description: The 12-bit literal `k' is loaded into the file select register pointed to by `f'. 2 2 Q2 Read literal `k' MSB Q3 Process Data Q4 Write literal `k' MSB to FSRfH Write literal `k' to FSRfL The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Decode Read literal `k' LSB Process Data Example: After Instruction FSR2H FSR2L LFSR 2, 3ABh = = 03h ABh Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' MOVF Q3 Process Data REG, 0, 0 Q4 Write W Example: Before Instruction REG W After Instruction REG W = = = = 22h FFh 22h 22h 2011 Microchip Technology Inc. Preliminary DS39977C-page 511 PIC18F66K80 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd Syntax: Operands: Operation: Status Affected: Encoding: Description: MOVLW k 0 k 255 k BSR None 0000 0001 kkkk kkkk The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0' regardless of the value of k7:k4. 1 1 Q2 Read literal `k' MOVLB Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 5 Q4 Write literal `k' to BSR Example: The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register Words: Cycles: Q Cycle Activity: Q1 Decode 2 2 Q2 Read register `f' (src) No operation No dummy read MOVFF Before Instruction BSR Register = After Instruction BSR Register = 02h 05h Q3 Process Data No operation Q4 No operation Write register `f' (dest) Decode Example: REG1, REG2 Before Instruction REG1 REG2 After Instruction REG1 REG2 = = = = 33h 11h 33h 33h DS39977C-page 512 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode MOVLW k 0 k 255 kW None 0000 1110 kkkk kkkk Syntax: Operands: Operation: Status Affected: Encoding: Description: MOVWF 0 f 255 a [0,1] (W) f None 0110 f {,a} The eight-bit literal `k' is loaded into W. 1 1 Q2 Read literal `k' MOVLW 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q3 Process Data 5Ah Q4 Write to W Example: After Instruction W = 5Ah Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' MOVWF Q3 Process Data REG, 0 Q4 Write register `f' Example: Before Instruction W = REG = After Instruction W = REG = 4Fh FFh 4Fh 4Fh 2011 Microchip Technology Inc. Preliminary DS39977C-page 513 PIC18F66K80 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: Operands: Operation: Status Affected: Encoding: Description: MULLW k Syntax: Operands: Operation: MULWF 0 f 255 a [0,1] f {,a} 0 k 255 (W) x k PRODH:PRODL None 0000 1101 kkkk kkkk (W) x (f) PRODH:PRODL None 0000 001a ffff ffff Status Affected: Encoding: Description: An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read literal `k' Q3 Process Data Q4 Write registers PRODH: PRODL Example: Before Instruction W PRODH PRODL After Instruction W PRODH PRODL If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' Q3 Process Data Q4 Write registers PRODH: PRODL MULLW 0C4h = = = = = = E2h ? ? E2h ADh 08h Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL MULWF REG, 1 = = = = = = = = C4h B5h ? ? C4h B5h 8Ah 94h DS39977C-page 514 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY NEGF Negate f NOP No Operation Syntax: Operands: Operation: Status Affected: Encoding: Description: NEGF f {,a} Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff NOP None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx 0 f 255 a [0,1] (f) + 1 f N, OV, C, DC, Z 0110 110a Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Description: Words: Cycles: Q Cycle Activity: Q1 Decode No operation. 1 1 Q2 No operation Q3 No operation Q4 No operation Example: None. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' NEGF Q3 Process Data REG, 1 Q4 Write register `f' Example: Before Instruction REG = After Instruction REG = 0011 1010 [3Ah] 1100 0110 [C6h] 2011 Microchip Technology Inc. Preliminary DS39977C-page 515 PIC18F66K80 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: Operands: Operation: Status Affected: Encoding: Description: POP None (TOS) bit bucket None 0000 0000 0000 0110 Syntax: Operands: Operation: Status Affected: Encoding: Description: PUSH None (PC + 2) TOS None 0000 0000 0000 0101 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2 No operation POP GOTO The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1 Q2 PUSH PC + 2 onto return stack PUSH Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode Q3 POP TOS value Q4 No operation Q3 No operation Q4 No operation Example: Example: NEW Before Instruction TOS Stack (1 level down) After Instruction TOS PC = = = = 0031A2h 014332h 014332h NEW Before Instruction TOS PC After Instruction PC TOS Stack (1 level down) = = = = = 345Ah 0124h 0126h 0126h 345Ah DS39977C-page 516 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY RCALL Relative Call RESET Reset Syntax: Operands: Operation: Status Affected: Encoding: Description: RCALL n Syntax: Operands: Operation: Status Affected: 1nnn nnnn nnnn RESET None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q2 Read literal `n' PUSH PC to stack No operation HERE This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2 Start reset RESET Words: Cycles: Q Cycle Activity: Q1 Decode Q3 No operation Q4 No operation Example: Q3 Process Data Q4 Write to PC After Instruction Registers = Flags* = Reset Value Reset Value No operation Example: No operation RCALL Jump No operation Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) 2011 Microchip Technology Inc. Preliminary DS39977C-page 517 PIC18F66K80 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: Operands: Operation: RETFIE {s} s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged GIE/GIEH, PEIE/GIEL. 0000 0000 0001 000s Syntax: Operands: Operation: RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2 Read literal `k' No operation Q3 Process Data No operation Q4 POP PC from stack, write to W No operation Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode No operation Example: Q2 No operation Q3 No operation No operation Example: No operation RETFIE 1 No operation Q4 POP PC from stack Set GIEH or GIEL No operation After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL = = = = = TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value W = offset Begin table End of table Before Instruction W = After Instruction W = 07h value of kn DS39977C-page 518 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: Operands: Operation: RETURN {s} s [0,1] (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s Syntax: Operands: RLCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f 0011 01da ffff ffff Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2 No operation No operation Q3 Process Data No operation Q4 POP PC from stack No operation The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f Words: Cycles: Q Cycle Activity: Q1 Decode No operation Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' RLCF Example: RETURN After Instruction: PC = TOS Q3 Process Data Q4 Write to destination Example: Before Instruction REG = C = After Instruction REG = = W C = REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1 2011 Microchip Technology Inc. Preliminary DS39977C-page 519 PIC18F66K80 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: Operands: RLNCF 0 f 255 d [0,1] a [0,1] f {,d {,a}} Syntax: Operands: RRCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f 0011 00da ffff ffff Operation: Status Affected: Encoding: Description: (f 0100 01da ffff ffff Operation: Status Affected: Encoding: Description: The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' RLNCF Words: Q3 Process Data Q4 Write to destination Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' RRCF Example: Before Instruction REG = After Instruction REG = REG, 1, 0 Q3 Process Data REG, 0, 0 Q4 Write to destination 1010 1011 0101 0111 Example: Before Instruction REG = C = After Instruction REG = = W C = 1110 0110 0 1110 0110 0111 0011 0 DS39977C-page 520 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: Operands: RRNCF f {,d {,a}} Syntax: Operands: Operation: Status Affected: Encoding: ffff SETF f {,a} 0 f 255 d [0,1] a [0,1] (f 0100 00da ffff 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff Operation: Status Affected: Encoding: Description: Description: The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' SETF Q3 Process Data REG,1 Q4 Write register `f' Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' RRNCF Example: Q3 Process Data REG, 1, 0 Q4 Write to destination Before Instruction REG After Instruction REG = = 5Ah FFh Example 1: Before Instruction REG = After Instruction REG = Example 2: 1101 0111 1110 1011 REG, 0, 0 RRNCF Before Instruction W = REG = After Instruction W = REG = ? 1101 0111 1110 1011 1101 0111 2011 Microchip Technology Inc. Preliminary DS39977C-page 521 PIC18F66K80 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: Operands: Operation: SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 Syntax: Operands: SUBFWB 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: Status Affected: Encoding: Description: (W) - (f) - (C) dest N, OV, C, DC, Z 0101 01da ffff ffff Status Affected: Encoding: Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. The Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 No operation SLEEP Q3 Process Data Q4 Go to Sleep Words: Cycles: Q Cycle Activity: Q1 Decode Example: 1 1 Q2 Read register `f' Q3 Process Data Q4 Write to destination Before Instruction ? TO = PD = ? After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared. Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39977C-page 522 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z 0000 1000 kkkk kkkk Syntax: Operands: SUBWF 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: Status Affected: Encoding: Description: (f) - (W) dest N, OV, C, DC, Z 0101 11da ffff ffff W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1 Q2 Read literal `k' SUBLW Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q3 Process Data 02h Q4 Write to W 01h ? 01h 1 0 0 SUBLW ; result is positive Words: Cycles: 02h 1 1 Q2 Read register `f' Q3 Process Data REG, 1, 0 02h ? 00h 1 1 0 SUBLW Q Cycle Activity: Q1 Decode Q4 Write to destination ; result is zero 02h 03h ? FFh 0 0 1 ; (2's complement) ; result is negative SUBWF Example 1: Before Instruction REG = 3 W = 2 C = ? After Instruction REG = 1 W = 2 C = 1 Z = 0 N = 0 Example 2: SUBWF Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 Z = 1 N = 0 Example 3: SUBWF Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh W = 2 C = 0 Z = 0 N = 1 ; result is positive REG, 0, 0 ; result is zero REG, 1, 0 ;(2's complement) ; result is negative 2011 Microchip Technology Inc. Preliminary DS39977C-page 523 PIC18F66K80 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: Operands: SUBWFB 0 f 255 d [0,1] a [0,1] f {,d {,a}} Syntax: Operands: SWAPF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff Operation: Status Affected: Encoding: Description: (f) - (W) - (C) dest N, OV, C, DC, Z 0101 10da ffff ffff Operation: Status Affected: Encoding: Description: Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' Q3 Process Data Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' SWAPF Example 1: SUBWFB REG, 1, 0 Before Instruction REG = 19h (0001 1001) W = 0Dh (0000 1101) C = 1 After Instruction REG = 0Ch (0000 1011) W = 0Dh (0000 1101) C = 1 Z = 0 N = 0 ; result is positive SUBWFB REG, 0, 0 Example 2: Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero 0 N = Example 3: SUBWFB Before Instruction REG = 03h W = 0Eh C = 1 After Instruction REG = F5h W C Z N REG, 1, 0 (0000 0011) (0000 1101) Q3 Process Data REG, 1, 0 Q4 Write to destination Example: Before Instruction REG = After Instruction REG = 53h 35h = = = = 0Eh 0 0 1 (1111 0100) ; [2's comp] (0000 1101) ; result is negative DS39977C-page 524 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TBLRD Table Read TBLRD Table Read (Continued) TBLRD *+ ; Syntax: Operands: Operation: TBLRD ( *; *+; *-; +*) None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Example 1: Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: TBLRD = = = = = +* ; 55h 00A356h 34h 34h 00A357h Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* Before Instruction TABLAT TBLPTR MEMORY(01A357h) MEMORY(01A358h) After Instruction TABLAT TBLPTR = = = = = = AAh 01A357h 12h 34h 34h 01A358h Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0: Least Significant Byte of Program Memory Word TBLPTR<0> = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: Cycles: Q Cycle Activity: Q1 Decode No operation 1 2 Q2 No operation No operation (Read Program Memory) Q3 No operation No operation Q4 No operation No operation (Write TABLAT) 2011 Microchip Technology Inc. Preliminary DS39977C-page 525 PIC18F66K80 FAMILY TBLWT Table Write TBLWT Table Write (Continued) TBLWT *+; Syntax: Operands: Operation: TBLWT ( *; *+; *-; +*) None if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* Example 1: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: TBLWT +*; Status Affected: Encoding: Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 "Memory Organization" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h Words: Cycles: Q Cycle Activity: 1 2 Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register) DS39977C-page 526 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: Operands: Operation: Status Affected: Encoding: Description: TSTFSZ f {,a} 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff Syntax: Operands: Operation: Status Affected: Encoding: Description: XORLW k 0 k 255 (W) .XOR. k W N, Z 0000 1010 kkkk kkkk If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2 Read literal `k' XORLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0AFh Q4 Write to W Example: Before Instruction W = After Instruction W = B5h 1Ah Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NZERO ZERO TSTFSZ : : CNT, 1 Before Instruction PC After Instruction If CNT PC If CNT PC = = = = Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO) 2011 Microchip Technology Inc. Preliminary DS39977C-page 527 PIC18F66K80 FAMILY XORWF Exclusive OR W with f Syntax: Operands: XORWF 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: Status Affected: Encoding: Description: (W) .XOR. (f) dest N, Z 0001 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' XORWF Q3 Process Data REG, 1, 0 Q4 Write to destination Example: Before Instruction REG = W = After Instruction REG = W = AFh B5h 1Ah B5h DS39977C-page 528 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 29.2 Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, the PIC18F66K80 family of devices also provides an optional extension to the core CPU functionality. The added features include eight additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing for many of the standard PIC18 instructions. The additional features of the extended instruction set are enabled by default on unprogrammed devices. Users must properly set or clear the XINST Configuration bit during programming to enable or disable these features. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: * Dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * Manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 29-3. Detailed descriptions are provided in Section 29.2.2 "Extended Instruction Set". The opcode field descriptions in Table 29-1 (page 488) apply to both the standard and extended PIC18 instruction sets. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. 29.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. The MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 29.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). TABLE 29-3: Mnemonic, Operands EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Description Cycles MSb LSb 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk Status Affected ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k zs, fd zs, zd k f, k k Add Literal to FSR Add Literal to FSR2 and Return Call Subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store Literal at FSR2, Decrement FSR2 Subtract Literal from FSR Subtract Literal from FSR2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 None None None None None None None None 2011 Microchip Technology Inc. Preliminary DS39977C-page 529 PIC18F66K80 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk Syntax: Operands: Operation: Status Affected: Encoding: Description: kkkk ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk kkkk The 6-bit literal `k' is added to the contents of the FSR specified by `f'. 1 1 Q2 Read literal `k' Q3 Process Data Q4 Write to FSR The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 Q2 Read literal `k' No Operation Q3 Process Data No Operation Q4 Write to FSR No Operation Example: ADDFSR 2, 23h Before Instruction FSR2 = After Instruction FSR2 = 03FFh 0422h Words: Cycles: Q Cycle Activity: Q1 Decode No Operation Example: ADDULNK 23h Before Instruction FSR2 = PC = After Instruction FSR2 = PC = 03FFh 0100h 0422h (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39977C-page 530 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: Operands: Operation: CALLW None (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU None 0000 0000 0001 0100 Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: MOVSF [zs], fd 0 zs 127 0 fd 4095 ((FSR2) + zs) fd None 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd Status Affected: Encoding: Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR. The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs', in the first word, to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. Words: Cycles: Q Cycle Activity: Q1 Decode No operation 1 2 Q2 Read WREG No operation Q3 Push PC to stack No operation Q4 No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode Decode 2 2 Q2 Q3 Determine Determine source addr source addr No No operation operation No dummy read Q4 Read source reg Write register `f' (dest) Example: HERE CALLW Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h Example: MOVSF [05h], REG2 Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 = = = = = = 80h 33h 11h 80h 33h 33h 2011 Microchip Technology Inc. Preliminary DS39977C-page 531 PIC18F66K80 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (dest.) Description MOVSS [zs], [zd] 0 zs 127 0 zd 127 ((FSR2) + zs) ((FSR2) + zd) None 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd Syntax: Operands: Operation: Status Affected: Encoding: Description: PUSHL k 0k 255 k (FSR2), FSR2 - 1 FSR2 None 1111 1010 kkkk kkkk The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets, `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the resultant destination address points to an Indirect Addressing register, the instruction will execute as a NOP. The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read `k' Q3 Process data Q4 Write to destination Example: PUSHL 08h Before Instruction FSR2H:FSR2L Memory (01ECh) After Instruction FSR2H:FSR2L Memory (01ECh) = = = = 01ECh 00h 01EBh 08h Words: Cycles: Q Cycle Activity: Q1 Decode Decode 2 2 Q2 Q3 Determine Determine source addr source addr Determine Determine dest addr dest addr Q4 Read source reg Write to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h = = = = = = 80h 33h 11h 80h 33h 33h DS39977C-page 532 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: Operands: Operation: Status Affected: Encoding: Description: SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSRf - k FSRf None 1110 1001 Syntax: Operands: Operation: Status Affected: Encoding: Description: ffkk kkkk SUBULNK k 0 k 63 FSR2 - k FSR2, (TOS) PC None 1110 1001 11kk kkkk Words: Cycles: Q Cycle Activity: Q1 Decode The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. 1 1 Q2 Read register `f' Q3 Process Data Q4 Write to destination The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 Q2 Read register `f' No Operation Q3 Process Data No Operation Q4 Write to destination No Operation SUBFSR 2, 23h Example: Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh Words: Cycles: Q Cycle Activity: Q1 Decode No Operation SUBULNK 23h Example: Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) 2011 Microchip Technology Inc. Preliminary DS39977C-page 533 PIC18F66K80 FAMILY 29.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. 29.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands Note: In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0) or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward-compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 29.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. When the extended instruction set is enabled, the file register argument `f' in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within the brackets, will generate an error in the MPASMTM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled), when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument `d' functions as before. In the latest versions of the MPASM Assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 29.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F66K80 family, it is very important to consider the type of code. A large, re-entrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39977C-page 534 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: Operands: Operation: Status Affected: Encoding: Description: ADDWF 0 k 95 d [0,1] [k] {,d} Syntax: Operands: Operation: Status Affected: kkkk kkkk BSF [k], b 0 f 95 0b7 1 ((FSR2) + k) (W) + ((FSR2) + k) dest N, OV, C, DC, Z 0010 01d0 None 1000 bbb0 kkkk kkkk Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Bit `b' of the register indicated by FSR2, offset by the value `k', is set. 1 1 Q2 Read register `f' BSF Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read `k' Q3 Process Data [OFST] ,0 Q3 Process Data Q4 Write to destination Q4 Write to destination Example: [FLAG_OFST], 7 Example: ADDWF Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch = = = = = = 17h 2Ch 0A00h 20h 37h 20h Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah = = = = 0Ah 0A00h 55h D5h SETF Set Indexed (Indexed Literal Offset mode) Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode SETF [k] 0 k 95 FFh ((FSR2) + k) None 0110 1000 kkkk kkkk The contents of the register indicated by FSR2, offset by `k', are set to FFh. 1 1 Q2 Read `k' Q3 Process Data [OFST] Q4 Write register Example: SETF Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch = = = = 2Ch 0A00h 00h FFh 2011 Microchip Technology Inc. Preliminary DS39977C-page 535 PIC18F66K80 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS The latest versions of Microchip's software tools have been designed to fully support the extended instruction set for the PIC18F66K80 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. DS39977C-page 536 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 30.0 DEVELOPMENT SUPPORT 30.1 The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2011 Microchip Technology Inc. Preliminary DS39977C-page 537 PIC18F66K80 FAMILY 30.2 MPLAB C Compilers for Various Device Families 30.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 30.6 MPLAB Assembler, Linker and Librarian for Various Device Families 30.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS39977C-page 538 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 30.7 MPLAB SIM Software Simulator 30.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 30.8 MPLAB REAL ICE In-Circuit Emulator System 30.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2011 Microchip Technology Inc. Preliminary DS39977C-page 539 PIC18F66K80 FAMILY 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 30.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39977C-page 540 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on MCLR with respect to VSS.......................................................................................................... -0.3V to 9.0V Voltage on any digital only I/O pin with respect to VSS (except VDD)........................................................... -0.3V to 7.5V Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS (PIC18F66K80) .................................................................................. -0.3V to 7.5V Voltage on VDD with respect to VSS (PIC18LF66K80) .............................................................................. -0.3V to 3.66V Total power dissipation (Note 1) ..................................................................................................................................1W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .................................................................................................. 20 mA Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA Maximum output current sunk by any PORTD and PORTE I/O pins........................................................................8 mA Maximum output current sunk by PORTA<5:0> and any PORTF and PORTG I/O pins...........................................2 mA Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins .....................................................8 mA Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA Maximum current sunk byall ports combined.......................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2011 Microchip Technology Inc. Preliminary DS39977C-page 541 PIC18F66K80 FAMILY FIGURE 31-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL/EXTENDED)(1) 6V 5.5V 5V 4V 3V 1.8V 3V PIC18F66K80 Family Voltage (VDD) 0 4 MHz Frequency 64 MHz Note 1: For VDD values 1.8V to 3V, FMAX = (VDD - 1.72)/0.02 MHz. FIGURE 31-2: VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL/EXTENDED)(1,2) 4V 3.75V 3.25V PIC18LF66K80 Family 3.6V 3V Voltage (VDD) 2.5V 1.8V 4 MHz Frequency 64 MHz Note 1: 2: When the on-chip voltage regulator is disabled, VDD must be maintained so that VDD 3.6V. For VDD values 1.8V to 3V, FMAX = (VDD - 1.72)/0.02 MHz. DS39977C-page 542 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F66K80 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage Analog Supply Voltage RAM Data Retention Voltage(1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal Brown-out Reset Voltage (High, Medium and Low-Power mode BORV<1:0> = 11(2) BORV<1:0> = 10 BORV<1:0> = 01 BORV<1:0> = 00 Min Typ Max Units Conditions PIC18F66K80 Family (Industrial, Extended) Param Symbol No. D001 VDD 1.8 1.8 VDD - 0.3 1.5 -- -- -- -- -- -- -- 3.6 5.5 VDD + 0.3 VSS + 0.3 -- 0.7 V V V V V V For LF devices For F devices D001C AVDD D001D AVSS D002 D003 VDR VPOR Analog Ground Potential VSS - 0.3 See Section 5.3 "Power-on Reset (POR)" for details D004 SVDD 0.05 -- -- V/ms See Section 5.3 "Power-on Reset (POR)" for details D005 BVDD 1.69 1.88 2.53 2.82 1.8 2.0 2.7 3.0 1.91 2.12 2.86 3.18 V V V V Note 1: 2: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. Device will operate normally until Brown-out Reset occurs, even though VDD may be below VDDMIN. 2011 Microchip Technology Inc. Preliminary DS39977C-page 543 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Power-Down Current (IPD)(1) PIC18LFXXK80 8 13 35 218 3 400 500 750 980 6 500 600 850 1250 8 700 800 1050 1500 9 1000 1000 1100 1580 10 nA nA nA nA A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V (Sleep mode) Regulator Enabled VDD = 3.3V (Sleep mode) Regulator Enabled VDD = 3.3V (Sleep mode) Regulator Disabled VDD = 1.8V (Sleep mode) Regulator Disabled PIC18LFXXK80 14 34 92 312 4 nA nA nA nA A nA nA nA nA A nA nA nA nA A PIC18FXXK80 200 230 320 510 5 PIC18FXXK80 220 240 340 540 5 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 544 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LFXXK80 4 4 4 5 9 8 8 8 9 12 11 11 11 12 15 150 150 150 170 190 180 180 180 190 200 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 31 kHz (RC_RUN mode, LF-INTOSC) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 7 7 7 8 13 PIC18FXXK80 51 70 75 80 88 PIC18FXXK80 75 75 75 80 95 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 545 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 274 274 274 280 290 600 600 600 650 700 820 820 820 840 990 860 860 860 890 1060 910 910 910 970 1125 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 1 MHz (RC_RUN mode, HF-INTOSC) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 410 410 410 420 430 PIC18FXXK80 490 490 490 500 510 PIC18FXXK80 490 490 490 500 510 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 546 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 520 520 520 530 540 820 820 820 880 1000 1600 1600 1600 1610 1800 1640 1640 1640 1650 1900 2.2 2.2 2.2 2.2 2.2 A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 4 MHz (RC_RUN mode, HF-INTOSC) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 941 941 941 950 960 PIC18FXXK80 981 981 981 990 1000 PIC18FXXK80 1 1 1 1 1 mA mA mA mA mA Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 547 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 880 880 880 1 5 1600 1600 1600 2 10 5 5 5 6 12 130 130 130 150 175 160 160 160 170 180 nA nA nA A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 31 kHz (RC_IDLE mode, LF-INTOSC) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 1.6 1.6 1.6 2 7 PIC18FXXK80 41 59 64 70 80 PIC18FXXK80 53 62 70 85 100 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 548 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 260 260 260 270 280 380 380 380 390 420 500 500 500 520 580 560 560 560 580 620 620 620 620 640 680 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 1 MHz (RC_IDLE mode, HF-INTOSC) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 400 400 400 410 420 PIC18FXXK80 430 430 430 450 480 PIC18FXXK80 450 450 450 470 500 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 549 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 330 330 330 340 350 480 480 480 500 540 720 720 720 740 780 760 760 760 780 810 1250 1250 1250 1300 1340 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 4 MHz (RC_IDLE mode, Internal HF-INTOSC) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 522 522 522 540 550 PIC18FXXK80 540 540 540 560 580 PIC18FXXK80 600 600 600 610 620 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 550 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 90 90 90 100 110 260 260 260 270 300 540 540 540 560 600 560 560 560 580 620 740 740 740 840 940 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 1 MHZ (PRI_RUN mode, EC oscillator) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 163 163 163 170 180 PIC18FXXK80 201 217 224 228 236 PIC18FXXK80 240 240 240 250 260 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 551 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 270 270 270 300 320 600 600 600 700 850 1000 1000 1000 1100 1200 1020 1020 1020 1120 1220 2000 2000 2000 2000 2000 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 4 MHz (PRI_RUN mode, EC oscillator) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 540 540 540 550 560 PIC18FXXK80 566 585 590 595 600 PIC18FXXK80 630 630 630 640 650 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 552 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 7 7 7 7 7 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +60C +85C +125C -40C +60C +25C +85C +125C -40C +60C +25C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled FOSC = 64 MHZ (PRI_RUN mode, EC oscillator) VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 7 7 7 7 7 PIC18FXXK80 8 8 8 8 8 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 553 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 2 2 2 2 2 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled FOSC = 64 MHz VDD = 3.3V(5) (PRI_RUN mode, 16 MHz Regulator Enabled EC oscillator with PLL) VDD = 3.3V(4) VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled FOSC = 16 MHz (PRI_RUN mode, 4 MHz EC oscillator with PLL) VDD = 3.3V(4) PIC18FXXK80 2 2 2 2 2 PIC18FXXK80 2.2 2.2 2.2 2.2 2.2 PIC18LFXXK80 7 7 7 7 7 PIC18FXXK80 7 7 7 7 7 PIC18FXXK80 8 8 8 8 8 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 554 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 20 20 20 25 30 70 70 70 80 100 120 120 120 130 150 140 140 140 150 170 225 225 225 230 250 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator enabled VDD = 3.3V(5) Regulator enabled VDD = 3.3V(4) Regulator disabled FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 1.8V(4) Regulator disabled PIC18LFXXK80 37 37 37 40 45 PIC18FXXK80 85 100 105 110 120 PIC18FXXK80 110 110 110 120 130 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 555 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 75 75 75 76 82 160 160 160 170 180 300 300 300 400 460 320 320 320 420 480 500 500 500 600 700 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 148 148 148 150 157 PIC18FXXK80 187 204 212 218 230 PIC18FXXK80 230 230 230 240 250 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 556 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 2.3 2.3 2.3 2.3 2.3 4 4 4 5 5 4 4 4 5 5 5 5 5 6 6 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled FOSC = 64 MHz (PRI_IDLE mode, EC oscillator) VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 2.3 2.3 2.3 2.3 2.3 PIC18FXXK80 2.5 2.5 2.5 2.5 2.5 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 557 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 2 5 6 8 13 8 10 15 20 30 15 22 28 39 60 170 170 170 180 190 180 180 180 190 200 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 32 kHz(3) (SEC_RUN mode, SOSCSEL= 01) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 3 16 17 19 25 PIC18FXXK80 70 70 70 75 90 PIC18FXXK80 75 75 75 80 95 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS39977C-page 558 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 1.4 2.4 3.6 4.6 9.0 4 6 10 12 20 5 18 22 30 40 150 150 150 160 170 160 160 160 170 180 A A A A A A A A A A A A A A A A A A A A -40C +25C +60C +85C +125 -40C +25C +60C +85C +125 +25C +60C +85C +125C +25C -40C +25C +60C +85C +125C VDD = 5V(5) Regulator Enabled VDD = 3.3V(5) Regulator Enabled VDD = 3.3V(4) Regulator Disabled FOSC = 32 kHz(3) (SEC_IDLE mode, SOSCSEL= 01) VDD = 1.8V(4) Regulator Disabled PIC18LFXXK80 2 10 11 13 17 PIC18FXXK80 55 55 55 60 75 PIC18FXXK80 53 62 70 85 100 Legend: Note 1: 2: 3: 4: 5: Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. 2011 Microchip Technology Inc. Preliminary DS39977C-page 559 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device D022 IWDT) Module Differential Currents (IWDT, IOSCB, IAD) Watchdog Timer Legend: Note 1: 2: 3: 4: 5: 0.4 1 A -40C A +25C 0.4 1 VDD = 1.8V 0.5 1 A +60C Regulator Disabled 0.5 1 A +85C 0.5 2 A +125C PIC18LFXXK80 0.6 2 A -40C A +25C 0.6 2 VDD = 3.3V 0.7 2 A +60C Regulator Disabled 0.7 2 A +85C 1 3 A +125C PIC18FXXK80 0.6 2 A -40C 0.6 2 A +25C VDD = 3.3V 0.7 2 A +60C Regulator Enabled 0.7 2 A +85C 1 3 A +125C PIC18FXXK80 0.8 2 A -40C 0.8 2 A +25C VDD = 5V 0.9 2 A +60C Regulator Enabled 0.9 2 A +85C 1.5 4 A +125C Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. PIC18LFXXK80 DS39977C-page 560 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device Brown-out Reset D022A (IBOR) Legend: Note 1: 2: 3: 4: 5: 4.6 19 A -40C 4.5 20 A +25C VDD = 3.3V High-Power BOR 4.7 20 A +60C Regulator Disabled 4.7 20 A +85C 4.7 20 A +125C PIC18FXXK80 4.6 19 A -40C 4.6 20 A +25C VDD = 3.3V High-Power BOR 4.7 20 A +60C Regulator Enabled 4.7 20 A +85C 4.7 20 A +125C PIC18FXXK80 4.2 20 A -40C 4.3 20 A +25C VDD = 5V High-Power BOR 4.4 20 A +60C Regulator Enabled 4.4 20 A +85C 4.4 20 A +125C Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. PIC18LFXXK80 2011 Microchip Technology Inc. Preliminary DS39977C-page 561 PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device High/Low-Voltage Detect D022B (IHLVD) Legend: Note 1: 2: 3: 4: 5: 3.8 9 A -40C A +25C 4.2 9 VDD = 1.8V 4.3 10 A +60C Regulator Disabled 4.3 10 A +85C 4.3 10 A +125C PIC18LFXXK80 4.5 11 A -40C A +25C 4.8 12 VDD = 3.3V 4.8 12 A +60C Regulator Disabled 4.8 12 A +85C 4.8 12 A +125C PIC18FXXK80 3.8 11 A -40C 4.2 12 A +25C VDD = 3.3V 4.3 12 A +60C Regulator Enabled 4.3 12 A +85C 4.3 12 A +125C PIC18FXXK80 4.9 13 A -40C 4.9 13 A +25C VDD = 5V 4.9 13 A +60C Regulator Enabled 4.9 13 A +85C 4.9 13 A +125C Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. PIC18LFXXK80 DS39977C-page 562 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions PIC18F66K80 Family (Industrial/Extended) Param No. Device A/D Converter D026 (IAD) Legend: Note 1: 2: 3: 4: 5: 0.4 1 A -40C 0.4 1 A +25C VDD = 1.8V A/D on, not converting 0.4 1 A +60C Regulator Disabled 0.4 1 A +85C 0.6 1.5 A +125C PIC18LFXXK80 0.5 1 A -40C 0.5 1 A +25C VDD = 3.3V A/D on, not converting 0.5 1 A +60C Regulator Disabled 0.5 1 A +85C 0.8 2 A +125C PIC18FXXK80 0.5 1 A -40C 0.5 1 A +25C VDD = 3.3V A/D on, not converting 0.5 1 A +60C Regulator Enabled 0.5 1 A +85C 0.8 2 A +125C PIC18FXXK80 1 2 A -40C 1 2 A +25C VDD = 5V A/D on, not converting 1 2 A +60C Regulator Enabled 1 2 A +85C 1 3 A +125C Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. For LF devices, RETEN (CONFIG1L<0>) = 1. For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. PIC18LFXXK80 2011 Microchip Technology Inc. Preliminary DS39977C-page 563 PIC18F66K80 FAMILY 31.3 DC Characteristics: PIC18F66K80 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL D031 D031A D031B D032 D033 D033A D034 VIH D041 D041A D041B D042 D043 D043A D044 IIL D060 D061 D063 IPU D070 Note 1: All I/O Ports: Schmitt Trigger Buffer RC3 and RC4 MCLR OSC1 OSC1 SOSCI Input High Voltage VSS VSS VSS VSS VSS VSS VSS 0.2 VDD 0.3 VDD 0.8 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD V V V V V V V 1.8V VDD 5.5V I2CTM enabled SMBus enabled LP, XT, HS modes EC modes All I/O Ports: Schmitt Trigger Buffer RC3 and RC4 MCLR OSC1 OSC1 SOSCI Input Leakage Current(1) 0.8 0.7 VDD 2.1 0.8 VDD 0.9 VDD 0.7 VDD 0.7 VDD 50 -- -- 50 VDD VDD VDD VDD VDD VDD VDD 500 500 1 400 V V V V V V V nA nA A A 1.8V VDD 5.5V I2C enabled SMBus enabled RC mode HS mode I/O Ports MCLR OSC1 Weak Pull-up Current VSS VPIN VDD, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD VDD = 5.5V, VPIN = VSS Weak Pull-up Current Negative current is defined as current sourced by the pin. DS39977C-page 564 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.3 DC Characteristics: PIC18F66K80 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Output Low Voltage Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VOL D080 I/O Ports: PORTA, PORTB, PORTC PORTD, PORTE, PORTF, PORTG -- -- -- 0.6 0.6 0.6 V V V IOL = 8.5 mA, VDD = 5.5V, -40C to +125C IOL = 3.5 mA, VDD = 5.5V, -40C to +125C IOL = 1.6 mA, VDD = 5.5V, -40C to +125C D083 VOH D090 OSC2/CLKO (EC modes) Output High Voltage(1) I/O Ports: PORTA, PORTB, PORTC PORTD, PORTE, PORTF, PORTG VDD - 0.7 VDD - 0.7 VDD - 0.7 -- -- -- V V V V IOH = -3 mA, VDD = 5.5V, -40C to +125C IOH = -2 mA, VDD = 5.5V, -40C to +125C IOH = -1 mA, VDD = 5.5V, -40C to +125C D092 OSC2/CLKO (INTOSC, EC modes) Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 Pin -- 20 pF In HS mode when external clock is used to drive OSC1 To meet the AC Timing Specifications I2CTM Specification D101 D102 Note 1: CIO CB All I/O Pins and OSC2 SCLx, SDAx -- -- 50 400 pF pF Negative current is defined as current sourced by the pin. 31.4 DC Characteristics: CTMU Current Source Specifications Standard Operating Conditions: 1.8V to 5.5V Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Sym No. Characteristic IOUT1 CTMU Current Source, Base Range IOUT2 CTMU Current Source, 10x Range IOUT3 CTMU Current Source, 100x Range Note 1: -- -- -- 550 5.5 55 -- -- -- nA A A CTMUICON<1:0> = 01 CTMUICON<1:0> = 10 CTMUICON<1:0> = 11 Nominal value at center point of current trim range (CTMUICON<7:2> = 000000). 2011 Microchip Technology Inc. Preliminary DS39977C-page 565 PIC18F66K80 FAMILY TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Internal Program Memory Programming Specifications(1) D110 D113 VPP IDDP Voltage on MCLR/VPP/RE5 pin Supply Current during Programming Data EEPROM Memory D120 D121 ED VDRW Byte Endurance VDD for Read/Write 100K 1.8 1000K -- -- 5.5 E/W V VDD + 1.5 -- -- -- 10 10 V mA (Note 2) -40C to +125C (Note 3, Note 4) DC CHARACTERISTICS Param No. Sym Min Typ Max Units Conditions Using EECON to read/write PIC18FXXKXX devices Using EECON to read/write PIC18LFXXKXX devices 1.8 D122 D123 D124 TDEW Erase/Write Cycle Time -- 20 1M -- 4 -- 10M 3.6 -- -- -- V ms TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(2) Year Provided no other specifications are violated E/W -40C to +125C Program Flash Memory D130 D131 EP VPR Cell Endurance VDD for Read Voltage for Self-Timed Erase or Write Operations VDD Self-Timed Write Cycle Time 1K 1.8 1.8 10K -- -- -- 5.5 3.6 E/W -40C to +125C V V PIC18FXXKXX devices PIC18LFXXKXX devices D132B VPEW 1.8 -- 20 -- -- -- 2 -- -- -- 5.5 -- -- 10 1 V ms PIC18FXXKXX devices D133A TIW D134 D135 D140 TRETD Characteristic Retention IDDP TWE Supply Current during Programming Writes per Erase Cycle Year Provided no other specifications are violated mA For each physical address Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section 8.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. 4: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD2 and target system when programming or debugging with the ICD2. DS39977C-page 566 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 31-2: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V VDD 5.5V, -40C TA +125C Param No. Sym Characteristics Min Typ Max Units Comments D300 D301 D302 D303 D304 Note 1: VIOFF VICM CMRR TRESP TMC2OV Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1) Comparator Mode Change to Output Valid* -- -- 55 -- -- 5.0 -- -- 150 -- 40 AVDD - 1.5 -- 400 10 mV V dB ns s Response time measured with one comparator input at (AVDD - 1.5)/2, while the other input transitions from VSS to VDD. TABLE 31-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 1.8V VDD 5.5V, -40C TA +125C Param No. Sym Characteristics Min Typ Max Units Comments D310 D311 D312 D313 Note 1: VRES VRAA VRUR TSET Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) VDD/24 -- -- -- -- -- 2k -- VDD/32 1/2 -- 10 LSb LSb s Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. TABLE 31-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C TA +125C Param No. Sym Characteristics Min Typ Max Units Comments VRGOUT Regulator Output Voltage CEFC External Filter Capacitor Value -- 4.7 3.3 10 -- -- V F Capacitor must be low-ESR, a low series resistance (< 5) 2011 Microchip Technology Inc. Preliminary DS39977C-page 567 PIC18F66K80 FAMILY 31.5 31.5.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z High Low Period Rise Valid High-impedance High Low SU STO Setup Stop condition DS39977C-page 568 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 31.5.2 TIMING CONDITIONS The temperature and voltages specified in Table 31-5 apply to all timing specifications unless otherwise noted. Figure 31-3 specifies the load conditions for the timing specifications. TABLE 31-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in Section 31.1 and Section 31.3. AC CHARACTERISTICS FIGURE 31-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 VDD/2 RL Load Condition 2 Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF CL = 15 pF for all pins except OSC2/CLKO/RA6 and including D and E outputs as ports for OSC2/CLKO/RA6 2011 Microchip Technology Inc. Preliminary DS39977C-page 569 PIC18F66K80 FAMILY 31.5.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 FIGURE 31-4: OSC1 1 2 3 3 4 4 CLKO TABLE 31-6: Param. No. EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min Max Units Conditions Symbol 1A FOSC External CLKIN Frequency(1) Oscillator Frequency(1) DC DC 0.1 4 4 5 64 4 4 16 16 33 -- -- 10,000 250 250 200 -- -- -- -- 20 50 7.5 MHz MHz MHz MHz MHz kHz ns ns ns ns ns s EC, ECIO Oscillator mode RC Oscillator mode XT Oscillator mode HS Oscillator mode HS + PLL Oscillator mode LP Oscillator mode EC, ECIO Oscillator mode RC Oscillator mode XT Oscillator mode HS Oscillator mode HS + PLL Oscillator mode LP Oscillator mode TCY = 4/FOSC XT Oscillator mode LP Oscillator mode HS Oscillator mode XT Oscillator mode LP Oscillator mode HS Oscillator mode 1 TOSC External CLKIN Period(1) Oscillator Period(1) 15.6 250 250 40 62.5 5 2 3 TCY TOSL, TOSH TOSR, TOSF Instruction Cycle Time(1) 62.5 30 2.5 10 -- -- -- ns ns s External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time ns ns ns ns 4 Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. DS39977C-page 570 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 31-7: Param No. Sym PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V) Characteristic Min Typ Max Units Conditions F10 FOSC Oscillator Frequency Range 4 4 -- -- -- -- -- -- 5 16 20 64 2 +2 MHz VDD = 1.8-5.5V MHz VDD = 3.0-5.5V, -40C to +125C MHz VDD = 1.8-5.5V MHz VDD = 3.0-5.5V, -40C to +125C ms % F11 FSYS On-Chip VCO System Frequency 16 16 F12 F13 trc CLK PLL Start-up Time (Lock Time) CLKOUT Stability (Jitter) -- -2 TABLE 31-8: INTERNAL RC ACCURACY (INTOSC) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min Typ Max Units Conditions PIC18F66K80 Family Param No. OA1 HFINTOSC/MFINTOSC Accuracy @ Freq = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz(1) -2 -5 -10 OA2 LFINTOSC Accuracy @ Freq = 31 kHz -- -- -- -- +2 +5 +10 15 % % % % +25C VDD = 3-5.5V -40C to +85C VDD = 1.8-5.5V -40C to +125C VDD = 1.8-5.5V -40C to +125C VDD = 1.8-5.5V -15 Note 1: Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. 2011 Microchip Technology Inc. Preliminary DS39977C-page 571 PIC18F66K80 FAMILY FIGURE 31-5: CLKO AND I/O TIMING Q4 OSC1 10 CLKO 13 14 19 18 12 16 11 Q1 Q2 Q3 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Note: 15 New Value Refer to Figure 31-3 for load conditions. TABLE 31-9: Param No. CLKO AND I/O TIMING REQUIREMENTS Characteristic Min Typ Max Units Conditions Symbol 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TOSH2CKL OSC1 to CLKO TOSH2CKH OSC1 to CLKO TCKR TCKF CLKO Rise Time CLKO Fall Time -- -- -- -- -- 0.25 TCY + 25 0 -- 100 0 -- -- 20 TCY 75 75 15 15 -- -- -- 50 -- -- 10 10 -- -- 200 200 30 30 0.5 TCY + 20 -- -- 150 -- -- 25 25 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) TCKL2IOV CLKO to Port Out Valid TIOV2CKH Port In Valid before CLKO TCKH2IOI TOSH2IOI Port In Hold after CLKO OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) TIOR TIOF TINP TRBP Port Output Rise Time Port Output Fall Time INTx pin High or Low Time RB<7:4> Change INTx High or Low Time These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC. DS39977C-page 572 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 31-10: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 151 155 160 161 162 163 164 165 166 167 168 169 171 171A TadV2alL TalL2adl TalL2oeL TadZ2oeL Address Out Valid to ALE (address setup time) ALE to Address Out Invalid (address hold time) ALE to OE AD High-Z to OE (bus release to OE) 0.25 TCY - 10 5 10 0 0.125 TCY - 5 20 0 -- 0.5 TCY - 5 -- 0.75 TCY - 25 0.625 TCY - 10 0.25 TCY - 20 -- -- -- 0.125 TCY -- -- -- -- 0.25 TCY 0.5 TCY TCY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 TCY - 25 0.625 TCY + 10 -- 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ToeH2adD OE to AD Driven TadV2oeH LS Data Valid before OE (data setup time) ToeH2adl TalH2alL TalH2alH Tacc Toe TalL2oeH TalH2csL OE to Data In Invalid (data hold time) ALE Pulse Width ALE to ALE (cycle time) Address Valid to Data Valid OE to Data Valid ALE to OE Chip Enable Active to ALE ToeL2oeH OE Pulse Width TubL2oeH AD Valid to Chip Enable Active FIGURE 31-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR PWRT Time-out Oscillator Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: 30 33 32 31 34 Refer to Figure 31-3 for load conditions. 2011 Microchip Technology Inc. Preliminary DS39977C-page 573 PIC18F66K80 FAMILY FIGURE 31-7: VDD BROWN-OUT RESET TIMING BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 31-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units s ms Conditions 30 31 32 33 34 35 36 37 38 39 TmcL TWDT TOST TPWRT TIOZ TBOR TIVRST THLVD TCSD TIOBST MCLR Pulse Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become Stable High/Low-Voltage Detect Pulse Width CPU Start-up Time Time for INTOSC to Stabilize 2 -- -- 4.00 -- -- 1024 TOSC -- 1024 TOSC -- 65.5 -- -- 200 -- 200 5 -- 2 -- 25 -- -- 1 -- -- -- -- 10 -- -- ms s s s s s s TOSC = OSC1 period VDD BVDD (see D005) VDD VHLVD DS39977C-page 574 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 31-8: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD VHLVD For VDIRMAG = 1: (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param Sym No. Characteristic Min Typ Max Units Conditions D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 Transition High-to-Low HLVDL<3:0> = 0001 HLVDL<3:0> = 0010 HLVDL<3:0> = 0011 HLVDL<3:0> = 0100 HLVDL<3:0> = 0101 HLVDL<3:0> = 0110 HLVDL<3:0> = 0111 HLVDL<3:0> = 1000 HLVDL<3:0> = 1001 HLVDL<3:0> = 1010 HLVDL<3:0> = 1011 HLVDL<3:0> = 1100 HLVDL<3:0> = 1101 HLVDL<3:0> = 1110 1.80 2.03 2.24 2.40 2.50 2.70 2.82 2.95 3.24 3.42 3.61 3.82 4.06 4.33 4.64 1.85 2.08 2.29 2.46 2.56 2.77 2.89 3.02 3.32 3.50 3.70 3.91 4.16 4.44 4.75 1.90 2.13 2.35 2.53 2.62 2.84 2.97 3.10 3.41 3.59 3.79 4.10 4.26 4.55 4.87 V V V V V V V V V V V V V V V 2011 Microchip Technology Inc. Preliminary DS39977C-page 575 PIC18F66K80 FAMILY FIGURE 31-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TxCKI 40 42 SOSCO/SCLKI 41 45 47 TMR0 or TMR1 Note: 46 48 Refer to Figure 31-3 for load conditions. TABLE 31-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic Min Max Units Conditions 40 41 42 TT0H TT0L TT0P T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY + 20 10 30 0.5 TCY + 5 10 30 Greater of: 20 ns or (TCY + 40)/N 60 DC 2 TOSC -- -- -- -- -- -- ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) 45 TT1H T1CKI High Time T1CKI Low Time T1CKI Input Period Synchronous, no prescaler Synchronous, with prescaler Asynchronous Synchronous, no prescaler Synchronous, with prescaler Asynchronous Synchronous -- -- -- -- -- -- -- ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8) 46 TT1L 47 TT1P Asynchronous FT1 48 T1CKI Oscillator Input Frequency Range TCKE2TMRI Delay from External T1CKI Clock Edge to Timer Increment -- 50 7 TOSC ns kHz -- DS39977C-page 576 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 31-10: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 52 51 CCPx (Compare or PWM Mode) 53 Refer to Figure 31-3 for load conditions. 54 Note: TABLE 31-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol No. Characteristic Min Max Units Conditions 50 51 52 53 54 TCCL TCCH TCCP TCCR TCCF CCPx Input Low No prescaler Time With prescaler CCPx Input High Time No prescaler With prescaler 0.5 TCY + 20 10 0.5 TCY + 20 10 3 TCY + 40 N -- -- -- -- -- -- -- 25 25 ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) CCPx Input Period CCPx Output Fall Time CCPx Output Fall Time 2011 Microchip Technology Inc. Preliminary DS39977C-page 577 PIC18F66K80 FAMILY FIGURE 31-11: SCKx (CKPx = 0) 78 SCKx (CKPx = 1) 79 MSb 75, 76 SDIx MSb In 74 73 Note: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) 79 80 SDOx 78 LSb bit 6 - - - - - - 1 bit 6 - - - - 1 LSb In Refer to Figure 31-3 for load conditions. TABLE 31-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic Min Max Units Conditions 73 73A 74 75 76 78 79 80 TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF Setup Time of SDIx Data Input to SCKx Edge Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDIx Data Input to SCKx Edge SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) 20 1.5 TCY + 40 40 -- -- -- -- -- -- -- -- 25 25 25 25 50 ns ns ns ns ns ns ns ns TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV DS39977C-page 578 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 31-12: SCKx (CKPx = 0) 79 EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 73 SCKx (CKPx = 1) 80 78 SDOx MSb 75, 76 bit 6 - - - - - - 1 LSb SDIx MSb In 74 bit 6 - - - - 1 LSb In Note: Refer to Figure 31-3 for load conditions. TABLE 31-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic Min Max Units Conditions 73 73A 74 75 76 78 79 80 81 TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF Setup Time of SDIx Data Input to SCKx Edge Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDIx Data Input to SCKx Edge SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) 20 1.5 TCY + 40 40 -- -- -- -- -- TCY -- -- -- 25 25 25 25 50 -- ns ns ns ns ns ns ns ns ns TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV TDOV2SCH, SDOx Data Output Setup to SCKx Edge TDOV2SCL 2011 Microchip Technology Inc. Preliminary DS39977C-page 579 PIC18F66K80 FAMILY FIGURE 31-13: SSx 70 SCKx (CKPx = 0) 71 72 78 79 83 EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SCKx (CKP = 1) 80 SDOx MSb 75, 76 SDIx MSb In 74 73 Note: 79 bit 6 - - - - - - 1 78 LSb 77 bit 6 - - - - 1 LSb In Refer to Figure 31-3 for load conditions. TABLE 31-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic Min Max Units Conditions 70 70A 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83 Note 1: 2: TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSSL2WB SSx to write to SSPBUF TSCH TSCL SCKx Input High Time (Slave mode) SCKx Input Low Time (Slave mode) Continuous Single Byte Continuous Single Byte 3 TCY 3 TCY 1.25 TCY + 30 40 1.25 TCY + 30 40 20 -- -- -- -- -- -- -- -- -- 25 25 50 25 25 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge TDIV2SCL TB2B TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL TDOR TDOF TSCR TSCF SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 40 -- -- 10 -- -- -- 1.5 TCY + 40 TSSH2DOZ SSx to SDOx Output High-impedance TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV TSCH2SSH, SSx after SCKx Edge TSCL2SSH Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. DS39977C-page 580 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 31-14: SSx 70 83 71 72 EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SCKx (CKPx = 0) SCKx (CKPx = 1) 80 MSb 75, 76 SDIx MSb In 74 Note: SDOx bit 6 - - - - - - 1 LSb 77 bit 6 - - - - 1 LSb In Refer to Figure 31-3 for load conditions. TABLE 31-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min Max Units Conditions 70 70A 71 71A 72 72A 73A 74 75 76 77 78 79 80 82 83 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSSL2WB TSCH TSCL TB2B SSx to write to SSPBUF SCKx Input High Time (Slave mode) SCKx Input Low Time (Slave mode) Continuous Single Byte Continuous Single Byte 3 TCY 3 TCY 1.25 TCY + 30 40 1.25 TCY + 30 40 40 -- -- 10 -- -- -- -- 1.5 TCY + 40 -- -- -- -- -- -- -- -- 25 25 50 25 25 50 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 2) (Note 1) Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL TDOR TDOF TSCR TSCF SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) TSSH2DOZ SSx to SDOx Output High-Impedance TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV TSSL2DOV SDOx Data Output Valid after SSx Edge TSCH2SSH, SSx after SCKx Edge TSCL2SSH Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. Note 1: 2: 2011 Microchip Technology Inc. Preliminary DS39977C-page 581 PIC18F66K80 FAMILY FIGURE 31-15: I2CTM BUS START/STOP BITS TIMING SCLx 91 90 92 93 SDAx Start Condition Note: Stop Condition Refer to Figure 31-3 for load conditions. TABLE 31-19: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. Characteristic Min Max Units Conditions 90 91 92 93 TSU:STA THD:STA TSU:STO Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4700 600 4000 600 4700 600 4000 600 -- -- -- -- -- -- -- -- ns ns ns ns Only relevant for Repeated Start condition After this period, the first clock pulse is generated THD:STO Stop Condition Hold Time DS39977C-page 582 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 31-16: I2CTM BUS DATA TIMING 103 100 101 90 91 106 107 92 102 SCLx SDAx In 109 109 110 SDAx Out Note: Refer to Figure 31-3 for load conditions. TABLE 31-20: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. Symbol Characteristic Min Max Units s s s s Conditions 100 THIGH Clock High Time 100 kHz mode 400 kHz mode MSSP module 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode MSSP module 102 TR SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode ns ns ns ns s s s s CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated 103 TF SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 90 91 106 107 92 109 110 D102 Note 1: 2: TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF CB Start Condition Setup Time 100 kHz mode 400 kHz mode Start Condition Hold Time Data Input Hold Time Data Input Setup Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Stop Condition Setup Time 100 kHz mode 400 kHz mode Output Valid from Clock Bus Free Time Bus Capacitive Loading 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode ns s ns ns s s (Note 2) ns ns s s (Note 1) Time the bus must be free before a new transmission can start pF As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. 2011 Microchip Technology Inc. Preliminary DS39977C-page 583 PIC18F66K80 FAMILY FIGURE 31-17: MSSP I2CTM BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 90 92 93 SDAx Start Condition Note: Stop Condition Refer to Figure 31-3 for load conditions. TABLE 31-21: MSSP I2CTM BUS START/STOP BITS REQUIREMENTS Param. Symbol No. Characteristic Min Max Units Conditions 90 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- -- -- -- -- -- -- -- -- -- ns Only relevant for Repeated Start condition After this period, the first clock pulse is generated 91 THD:STA Start Condition Hold Time ns 92 TSU:STO Stop Condition Setup Time ns 93 THD:STO Stop Condition Hold Time ns Note 1: Maximum pin capacitance = 10 pF for all I2CTM pins. FIGURE 31-18: MSSP I2CTM BUS DATA TIMING 103 100 101 90 91 106 107 92 102 SCLx SDAx In 109 109 110 SDAx Out Note: Refer to Figure 31-3 for load conditions. DS39977C-page 584 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 31-22: MSSP I2CTM BUS DATA REQUIREMENTS Param. Symbol No. Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 -- 250 100 -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 -- -- -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 s -- -- -- -- -- -- ns ns ns ns ns ns -- -- -- -- -- -- -- s 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 102 TR SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 1 MHz mode(1) CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated 103 TF SDAx and 100 kHz mode SCLx Fall Time 400 kHz mode 1 MHz mode(1) Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 90 TSU:STA 91 THD:STA Start Condition Hold Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time 106 ns ns ns ns -- -- -- ns ns ns s s s (Note 2) 107 -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 92 TSU:STO Stop Condition Setup Time TAA Output Valid from Clock Bus Free Time 109 110 TBUF Time the bus must be free before a new transmission can start D102 Note 1: 2: CB Bus Capacitive Loading pF Maximum pin capacitance = 10 pF for all I2CTM pins. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx line is released. 2011 Microchip Technology Inc. Preliminary DS39977C-page 585 PIC18F66K80 FAMILY FIGURE 31-19: TXx/CKx pin RXx/DTx pin 120 Note: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING 121 121 122 Refer to Figure 31-3 for load conditions. TABLE 31-23: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. Symbol Characteristic Min Max Units Conditions 120 121 122 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid TCKRF TDTRF Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time -- -- -- 40 20 20 ns ns ns FIGURE 31-20: TXx/CKx pin RXx/DTx pin EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING 125 126 Refer to Figure 31-3 for load conditions. Note: TABLE 31-24: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. Symbol Characteristic Min Max Units Conditions 125 126 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx (DTx hold time) TCKL2DTL Data Hold after CKx (DTx hold time) 10 15 -- -- ns ns DS39977C-page 586 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F66K80 FAMILY (INDUSTRIAL/EXTENDED) Param No. Sym Characteristic Min Typ Max Units Conditions VREF 3.0V A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A28 A29 A30 NR EIL EDL EOFF EGN -- Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity -- -- -- -- -- -- -- -- -- -- <1 -- <1 -- <1 -- <1 -- Guaranteed(1) -- -- -- -- -- -- -- 12 2.0 2.0 +1.5/-1.0 +1.5/-1.0 5 3 1.25 2.00 VDD - VSS AVDD + 0.3V AVDD - 3.0V VREFH VDD + 0.3 VSS + 0.3 2.5 bit LSB LSB LSB LSB LSB LSB LSB LSB -- V V V V V V k VDD = 3.0V (VREF 3.0V) VDD = 5.0V VDD = 3.0V (VREF 3.0V) VDD = 5.0V VDD = 3.0V (VREF 3.0V) VDD = 5.0V VDD = 3.0V (VREF 3.0V) VDD = 5.0V VSS VAIN VREF For 12-bit resolution For 12-bit resolution For 12-bit resolution VREF Reference Voltage Range (VREFH - VREFL) 3 AVSS + 3.0V AVSS - 0.3V VREFL VDD - 0.3 VSS - 0.3 -- VREFH Reference Voltage High VREFL Reference Voltage Low VAIN AVDD AVSS ZAIN Analog Input Voltage Analog Supply Voltage Analog Supply Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) A50 IREF -- -- -- -- 5 150 A A During VAIN acquisition. During A/D conversion cycle. Note 1: 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. 2011 Microchip Technology Inc. Preliminary DS39977C-page 587 PIC18F66K80 FAMILY FIGURE 31-21: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) Q4 A/D CLK 132 131 130 A/D DATA 11 10 9 ... ... 2 1 0 ADRES ADIF GO OLD_DATA NEW_DATA TCY (Note 1) DONE SAMPLE SAMPLING STOPPED Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 31-26: A/D CONVERSION REQUIREMENTS Param Symbol No. Characteristic Min Max Units s s s s Conditions 130 TAD A/D Clock Period 0.8 1.4 -- -- 12.5(1) 25 (1) TOSC based, VREF 3.0V VDD = 3.0V; TOSC based, VREF full range A/D RC mode VDD = 3.0V; A/D RC mode 1 3 15 -- (Note 4) 131 132 135 TBD Note 1: 2: 3: 4: TCNV TACQ TSWC TDIS Conversion Time (not including acquisition time)(2) Acquisition Time(3) Switching Time from Convert Sample Discharge Time 14 1.4 -- 0.2 TAD s s -40C to +125C -40C to +125C -- The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES registers may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock. DS39977C-page 588 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 32.0 32.1 PACKAGING INFORMATION Package Marking Information 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 18F25K80 /MM e3 1010017 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F26K80/SO e3 1010017 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F26K80-I/SP e3 1010017 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC18F26K80 -I/SS e3 1010017 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011 Microchip Technology Inc. Preliminary DS39977C-page 589 PIC18F66K80 FAMILY 32.1 Package Marking Information (Continued) 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F45K80-I/P e3 1010017 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP 18F45K80 -I/ML e3 1010017 Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F45K80 Example -I/PT e3 1010017 64-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F65K80 -I/MR e3 1010017 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F65K80 -I/PT e3 1010017 DS39977C-page 590 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY 32.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 00 [ [ ZLWK PP &RQWDFW /HQJWK 1RWH PP %RG\ >4)1 6@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E2 E b 2 1 2 1 N L TOP VIEW NOTE 1 BOTTOM VIEW K N A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 6WDQGRII &RQWDFW 7KLFNQHVV 2YHUDOO :LGWK ([SRVHG 3DG :LGWK 2YHUDOO /HQJWK ([SRVHG 3DG /HQJWK &RQWDFW :LGWK &RQWDFW /HQJWK 1 H $ $ $ ( ( ' ' E / %6& 5() %6& %6& 0,1 0,//,0(7(56 120 0$; &RQWDFW WR ([SRVHG 3DG . 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 3DFNDJH LV VDZ VLQJXODWHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % 2011 Microchip Technology Inc. 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PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. 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Preliminary DS39977C-page 601 PIC18F66K80 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39977C-page 602 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS39977C-page 603 PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39977C-page 604 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. 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PIC18F66K80 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2011 Microchip Technology Inc. Preliminary DS39977C-page 607 PIC18F66K80 FAMILY NOTES: DS39977C-page 608 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (August 2010) Original data sheet for PIC18F66K80 family devices. MIGRATION TO PIC18F66K80 FAMILY Revision B (December 2010) Changes to Section 31.0 "Electrical Characteristics" and minor text edits throughout document. Revision C (January 2011) Section 2.0 "Guidelines for Getting Started with PIC18FXXKXX Microcontrollers" was added to the data sheet. Changes to Section 31.0 "Electrical Characteristics" for PIC18F66K80 family devices. Minor text edits throughout document. Devices in the PIC18F66K80, PIC18F4580, PIC18F4680 and 18F8680 families are similar in their functions and features. Code can be migrated from the other families to the PIC18F66K80 without many changes. The differences between the device families are listed in Table B-1 and Table B-2. For more details on migrating to the PIC18F66K80, refer to "PIC18FXX80 to PIC18FXXK80 Migration Guide" (DS39982). TABLE B-1: NOTABLE DIFFERENCES BETWEEN 28, 40 AND 44-PIN DEVICES - PIC18F66K80, PIC18F4580 AND PIC18F4680 FAMILIES PIC18F66K80 Family PIC18F4680 Family PIC18F4580 Family Characteristic Max Operating Frequency 64 MHz Max Program Memory 64 Kbytes Data Memory (bytes) 3,648 CTMU Yes SOSC Oscillator Options Low-power oscillator option for SOSC T1CKI Clock T1CKI can be used as a clock without enabling the SOSC oscillator INTOSC Up to 16 MHz Timers Two 8-bit, three 16-bit ECCP One for all devices CCP Data EEPROM (bytes) WDT Prescale Options 5V Operation nanoWatt XLP Regulator Low-Power BOR A/D Converter A/D Channels Four 1,024 22 18FXXK80 parts - 5V operation 18LFXXK80 parts - 3.3V operation Yes 18FXXK80 parts - Yes 18LFXXK80 parts - No Yes 12-bit signed differential 28-pin devices - Eight Channels 40 and 44-pin devices - 15 Channels Yes Two Two 14 Yes Yes Available for all oscillator options No 40 MHz 64 Kbytes 3,328 No No options No Up to 8 MHz One 8-bit, three 16-bit 40 and 44-pin devices - One 28-pin devices - None One 1,024 16 Yes No No 40 MHz 32 Kbytes 1,536 No No options No Up to 8 MHz One 8-bit, three 16-bit 40 and 44-pin devices - One 28-pin devices - None One 256 16 Yes No No Internal Temp Sensor EUSART Comparators Oscillator Options Ultra Low-Power Wake-up (ULPW) Adjustable Slew Rate for I/O PLL TXM Modulator No No 10-bit 10-bit 8 Channels for 28-pin devices/ 8 Channels for 28-pin devices/ 11 Channels for 40 and 44-pin 11 Channels for 40 and 44-pin devices devices No No One One 28-pin devices - None 28-pin devices - None 40 and 44-pin devices - Two 40 and 44-pin devices - Two Nine Nine No No No Available only for high-speed crystal and internal oscillator No No Available only for high-speed crystal and internal oscillator No 2011 Microchip Technology Inc. Preliminary DS39977C-page 609 PIC18F66K80 FAMILY TABLE B-2: NOTABLE DIFFERENCES BETWEEN 64-PIN DEVICES - PIC18F66K80 AND PIC18F8680 FAMILIES PIC18F66K80 Family PIC18F8680 Family Characteristic Max Operating Frequency Max Program Memory Data Memory (bytes) CTMU SOSC Oscillator Options T1CKI Clock INTOSC SPI/I2CTM Timers ECCP CCP Data EEPROM (bytes) WDT Prescale Options 5V Operation nanoWatt XLP On-Chip 3.3V Regulator Low-Power BOR A/D Converter A/D Channels Internal Temp Sensor EUSART Comparators Oscillator Options Ultra Low-Power Wake-up (ULPW) Adjustable Slew Rate for I/O PLL Data Signal Modulator 64 MHz 64K 3,648 Yes Low-power oscillator option for SOSC T1CKI can be used as a clock without enabling the SOSC oscillator Up to 16 MHz 1 Module Two 8-bit, Three 16-bit 1 4 1,024 22 18FXXK80 parts - 5V operation 18LFXXK80 parts - 3.3V operation Yes 18FXXK80 parts - Yes 18LFXXK80 parts - No Yes 12-bit signed differential 15 Channels Yes Two Two 14 Yes Yes Available for all oscillator options Yes 40 MHz 64K 3,328 No No options No No Internal Oscillator 1 Module Two 8-bit, Three 16-bit 1 1 1,024 16 Yes No No No 10-bit 12 Channels No One Two Seven No No Available for only high-speed crystal and external oscillator No DS39977C-page 610 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY INDEX A A/D .................................................................................... 363 A/D Converter Interrupt, Configuring ........................ 371 Acquisition Requirements ......................................... 372 ADRESH Register..................................................... 369 Analog Port Pins, Configuring................................... 373 Associated Registers ................................................ 376 Automatic Acquisition Time....................................... 373 Configuring the Module............................................. 371 Conversion Clock (TAD) ............................................ 373 Conversion Requirements ........................................ 588 Conversion Status (GO/DONE Bit) ........................... 369 Conversions .............................................................. 374 Converter Characteristics ......................................... 587 Differential Converter ................................................ 363 Operation in Power-Managed Modes ....................... 375 Use of the Special Event Triggers ............................ 375 Absolute Maximum Ratings .............................................. 541 AC (Timing) Characteristics .............................................. 568 Load Conditions for Device Timing Specifications........................................ 569 Parameter Symbology .............................................. 568 Temperature and Voltage Specifications .................. 569 Timing Conditions ..................................................... 569 ACKSTAT ......................................................................... 328 ACKSTAT Status Flag ...................................................... 328 ADCON0 Register GO/DONE Bit............................................................ 369 ADDFSR ........................................................................... 530 ADDLW ............................................................................. 493 ADDULNK......................................................................... 530 ADDWF ............................................................................. 493 ADDWFC .......................................................................... 494 ADRESL Register ............................................................. 369 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................. 494 ANDWF ............................................................................. 495 Assembler MPASM Assembler................................................... 538 Auto-Wake-up on Sync Break Character .......................... 354 Connections for On-Chip Voltage Regulator ............ 478 Crystal/Ceramic Resonator Operation (HS, HSPLL ........................................................ 60 CTMU ....................................................................... 241 CTMU Current Source Calibration Circuit ................ 247 CTMU Temperature Measurement Circuit ............... 255 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 256 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 254 Data Signal Modulator .............................................. 202 Device Clock............................................................... 54 Differential Channel Measurement ........................... 363 EUSART Receive ..................................................... 352 EUSART Transmit .................................................... 349 External Components for the SOSC Oscillator......... 220 External Power-on Reset Circuit (Slow VDD Power-up) ......................................... 83 Fail-Safe Clock Monitor (FSCM)............................... 481 Full-Bridge Application.............................................. 281 Generic I/O Port Operation....................................... 177 Half-Bridge Applications ................................... 280, 287 High/Low-Voltage Detect with External Input ........... 390 Interrupt Logic........................................................... 154 INTIO1 Oscillator Mode .............................................. 62 INTIO2 Oscillator Mode .............................................. 62 MSSP (I2C Master Mode)......................................... 322 MSSP (I2C Mode)..................................................... 302 MSSP (SPI Mode) .................................................... 293 On-Chip Reset Circuit................................................. 81 PIC18F2XK80............................................................. 17 PIC18F4XK80............................................................. 18 PIC18F6XK80............................................................. 19 PLL ............................................................................. 61 PORTD and PORTE (Parallel Slave Port)................ 198 PWM (Enhanced Mode) ........................................... 277 PWM Operation (Simplified) ..................................... 268 RC Oscillator Mode .................................................... 59 RCIO Oscillator Mode................................................. 59 Reads from Flash Program Memory ........................ 139 Simplified Steering.................................................... 290 Single Channel Measurement .................................. 363 Single Comparator.................................................... 380 Table Read Operation .............................................. 135 Table Write Operation .............................................. 136 Table Writes to Flash Program Memory................... 141 Timer0 in 16-Bit Mode .............................................. 212 Timer0 in 8-Bit Mode ................................................ 212 Timer1 ...................................................................... 219 Timer2 ...................................................................... 228 Timer3 ...................................................................... 232 Timer4 ...................................................................... 240 Transmit Buffers ....................................................... 446 Ultra Low-Power Wake-up Initialization...................... 79 Using Open-Drain Output ......................................... 179 Watchdog Timer ....................................................... 476 BN..................................................................................... 496 BNC .................................................................................. 497 BNN .................................................................................. 497 BNOV ............................................................................... 498 BNZ .................................................................................. 498 BOR. See Brown-out Reset. BOV .................................................................................. 501 B Baud Rate Generator ........................................................ 324 BC ..................................................................................... 495 BCF ................................................................................... 496 BF ..................................................................................... 328 BF Status Flag .................................................................. 328 Bit Timing Configuration Registers BRGCON1 ................................................................ 456 BRGCON2 ................................................................ 456 BRGCON3 ................................................................ 456 Block Diagrams A/D ............................................................................ 370 Analog Input Model ................................................... 371 Baud Rate Generator................................................ 324 CAN Buffers and Protocol Engine............................. 396 Capture Mode Operation .................................. 263, 275 Comparator Analog Input Model ............................... 380 Comparator Configurations....................................... 382 Comparator Module .................................................. 377 Comparator Voltage Reference ................................ 386 Comparator Voltage Reference Output Buffer.......... 387 Compare Mode Operation ................................ 266, 276 2011 Microchip Technology Inc. Preliminary DS39977C-page 611 PIC18F66K80 FAMILY BRA................................................................................... 499 Break Character (12-Bit) Transmit and Receive ............... 356 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ...................................................... 84 Detecting ..................................................................... 84 Disabling in Sleep Mode ............................................. 84 Software Enabled........................................................ 84 BSF ................................................................................... 499 BTFSC .............................................................................. 500 BTFSS............................................................................... 500 BTG................................................................................... 501 BZ...................................................................................... 502 Computed GOTO Using an Offset Value.................. 109 Current Calibration Routine ...................................... 249 Data EEPROM Read ................................................ 148 Data EEPROM Refresh Routine............................... 149 Data EEPROM Write ................................................ 148 Erasing a Flash Program Memory Row.................... 140 Fast Register Stack .................................................. 109 How to Clear RAM (Bank 1) Using Indirect Addressing........................................... 128 Initializing PORTA..................................................... 181 Initializing PORTB..................................................... 184 Initializing PORTC .................................................... 187 Initializing PORTD .................................................... 190 Initializing PORTE..................................................... 193 Initializing PORTF..................................................... 195 Initializing PORTG .................................................... 196 Loading the SSPBUF (SSPSR) Register.................. 296 Reading a CAN Message ......................................... 416 Reading a Flash Program Memory Word ................. 139 Routine for Capacitive Touch Switch........................ 253 Routine for Temperature Measurement Using Internal Diode ................................. 255, 257 Saving STATUS, WREG and BSR Registers in RAM.............................................. 175 Setup for CTMU Calibration Routines ...................... 248 Transmitting a CAN Message Using Banked Method ................................................ 408 Transmitting a CAN Message Using WIN Bits.......... 409 Ultra Low-Power Wake-up Initialization ...................... 79 WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers..................... 400 Writing to Flash Program Memory .................... 142-143 Code Protection ................................................................ 461 COMF ............................................................................... 504 Comparator....................................................................... 377 Analog Input Connection Considerations ................. 380 Associated Registers ................................................ 384 Configuration ............................................................ 381 Control ...................................................................... 381 Effects of a Reset ..................................................... 384 Enable and Input Selection....................................... 381 Enable and Output Selection .................................... 381 Interrupts .................................................................. 383 Operation .................................................................. 380 Operation During Sleep ............................................ 384 Response Time......................................................... 380 Comparator Specifications................................................ 567 Comparator Voltage Reference ........................................ 385 Accuracy and Error ................................................... 386 Associated Registers ................................................ 387 Configuring ............................................................... 385 Connection Considerations....................................... 386 Effects of a Reset ..................................................... 386 Operation During Sleep ............................................ 386 Compare (CCP Module) ................................................... 265 CCP Pin Configuration.............................................. 265 Software Interrupt ..................................................... 265 Special Event Trigger ............................................... 265 Timer1/3 Mode Selection.......................................... 265 Compare (ECCP Module)................................................. 276 CCPR1 Register ....................................................... 276 Pin Configuration ...................................................... 276 Software Interrupt ..................................................... 276 Special Event Trigger ....................................... 238, 276 Timer1/2/3/4 Mode Selection.................................... 276 C C Compilers MPLAB C18 .............................................................. 538 CALL ................................................................................. 502 CALLW.............................................................................. 531 CAN Module External-Internal Clock in HS-PLL Based Oscillators .............................................. 451 Capture (CCP Module)...................................................... 263 CCP Pin Configuration .............................................. 263 CCPRxH:CCPRxL Registers .................................... 263 Software Interrupt ..................................................... 264 Timer1/3 Mode Selection .......................................... 263 Capture (ECCP Module) ................................................... 274 CCPR1H:CCPR1L Registers.................................... 274 ECCP Pin Configuration ........................................... 274 Prescaler ................................................................... 275 Software Interrupt ..................................................... 275 Timer1/2/3/4 Mode Selection .................................... 275 Capture, Compare, Timer1/3 Associated Registers ................................................ 267 Capture/Compare/PWM (CCP)......................................... 259 Capture Mode. See Capture. CCP Mode and Timer Resources ............................. 262 CCPRxH Register ..................................................... 262 CCPRxL Register...................................................... 262 Compare Mode. See Compare. Configuration............................................................. 262 Open-Drain Output Option ........................................ 262 Charge Time Measurement Unit (CTMU) ......................... 241 Associated Registers ................................................ 258 Calibrating the Module .............................................. 246 Creating a Delay ....................................................... 256 Effects of a Reset...................................................... 258 Measuring Capacitance ............................................ 252 Measuring Time ........................................................ 254 Module Initialization .................................................. 246 Operation .................................................................. 245 During Sleep, Idle Modes.................................. 258 Temperature Measurement ...................................... 255 Clock Sources ..................................................................... 58 Default System Clock on Reset .................................. 59 Selection Using OSCCON Register ............................ 58 CLRF................................................................................. 503 CLRWDT........................................................................... 503 Code Examples 16 x 16 Signed Multiply Routine ............................... 152 16 x 16 Unsigned Multiply Routine ........................... 152 8 x 8 Signed Multiply Routine ................................... 151 8 x 8 Unsigned Multiply Routine ............................... 151 Capacitance Calibration Routine .............................. 251 Changing Between Capture Prescalers ............ 264, 275 Changing to Configuration Mode .............................. 400 DS39977C-page 612 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Computed GOTO .............................................................. 109 Configuration Bits.............................................................. 461 Configuration Mismatch (CM) Reset ................................... 85 Configuration Mode........................................................... 442 Configuration Register Protection ..................................... 486 Core Features Easy Migration ............................................................ 14 Extended Instruction Set............................................. 13 Memory Options.......................................................... 13 nanoWatt Technology ................................................. 13 Oscillator Options and Features ................................. 13 CPFSEQ ........................................................................... 504 CPFSGT ........................................................................... 505 CPFSLT ............................................................................ 505 Crystal Oscillator/Ceramic Resonator ................................. 60 Customer Change Notification Service ............................. 623 Customer Notification Service........................................... 623 Customer Support............................................................. 623 Programmable Modulator Data ................................ 206 Slew Rate Control..................................................... 206 DAW ................................................................................. 506 DC Characteristics............................................................ 564 CTMU Current Source Specifications....................... 565 Power-Down and Supply Current ............................. 544 Supply Voltage ......................................................... 543 DCFSNZ ........................................................................... 507 DECF ................................................................................ 506 DECFSZ ........................................................................... 507 Default System Clock ......................................................... 59 Details on Individual Family Members ................................ 14 Development Support ....................................................... 537 Device Overview................................................................. 13 Features (28-Pin Devices).......................................... 15 Features (40/44-Pin Devices)..................................... 15 Features (64-Pin Devices).......................................... 16 Device Reset Timers .......................................................... 85 Oscillator Start-up Timer (OST).................................. 85 PLL Lock Time-out ..................................................... 85 Power-up Timer (PWRT) ............................................ 85 Direct Addressing ............................................................. 129 Disable/Sleep Mode.......................................................... 442 D Data Addressing Modes.................................................... 128 Comparing Addressing Modes with the Extended Instruction Set Enabled .................... 133 Direct......................................................................... 128 Indexed Literal Offset................................................ 132 BSR .................................................................. 134 Instructions Affected ......................................... 132 Mapping Access Bank ...................................... 134 Indirect ...................................................................... 128 Inherent and Literal ................................................... 128 Data EEPROM Associated Registers ................................................ 150 Code Protection ........................................................ 486 During Code-Protect ................................................. 149 EEADR and EEADRH Registers .............................. 145 EECON1 and EECON2 Registers ............................ 145 Overview ................................................................... 145 Reading..................................................................... 147 Spurious Write Protection ......................................... 149 Using......................................................................... 149 Write Verify ............................................................... 147 Writing....................................................................... 147 Data EEPROM Memory Operation During Code-Protect ................................ 149 Data Memory .................................................................... 112 Access Bank ............................................................. 114 Bank Select Register (BSR)...................................... 112 Extended Instruction Set........................................... 132 General Purpose Registers....................................... 114 Memory Maps PIC18FX5K80/X6K80 Devices ......................... 113 Special Function Registers ............................... 115 Special Function Registers ....................................... 115 Data Signal Modulator (DSM) ........................................... 201 Associated Registers ................................................ 210 Carrier Signal Sources.............................................. 203 Carrier Source Pin Disable........................................................ 206 Polarity Select ................................................... 206 Carrier Synchronization ............................................ 203 Effects of a Reset...................................................... 206 Modulated Output Polarity ........................................ 206 Modulator Signal Sources......................................... 203 Modulator Source Pin Disable .................................. 206 Operation .................................................................. 203 Operation in Sleep Mode .......................................... 206 E ECAN Module ................................................................... 395 Baud Rate Setting .................................................... 450 Bit Time Partitioning ................................................. 450 Bit Timing Configuration Registers ........................... 456 Calculating TQ, Nominal Bit Rate and Nominal Bit Time .............................................. 453 CAN Baud Rate Registers........................................ 434 CAN Control and Status Registers ........................... 397 CAN I/O Control Register ......................................... 437 CAN Interrupt Registers ........................................... 438 CAN Interrupts.......................................................... 457 Bus Activity Wake-up........................................ 458 Bus-Off ............................................................. 459 Code Bits .......................................................... 458 Error ................................................................. 458 Message Error .................................................. 458 Receive ............................................................ 458 Receiver Bus Passive....................................... 459 Receiver Overflow ............................................ 459 Receiver Warning ............................................. 459 Transmit............................................................ 458 Transmitter Bus Passive................................... 459 Transmitter Warning ......................................... 459 CAN Message Buffers .............................................. 444 Dedicated Receive ........................................... 444 Dedicated Transmit .......................................... 444 Programmable Auto-RTR ................................. 445 Programmable Transmit/Receive ..................... 444 CAN Message Transmission .................................... 445 Aborting ............................................................ 445 Initiating ............................................................ 445 Priority .............................................................. 446 CAN Modes of Operation ......................................... 442 CAN Registers.......................................................... 397 Configuration Mode .................................................. 442 Dedicated CAN Receive Buffer Registers ................ 410 Dedicated CAN Transmit Buffer Registers ............... 404 Disable/Sleep Mode ................................................. 442 2011 Microchip Technology Inc. Preliminary DS39977C-page 613 PIC18F66K80 FAMILY Error Detection .......................................................... 456 Acknowledge..................................................... 456 Bit...................................................................... 456 CRC .................................................................. 456 Error Modes and Counters................................ 456 Error States....................................................... 456 Form.................................................................. 456 Stuff Bit ............................................................. 456 Error Modes State (diagram) .................................... 457 Error Recognition Mode ............................................ 443 Filter-Mask Truth (table)............................................ 448 Functional Modes...................................................... 443 Mode 0 (Legacy Mode) ..................................... 443 Mode 1 (Enhanced Legacy Mode).................... 443 Mode 2 (Enhanced FIFO Mode) ....................... 444 Information Processing Time (IPT) ........................... 453 Lengthening a Bit Period........................................... 454 Listen Only Mode ...................................................... 443 Loopback Mode ........................................................ 443 Message Acceptance Filters and Masks .......... 425, 448 Message Acceptance Mask and Filter Operation .......................................................... 449 Message Reception .................................................. 447 Enhanced FIFO Mode....................................... 448 Priority............................................................... 447 Time-Stamping.................................................. 448 Normal Mode ............................................................ 442 Oscillator Tolerance .................................................. 455 Overview ................................................................... 395 Phase Buffer Segments ............................................ 453 Programmable TX/RX and Auto-RTR Buffers .......... 417 Programming Time Segments .................................. 455 Propagation Segment ............................................... 453 Sample Point............................................................. 453 Shortening a Bit Period ............................................. 455 Synchronization ........................................................ 454 Hard .................................................................. 454 Resynchronization ............................................ 454 Rules................................................................. 454 Synchronization Segment ......................................... 453 Time Quanta ............................................................. 453 Values for ICODE (table) .......................................... 458 Effect on Standard PIC18 Instructions .............................. 534 Effects of Power-Managed Modes on Various Clock Sources............................................................. 65 Electrical Characteristics................................................... 541 Enhanced Capture/Compare/PWM (ECCP) ..................... 271 Capture Mode. See Capture. Compare Mode. See Compare. ECCP Mode and Timer Resources........................... 274 Enhanced PWM Mode .............................................. 277 Auto-Restart...................................................... 286 Auto-Shutdown ................................................. 284 Direction Change in Full-Bridge Output Mode ............................................. 283 Full-Bridge Application ...................................... 281 Full-Bridge Mode............................................... 281 Half-Bridge Application ..................................... 280 Half-Bridge Application Examples..................... 287 Half-Bridge Mode .............................................. 280 Output Relationships (Active-High and Active-Low) ............................................... 278 Output Relationships Diagram .......................... 279 Programmable Dead-Band Delay ..................... 287 Shoot-Through Current..................................... 287 Start-up Considerations.................................... 284 Outputs and Configuration........................................ 274 Enhanced Capture/Compare/PWM (ECCP) and Timer1/2/3/4 Associated Registers........................... 292 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations 16 x 16 Signed Multiplication Algorithm.................... 152 16 x 16 Unsigned Multiplication Algorithm................ 152 A/D Acquisition Time ................................................ 372 A/D Minimum Charging Time.................................... 372 Calculating the Minimum Required Acquisition Time ............................................... 372 Errata .................................................................................. 11 Error Recognition Mode.................................................... 442 EUSART Asynchronous Mode ................................................. 349 12-Bit Break Transmit and Receive.................. 356 Associated Registers, Receive......................... 353 Associated Registers, Transmit........................ 351 Auto-Wake-up on Sync Break .......................... 354 Receiver ........................................................... 352 Setting up 9-Bit Mode with Address Detect ......................................... 352 Transmitter ....................................................... 349 Baud Rate Generator Operation in Power-Managed Mode................. 343 Baud Rate Generator (BRG) .................................... 343 Associated Registers........................................ 344 Auto-Baud Rate Detect..................................... 347 Baud Rate Error, Calculating............................ 344 Baud Rates, Asynchronous Modes .................. 345 High Baud Rate Select (BRGH Bit) .................. 343 Sampling........................................................... 343 Synchronous Master Mode....................................... 357 Associated Registers, Receive......................... 360 Associated Registers, Transmit........................ 358 Reception ......................................................... 359 Transmission .................................................... 357 Synchronous Slave Mode......................................... 361 Associated Registers, Receive......................... 362 Associated Registers, Transmit........................ 361 Reception ......................................................... 362 Transmission .................................................... 361 Extended Instruction Set ADDFSR ................................................................... 530 ADDULNK................................................................. 530 CALLW ..................................................................... 531 MOVSF ..................................................................... 531 MOVSS..................................................................... 532 PUSHL...................................................................... 532 SUBFSR ................................................................... 533 SUBULNK................................................................. 533 External Oscillator Modes Clock Input (EC Modes).............................................. 61 HS............................................................................... 60 DS39977C-page 614 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY F Fail-Safe Clock Monitor............................................. 461, 481 Exiting Operation ...................................................... 481 Interrupts in Power-Managed Modes........................ 482 POR or Wake from Sleep ......................................... 482 WDT During Oscillator Failure .................................. 481 Fast Register Stack........................................................... 109 Firmware Instructions........................................................ 487 Flash Program Memory .................................................... 135 Associated Registers ................................................ 143 Control Registers ...................................................... 136 EECON1 and EECON2 .................................... 136 TABLAT (Table Latch) Register........................ 138 TBLPTR (Table Pointer) Register ..................... 138 Erase Sequence ....................................................... 140 Erasing...................................................................... 140 Operation During Code-Protect ................................ 143 Reading..................................................................... 139 Table Pointer Boundaries Based on Operation....................... 138 Table Pointer Boundaries ......................................... 138 Table Reads and Table Writes ................................. 135 Write Sequence ........................................................ 141 Writing....................................................................... 141 Protection Against Spurious Writes .................. 143 Unexpected Termination................................... 143 Write Verify ....................................................... 143 FSCM. See Fail-Safe Clock Monitor. Bus Collision During a Repeated Start Condition................... 335 During a Stop Condition ................................... 336 Clock Arbitration ....................................................... 325 Clock Stretching ....................................................... 317 10-Bit Slave Receive Mode (SEN = 1) ............. 317 10-Bit Slave Transmit Mode ............................. 317 7-Bit Slave Receive Mode (SEN = 1) ............... 317 7-Bit Slave Transmit Mode ............................... 317 Clock Synchronization and the CKP bit.................... 318 Effects of a Reset ..................................................... 332 General Call Address Support.................................. 321 I2C Clock Rate w/BRG ............................................. 324 Master Mode............................................................. 322 Operation.......................................................... 323 Reception ......................................................... 328 Repeated Start Condition Timing ..................... 327 Start Condition Timing ...................................... 326 Transmission .................................................... 328 Multi-Master Communication, Bus Collision and Arbitration .................................................. 332 Multi-Master Mode.................................................... 332 Operation.................................................................. 307 Read/Write Bit Information (R/W Bit)................ 307, 310 Registers .................................................................. 302 Serial Clock (RC3REFO//SCL/SCK) ........................ 310 Slave Mode............................................................... 307 Address Masking Modes 5-Bit .......................................................... 308 7-Bit .......................................................... 309 Addressing ....................................................... 307 Reception ......................................................... 310 Transmission .................................................... 310 Sleep Operation........................................................ 332 Stop Condition Timing .............................................. 331 ID Locations.............................................................. 461, 486 Idle Modes .......................................................................... 72 INCF ................................................................................. 508 INCFSZ............................................................................. 509 In-Circuit Debugger........................................................... 486 In-Circuit Serial Programming (ICSP)....................... 461, 486 Indexed Literal Offset Addressing and Standard PIC18 Instructions.............................. 534 Indexed Literal Offset Mode.............................................. 534 Indirect Addressing ........................................................... 129 INFSNZ............................................................................. 509 Initialization Conditions for all Registers ............................. 90 Instruction Cycle ............................................................... 110 Clocking Scheme...................................................... 110 Flow/Pipelining ......................................................... 110 Instruction Set................................................................... 487 ADDLW..................................................................... 493 ADDWF .................................................................... 493 ADDWF (Indexed Literal Offset Mode) ..................... 535 ADDWFC.................................................................. 494 ANDLW..................................................................... 494 ANDWF .................................................................... 495 BC............................................................................. 495 BCF .......................................................................... 496 BN............................................................................. 496 BNC .......................................................................... 497 BNN .......................................................................... 497 BNOV ....................................................................... 498 BNZ .......................................................................... 498 BOV .......................................................................... 501 G GOTO ............................................................................... 508 H Hardware Multiplier ........................................................... 151 8 x 8 Multiplication Algorithms .................................. 151 Operation .................................................................. 151 Performance Comparison (table).............................. 151 High/Low-Voltage Detect .................................................. 389 Applications............................................................... 393 Associated Registers ................................................ 394 Current Consumption................................................ 391 Effects of a Reset...................................................... 394 Operation .................................................................. 390 During Sleep ..................................................... 394 Setup......................................................................... 391 Start-up Time ............................................................ 391 Typical Application .................................................... 393 HLVD. See High/Low-Voltage Detect. .............................. 389 I I/O Descriptions PIC18F2XK80 ............................................................. 20 PIC18F4XK80 ............................................................. 26 PIC18F6XK80 ............................................................. 35 I/O Ports ............................................................................ 177 Analog, Digital Ports ................................................. 180 Open-Drain Outputs.................................................. 179 Output Pin Drive........................................................ 177 Pin Capabilities ......................................................... 177 Port Slew Rate .......................................................... 180 Pull-up Configuration ................................................ 177 I2C Mode (MSSP) Acknowledge Sequence Timing................................ 331 Associated Registers ................................................ 337 Baud Rate Generator................................................ 324 2011 Microchip Technology Inc. Preliminary DS39977C-page 615 PIC18F66K80 FAMILY BRA........................................................................... 499 BSF ........................................................................... 499 BSF (Indexed Literal Offset Mode) ........................... 535 BTFSC ...................................................................... 500 BTFSS ...................................................................... 500 BTG........................................................................... 501 BZ ............................................................................. 502 CALL ......................................................................... 502 CLRF......................................................................... 503 CLRWDT................................................................... 503 COMF ....................................................................... 504 CPFSEQ ................................................................... 504 CPFSGT ................................................................... 505 CPFSLT .................................................................... 505 DAW.......................................................................... 506 DCFSNZ ................................................................... 507 DECF ........................................................................ 506 DECFSZ.................................................................... 507 Extended Instructions ............................................... 529 Considerations when Enabling ......................... 534 Syntax ............................................................... 529 Use with MPLAB IDE Tools .............................. 536 General Format......................................................... 489 GOTO ....................................................................... 508 INCF.......................................................................... 508 INCFSZ ..................................................................... 509 INFSNZ ..................................................................... 509 IORLW ...................................................................... 510 IORWF ...................................................................... 510 LFSR ......................................................................... 511 MOVF........................................................................ 511 MOVFF ..................................................................... 512 MOVLB ..................................................................... 512 MOVLW .................................................................... 513 MOVWF .................................................................... 513 MULLW ..................................................................... 514 MULWF ..................................................................... 514 NEGF ........................................................................ 515 NOP .......................................................................... 515 Opcode Field Descriptions........................................ 488 POP .......................................................................... 516 PUSH ........................................................................ 516 RCALL ...................................................................... 517 RESET ...................................................................... 517 RETFIE ..................................................................... 518 RETLW ..................................................................... 518 RETURN ................................................................... 519 RLCF......................................................................... 519 RLNCF ...................................................................... 520 RRCF ........................................................................ 520 RRNCF ..................................................................... 521 SETF ......................................................................... 521 SETF (Indexed Literal Offset Mode) ......................... 535 SLEEP ...................................................................... 522 Standard Instructions ................................................ 487 SUBFWB................................................................... 522 SUBLW ..................................................................... 523 SUBWF ..................................................................... 523 SUBWFB................................................................... 524 SWAPF ..................................................................... 524 TBLRD ...................................................................... 525 TBLWT ...................................................................... 526 TSTFSZ .................................................................... 527 XORLW ..................................................................... 527 XORWF..................................................................... 528 INTCON Register RBIF Bit .................................................................... 184 Inter-Integrated Circuit. See I2C. Internal Oscillator Block ...................................................... 62 Adjustment.................................................................. 63 INTIO Modes .............................................................. 62 INTOSC Frequency Drift............................................. 63 INTOSC Output Frequency ........................................ 63 INTPLL Modes............................................................ 62 Internal RC Oscillator Use with WDT........................................................... 476 Internal Voltage Regulator Specifications......................... 567 Internet Address ............................................................... 623 Interrupt Sources .............................................................. 461 A/D Conversion Complete ........................................ 371 Capture Complete (CCP).......................................... 264 Capture Complete (ECCP) ....................................... 275 Compare Complete (CCP)........................................ 265 Compare Complete (ECCP) ..................................... 276 ECAN Module ........................................................... 457 Interrupt-on-Change (RB7:RB4) ............................... 184 TMR0 Overflow......................................................... 213 TMR1 Overflow......................................................... 221 TMR2 to PR2 Match (PWM) ..................................... 268 TMR3 Overflow......................................................... 229 TMRx Overflow ......................................................... 238 Interrupts........................................................................... 153 Associated Registers ................................................ 175 During, Context Saving............................................. 175 INTx Pin .................................................................... 174 PORTB, Interrupt-on-Change ................................... 174 TMR0 ........................................................................ 174 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ...... 184 INTOSC. See Internal Oscillator Block. IORLW .............................................................................. 510 IORWF.............................................................................. 510 L LFSR................................................................................. 511 Listen Only Mode.............................................................. 442 Loopback Mode ................................................................ 442 M Master Clear Reset (MCLR) ............................................... 83 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ....................................................... 105 Data Memory ............................................................ 112 Program Memory ...................................................... 105 Memory Programming Requirements............................... 566 Microchip Internet Web Site.............................................. 623 Migration to PIC18F66K80 ............................................... 609 MOVF ............................................................................... 511 MOVFF ............................................................................. 512 MOVLB ............................................................................. 512 MOVLW ............................................................................ 513 MOVSF ............................................................................. 531 MOVSS............................................................................. 532 MOVWF ............................................................................ 513 MPLAB ASM30 Assembler, Linker, Librarian ................... 538 MPLAB Integrated Development Environment Software ................................................................... 537 MPLAB PM3 Device Programmer .................................... 540 MPLAB REAL ICE In-Circuit Emulator System ................ 539 MPLINK Object Linker/MPLIB Object Librarian ................ 538 DS39977C-page 616 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY MSSP ACK Pulse......................................................... 307, 310 I2C Mode. See I2C Mode. Module Overview ...................................................... 293 SPI Master/Slave Connection ................................... 297 MULLW ............................................................................. 514 MULWF ............................................................................. 514 RB2/CANTX/C1OUT/P1C/CTED1/INT2..................... 22 RB2/CANTX/CTED1/INT2.................................... 28, 37 RB3/CANRX/C2OUT/P1D/CTED2/INT3 .................... 22 RB3/CANRX/CTED2/INT3 ................................... 28, 37 RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0............... 23 RB4/AN9/CTPLS/KBI0 ......................................... 28, 37 RB5/T0CKI/T3CKI/CCP5/KBI1....................... 23, 28, 37 RB6/PGC/KBI2 ..................................................... 29, 38 RB6/PGC/TX2/CK2/KBI2 ........................................... 23 RB7/PGD/T3G/KBI3 ............................................. 29, 38 RB7/PGD/T3G/RX2/DT2/KBI3 ................................... 23 RC0/SOSCO/SCLKI ....................................... 24, 30, 39 RC1/SOSC ................................................................. 30 RC1/SOSCI .......................................................... 24, 39 RC2/T1G/CCP2.............................................. 24, 30, 39 RC3/REFO/SCL/SCK ..................................... 24, 30, 39 RC4/SDA/SDI ................................................. 24, 30, 39 RC5/SDO........................................................ 24, 30, 39 RC6/CANTX/TX1/CK1/CCP3 ............................... 24, 30 RC6/CCP3.................................................................. 39 RC7/CANRX/RX1/DT1/CCP4 .............................. 25, 31 RC7/CCP4.................................................................. 39 RD0/C1INA/PSP0................................................. 32, 40 RD1/C1INB/PSP1................................................. 32, 40 RD2/C2INA/PSP2................................................. 32, 40 RD3/C2INB/CTMUI/PSP3 .................................... 32, 40 RD4/ECCP1/P1A/PSP4 ....................................... 32, 40 RD5/P1B/PSP5 .................................................... 32, 40 RD6/P1C/PSP6 .......................................................... 41 RD6/TX2/CK2/P1C/PSP6........................................... 33 RD7/P1D/PSP7 .......................................................... 41 RD7/RX2/DT2/P1D/PSP7 .......................................... 33 RE0/AN5/RD ........................................................ 42, 33 RE1/AN6/C1OUT/WR .......................................... 42, 33 RE2/AN7/C2OUT/CS ........................................... 33, 42 RE4/CANRX ............................................................... 42 RE5/CANTX ............................................................... 42 RE6/RX2/DT2............................................................. 42 RE7/TX2/CK2 ............................................................. 42 RF0/MDMIN................................................................ 43 RF1............................................................................. 43 RF2/MDCIN1 .............................................................. 43 RF3............................................................................. 43 RF4/MDCIN2 .............................................................. 43 RF5............................................................................. 43 RF6/MDOUT............................................................... 43 RF7............................................................................. 43 RG0/RX1/DT1 ............................................................ 44 RG1/CANTX2 ............................................................. 44 RG2/T3CKI ................................................................. 44 RG3/TX1/CK1............................................................. 44 RG4/T0CKI ................................................................. 44 VDD ........................................................... 34, 45, 34, 45 VDDCORE/VCAP ............................................... 25, 34, 45 VSS ........................................................... 34, 45, 25, 45 PLL Frequency Multiplier ................................................... 61 HSPLL and ECPLL Oscillator Modes ......................... 61 Use with HF-INTOSC ................................................. 61 PLL Lock Time-out.............................................................. 86 POP .................................................................................. 516 POR. See Power-on Reset. N NEGF ................................................................................ 515 NOP .................................................................................. 515 Normal Operation Mode.................................................... 442 Notable Differences Between PIC18F66K80 and PIC18F4580 and PIC18F4680 Families - 28, 40/44-pin Devices............................... 609 Notable Differences Between PIC18F66K80 and PIC18F8680 Families - 64-pin Devices .................... 610 O On-Chip Voltage Regulator ............................................... 478 Oscillator Configuration....................................................... 53 EC ............................................................................... 53 ECIO ........................................................................... 53 HS ............................................................................... 53 Internal Oscillator Block .............................................. 62 INTIO1 ........................................................................ 53 INTIO2 ........................................................................ 53 LP................................................................................ 53 RC............................................................................... 53 RCIO ........................................................................... 53 XT ............................................................................... 53 Oscillator Selection ........................................................... 461 Oscillator Start-up Timer (OST) .................................... 65, 86 Oscillator Switching............................................................. 58 Oscillator Transitions .......................................................... 59 Oscillator, Timer1 .............................................................. 215 Oscillator, Timer3 .............................................................. 229 P P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/PWM (ECCP). ............................. 277 Packaging ......................................................................... 589 Details ....................................................................... 591 Marking ..................................................................... 589 Parallel Slave Port (PSP) .................................................. 198 Associated Registers ................................................ 200 PORTD ..................................................................... 198 Pin Functions MCLR/RE3.................................................................. 26 AVDD ........................................................................... 45 AVSS ........................................................................... 45 MCLR/RE3............................................................ 20, 35 OSC1/CLKIN/RA7........................................... 20, 26, 35 OSC2/CLKOUT/RA6....................................... 20, 26, 35 RA0/CVREF/AN0/ULPWU ............................... 21, 27, 36 RA1/AN1 ..................................................................... 21 RA1/AN1/C1INC ................................................... 27, 36 RA2/REF-/AN2 ............................................................. 21 RA2/VREF-/AN2//C2INC........................................ 36, 27 RA3/VREF+/AN3.............................................. 21, 27, 36 RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI.............. 21 RA5/AN4/HLVDIN/T1CKI/SS................................ 36, 27 RB0/AN10/C1INA/FLT0/INT0 ..................................... 22 RB0/AN10/FLT0/INT0........................................... 28, 37 RB1/AN8/C1INB/P1B/CTDIN/INT1............................. 22 RB1/AN8/CTDIN/INT1 .......................................... 28, 37 2011 Microchip Technology Inc. Preliminary DS39977C-page 617 PIC18F66K80 FAMILY PORTA Associated Registers ................................................ 183 LATA Register........................................................... 181 PORTA Register ....................................................... 181 TRISA Register ......................................................... 181 PORTB Associated Registers ................................................ 186 LATB Register........................................................... 184 PORTB Register ....................................................... 184 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ......... 184 TRISB Register ......................................................... 184 PORTC Associated Registers ................................................ 189 LATC Register .......................................................... 187 PORTC Register ....................................................... 187 RC3/REFO/SCL/SCK Pin ......................................... 310 TRISC Register ......................................................... 187 PORTD Associated Registers ................................................ 192 LATD Register .......................................................... 190 PORTD Register ....................................................... 190 TRISD Register ......................................................... 190 PORTE Associated Registers ................................................ 194 LATE Register........................................................... 193 PORTE Register ....................................................... 193 RE0/AN5/RD Pin....................................................... 198 RE1/AN6/C1OUT/WR Pin......................................... 198 RE2/AN7/C2OUT/CS Pin.......................................... 198 TRISE Register ......................................................... 193 PORTF Associated Registers ................................................ 195 LATF Register ........................................................... 195 PORTF Register ....................................................... 195 TRISF Register ......................................................... 195 PORTG Associated Registers ................................................ 197 LATG Register .......................................................... 196 PORTG Register ....................................................... 196 TRISG Register......................................................... 196 Power-Managed Modes ...................................................... 67 and EUSART Operation............................................ 343 and PWM Operation ................................................. 291 and SPI Operation .................................................... 301 Clock Transitions and Status Indicators...................... 68 Entering....................................................................... 67 Exiting Idle and Sleep Modes ..................................... 78 by Interrupt.......................................................... 78 by Reset.............................................................. 78 by WDT Time-out................................................ 78 Without a Start-up Delay..................................... 78 Idle Modes .................................................................. 72 PRI_IDLE ............................................................ 73 RC_IDLE............................................................. 74 SEC_IDLE........................................................... 73 Multiple Sleep Commands .......................................... 68 Run Modes.................................................................. 68 PRI_RUN ............................................................ 68 RC_RUN ............................................................. 69 SEC_RUN........................................................... 68 Selecting ..................................................................... 67 Sleep Mode ................................................................. 72 OSC1 and OSC2 Pin States ............................... 65 Summary (table) ......................................................... 67 Power-on Reset (POR)....................................................... 83 Oscillator Start-up Timer (OST) .................................. 86 Power-up Timer (PWRT) ............................................ 85 Time-out Sequence .................................................... 86 Power-up Delays ................................................................ 65 Power-up Timer (PWRT) .............................................. 65, 85 Prescaler, Capture............................................................ 264 Prescaler, Timer0 ............................................................. 213 Prescaler, Timer2 ............................................................. 269 PRI_IDLE Mode.................................................................. 73 PRI_RUN Mode .................................................................. 68 Program Counter .............................................................. 107 PCL, PCH and PCU Registers ................................. 107 PCLATH and PCLATU Registers ............................. 107 Program Memory Code Protection ........................................................ 484 Extended Instruction Set .......................................... 131 Hard Memory Vectors............................................... 106 Instructions ............................................................... 111 Two-Word ......................................................... 111 Interrupt Vector ......................................................... 106 Look-up Tables ......................................................... 109 Memory Maps ........................................................... 105 Hard Vectors and Configuration Words............ 106 Reset Vector ............................................................. 106 Program Verification and Code Protection ....................... 483 Associated Registers ................................................ 484 Programming, Device Instructions.................................... 487 PSP.See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP Module). PUSH................................................................................ 516 PUSH and POP Instructions............................................. 108 PUSHL.............................................................................. 532 PWM (CCP Module) Associated Registers ................................................ 270 Duty Cycle ................................................................ 269 Example Frequencies/Resolutions ........................... 269 Period ....................................................................... 268 Setup for PWM Operation......................................... 269 TMR2 to PR2 Match ................................................. 268 PWM (ECCP Module) Effects of a Reset ..................................................... 291 Operation in Power-Managed Modes ....................... 291 Operation with Fail-Safe Clock Monitor .................... 291 Pulse Steering Mode ................................................ 288 Steering Synchronization.......................................... 290 PWM Mode. See Enhanced Capture/Compare/PWM ...... 277 Q Q Clock ............................................................................. 269 R RAM. See Data Memory. RC_IDLE Mode................................................................... 74 RC_RUN Mode................................................................... 69 RCALL .............................................................................. 517 RCON Register Bit Status During Initialization ..................................... 89 Reader Response............................................................. 624 Receiver Warning ............................................................. 459 Reference Clock Output ..................................................... 63 Register File...................................................................... 114 Register File Summary ............................................. 117-126 DS39977C-page 618 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY Registers ADCON0 (A/D Control 0) .......................................... 364 ADCON1 (A/D Control 1) .......................................... 365 ADCON2 (A/D Control 2) .......................................... 366 ADRESH (A/D Result High Byte, Left Justified, ADFM = 0) ........................................................ 367 ADRESH (A/D Result High Byte, Right Justified, ADFM = 1) ........................................................ 368 ADRESL (A/D Result Low Byte, Left Justified, ADFM = 0) ........................................................ 368 ADRESL (A/D Result Low Byte, Right Justified, ADFM = 1) ........................................................ 368 ANCON0 (A/D Port Configuration 0)......................... 369 ANCON1 (A/D Port Configuration 1)......................... 369 BAUDCONx (Baud Rate Control) ............................. 342 BIE0 (Buffer Interrupt Enable 0)................................ 441 BnCON (TX/RX Buffer n Control, Receive Mode).................................................. 417 BnCON (TX/RX Buffer n Control, Transmit Mode)................................................. 418 BnDLC (TX/RX Buffer n Data Length Code in Receive Mode) .................................... 423 BnDLC (TX/RX Buffer n Data Length Code in Transmit Mode) ................................... 424 BnDm (TX/RX Buffer n Data Field Byte m in Receive Mode) .............................................. 422 BnDm (TX/RX Buffer n Data Field Byte m in Transmit Mode) ............................................. 422 BnEIDH (TX/RX Buffer n Extended Identifier, High Byte in Receive Mode) ............................. 421 BnEIDH (TX/RX Buffer n Extended Identifier, High Byte in Transmit Mode) ............................ 421 BnEIDL (TX/RX Buffer n Extended Identifier, Low Byte in Receive Mode) ...................... 421, 422 BnSIDH (TX/RX Buffer n Standard Identifier, High Byte in Receive Mode) ............................. 419 BnSIDH (TX/RX Buffer n Standard Identifier, High Byte in Transmit Mode) ............................ 419 BnSIDL (TX/RX Buffer n Standard Identifier, Low Byte in Receive Mode) .............................. 420 BRGCON1 (Baud Rate Control 1) ............................ 434 BRGCON2 (Baud Rate Control 2) ............................ 435 BRGCON3 (Baud Rate Control 3) ............................ 436 BSEL0 (Buffer Select 0)............................................ 424 CANCON (CAN Control)........................................... 398 CANSTAT (CAN Status) ........................................... 399 CCP1CON (Enhanced Capture/Compare/PWM1 Control) ............................................................. 272 CCPPRxL (CCPx Period Low Byte).......................... 261 CCPRxH (CCPx Period High Byte)........................... 261 CCPTMRS (CCP Timer Select) ........................ 260, 273 CCPxCON (CCPx Control, CCP2-CCP5) ................. 259 CIOCON (CAN I/O Control) ...................................... 437 CMSTAT (Comparator Status).................................. 379 CMxCON (Comparator Control x)............................. 378 COMSTAT (CAN Communication Status) ................ 403 CONFIG1H (Configuration 1 High) ........................... 464 CONFIG1L (Configuration 1 Low)............................. 463 CONFIG2H (Configuration 2 High) ........................... 466 CONFIG2L (Configuration 2 Low)............................. 465 CONFIG3H (Configuration 3 High) ........................... 467 CONFIG4L (Configuration 4 Low)............................. 468 CONFIG5H (Configuration 5 High) ........................... 470 CONFIG5L (Configuration 5 Low)............................. 469 CONFIG6H (Configuration 6 High) ........................... 472 CONFIG6L (Configuration 6 Low) ............................ 471 CONFIG7H (Configuration 7 High)........................... 474 CONFIG7L (Configuration 7 Low) ............................ 473 CTMUCONH (CTMU Control High) .......................... 242 CTMUCONL (CTMU Control Low) ........................... 243 CTMUICON (CTMU Current Control) ....................... 244 CVRCON (Comparator Voltage Reference Control) ........................................... 385 DEVID1 (Device ID 1)............................................... 475 DEVID2 (Device ID 2)............................................... 475 ECANCON (Enhanced CAN Control) ....................... 402 ECCP1AS (ECCP1 Auto-Shutdown Control) ........... 285 ECCP1DEL (Enhanced PWM Control)..................... 288 EECON1 (Data EEPROM Control 1)........................ 146 EECON1 (EEPROM Control 1) ................................ 137 HLVDCON (High/Low-Voltage Detect Control) ........ 389 INTCON (Interrupt Control) ...................................... 155 INTCON2 (Interrupt Control 2) ................................. 156 INTCON3 (Interrupt Control 3) ................................. 157 IOCB (Interrupt-on-Change PORTB Control) ........... 174 IPR1 (Peripheral Interrupt Priority 1) ........................ 168 IPR2 (Peripheral Interrupt Priority 2) ........................ 169 IPR3 (Peripheral Interrupt Priority 3) ........................ 170 IPR4 (Peripheral Interrupt Priority 4) ........................ 171 IPR5 (Peripheral Interrupt Priority 5) ................ 172, 440 MDCARH (Modulation High Carrier Control)............ 209 MDCARL (Modulation Low Carrier Control) ............. 210 MDCON (Modulation Control Register) .................... 207 MDSRC (Modulation Source Control) ...................... 208 MSEL0 (Mask Select 0)............................................ 430 MSEL1 (Mask Select 1)............................................ 431 MSEL2 (Mask Select 2)............................................ 432 MSEL3 (Mask Select 3)............................................ 433 ODCON (Peripheral Open-Drain Control) ................ 179 OSCCON (Oscillator Control)..................................... 55 OSCCON2 (Oscillator Control 2)........................ 56, 231 OSCTUNE (Oscillator Tuning).................................... 57 PADCFG1 (Pad Configuration) ................................ 178 PIE1 (Peripheral Interrupt Enable 1) ........................ 163 PIE2 (Peripheral Interrupt Enable 2) ........................ 164 PIE3 (Peripheral Interrupt Enable 3) ........................ 165 PIE4 (Peripheral Interrupt Enable 4) ........................ 166 PIE5 (Peripheral Interrupt Enable 5) ................ 167, 439 PIR1 (Peripheral Interrupt Request (Flag) 1)............ 158 PIR2 (Peripheral Interrupt Request (Flag) 2)............ 159 PIR3 (Peripheral Interrupt Request (Flag) 3)............ 160 PIR4 (Peripheral Interrupt Request (Flag) 4)............ 161 PIR5 (Peripheral Interrupt Request (Flag) 5)...................................... 162, 438 PMD0 (Peripheral Module Disable 0) ......................... 77 PMD1 (Peripheral Module Disable 1) ......................... 76 PMD2 (Peripheral Module Disable 2) ......................... 75 PSPCON (Parallel Slave Port Control) ..................... 199 PSTR1CON (Pulse Steering Control)....................... 289 RCON (Reset Control)........................................ 82, 173 RCSTAx (Receive Status and Control) .................... 341 REFOCON (Reference Oscillator Control) ................. 64 RXB0CON (Receive Buffer 0 Control)...................... 410 RXB1CON (Receive Buffer 1 Control)...................... 412 RXBnDLC (Receive Buffer n Data Length Code).................................................... 415 RXBnDm (Receive Buffer n Data Field Byte m) ....... 415 RXBnEIDH (Receive Buffer n Extended Identifier, High Byte) ......................................... 414 2011 Microchip Technology Inc. Preliminary DS39977C-page 619 PIC18F66K80 FAMILY RXBnEIDL (Receive Buffer n Extended Identifier, Low Byte) .......................................... 414 RXBnSIDH (Receive Buffer n Standard Identifier, High Byte) ......................................... 413 RXBnSIDL (Receive Buffer n Standard Identifier, Low Byte) .......................................... 414 RXERRCNT (Receive Error Count) .......................... 416 RXFBCONn (Receive Filter Buffer Control n) ........... 429 RXFCONn (Receive Filter Control n) ........................ 428 RXFnEIDH (Receive Acceptance Filter n Extended Identifier, High Byte) ......................... 426 RXFnEIDL (Receive Acceptance Filter n Extended Identifier, Low Byte) .......................... 426 RXFnSIDH (Receive Acceptance Filter n Standard Identifier Filter, High Byte)................. 425 RXFnSIDL (Receive Acceptance Filter n Standard Identifier Filter, Low Byte).................. 425 RXMnEIDH (Receive Acceptance Mask n Extended Identifier Mask, High Byte)................ 427 RXMnEIDL (Receive Acceptance Mask n Extended Identifier Mask, Low Byte) ................ 427 RXMnSIDH (Receive Acceptance Mask n Standard Identifier Mask, High Byte) ................ 426 RXMnSIDL (Receive Acceptance Mask n Standard Identifier Mask, Low Byte) ................. 427 SDFLC (Standard Data Bytes Filter Length Count) ................................................... 428 SLRCON (Slew Rate Control)................................... 180 SSPCON1 (MSSP Control 1, I2C Mode) .................. 304 SSPCON1 (MSSP Control 1, SPI Mode) .................. 295 SSPCON2 (MSSP Control 2, I2C Master Mode) ...... 305 SSPCON2 (MSSP Control 2, I2C Slave Mode) ........ 306 SSPMSK (I2C Slave Address Mask)......................... 306 SSPSTAT (MSSP Status, I2C Mode)........................ 303 SSPSTAT (MSSP Status, SPI Mode) ....................... 294 STATUS .................................................................... 127 STKPTR (Stack Pointer) ........................................... 108 T0CON (Timer0 Control)........................................... 211 T1CON (Timer1 Control)........................................... 215 T1GCON (Timer1 Gate Control) ............................... 217 T2CON (Timer2 Control)........................................... 227 T3CON (Timer3 Control)........................................... 229 T3GCON (Timer3 Gate Control) ............................... 230 T4CON (Timer4 Control)........................................... 239 TXBIE (Transmit Buffers Interrupt Enable) ............... 441 TXBnCON (Transmit Buffer n Control) ..................... 404 TXBnDLC (Transmit Buffer n Data Length Code)............................................ 407 TXBnDm (Transmit Buffer n Data Field Byte m) ....... 406 TXBnEIDH (Transmit Buffer n Extended Identifier, High Byte) ......................................... 405 TXBnEIDL (Transmit Buffer n Extended Identifier, Low Byte) .......................................... 406 TXBnSIDH (Transmit Buffer n Standard Identifier, High Byte) ......................................... 405 TXBnSIDL (Transmit Buffer n Standard Identifier, Low Byte) .......................................... 405 TXERRCNT (Transmit Error Count).......................... 407 TXSTAx (Transmit Status and Control) .................... 340 WDTCON (Watchdog Timer Control)........................ 477 WPUB (Weak Pull-up PORTB Enable) ..................... 178 RESET.............................................................................. 517 Resets......................................................................... 81, 461 Brown-out Reset (BOR)............................................ 461 Oscillator Start-up Timer (OST) ................................ 461 Power-on Reset (POR)............................................. 461 Power-up Timer (PWRT) .......................................... 461 RETFIE ............................................................................. 518 RETLW ............................................................................. 518 RETURN........................................................................... 519 Return Address Stack....................................................... 107 Return Stack Pointer (STKPTR) ....................................... 108 Revision History................................................................ 609 RLCF ................................................................................ 519 RLNCF.............................................................................. 520 RRCF................................................................................ 520 RRNCF ............................................................................. 521 S SCK .................................................................................. 293 SDI.................................................................................... 293 SDO .................................................................................. 293 SEC_IDLE Mode ................................................................ 73 SEC_RUN Mode................................................................. 68 Selective Peripheral Module Control .................................. 74 Serial Clock, SCK ............................................................. 293 Serial Data In (SDI)........................................................... 293 Serial Data Out (SDO) ...................................................... 293 Serial Peripheral Interface. See SPI Mode. SETF................................................................................. 521 Shoot-Through Current..................................................... 287 Slave Select (SS).............................................................. 293 SLEEP .............................................................................. 522 Sleep Mode......................................................................... 72 Software Simulator (MPLAB SIM) .................................... 539 Special Event Trigger. See Compare (CCP Module). Special Event Trigger. See Compare (ECCP Mode). SPI Mode (MSSP) ............................................................ 293 Associated Registers ................................................ 301 Bus Mode Compatibility ............................................ 301 Effects of a Reset ..................................................... 301 Enabling SPI I/O ....................................................... 297 Master Mode............................................................. 298 Master/Slave Connection.......................................... 297 Operation .................................................................. 296 Operation in Power-Managed Modes ....................... 301 Serial Clock............................................................... 293 Serial Data In ............................................................ 293 Serial Data Out ......................................................... 293 Slave Mode............................................................... 299 Slave Select.............................................................. 293 Slave Select Synchronization ................................... 299 SPI Clock .................................................................. 298 SSPBUF Register ..................................................... 298 SSPSR Register ....................................................... 298 Typical Connection ................................................... 297 .......................................................................................... 293 SSPOV ............................................................................. 328 SSPOV Status Flag .......................................................... 328 SSPSTAT Register R/W Bit ............................................................. 307, 310 Stack Full/Underflow Resets............................................. 109 DS39977C-page 620 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY SUBFSR ........................................................................... 533 SUBFWB........................................................................... 522 SUBLW ............................................................................. 523 SUBULNK ......................................................................... 533 SUBWF ............................................................................. 523 SUBWFB........................................................................... 524 SWAPF ............................................................................. 524 Timer4 .............................................................................. 239 Associated Registers................................................ 240 Interrupt .................................................................... 240 Operation.................................................................. 239 Output....................................................................... 240 Postscaler. See Postscaler, Timer4. PR4 Register ............................................................ 239 Prescaler. See Prescaler, Timer4. TMR4 Register ......................................................... 239 Timing Diagrams A/D Conversion ........................................................ 588 Asynchronous Reception.......................................... 353 Asynchronous Transmission .................................... 350 Asynchronous Transmission (Back-to-Back)............ 350 Automatic Baud Rate Calculation............................. 348 Auto-Wake-up Bit (WUE) During Normal Operation.......................................................... 355 Auto-Wake-up Bit (WUE) During Sleep.................... 355 Baud Rate Generator with Clock Arbitration............. 325 BRG Overflow Sequence ......................................... 348 BRG Reset Due to SDA Arbitration During Start Condition.................................................. 334 Brown-out Reset (BOR)............................................ 574 Bus Collision During a Repeated Start Condition (Case 1)............................................ 335 Bus Collision During a Repeated Start Condition (Case 2)............................................ 335 Bus Collision During a Start Condition (SCL = 0) .......................................................... 334 Bus Collision During a Stop Condition (Case 1)....... 336 Bus Collision During a Stop Condition (Case 2)....... 336 Bus Collision During Start Condition (SDA Only) ....................................................... 333 Bus Collision for Transmit and Acknowledge ........... 332 Capture/Compare/PWM (ECCP1, ECCP2).............. 577 CLKO and I/O ........................................................... 572 Clock/Instruction Cycle ............................................. 110 DSM Carrier High Synchronization (MDCHSYNC = 1, MDCLSYNC = 0) .............................................. 204 DSM Carrier Low Synchronization (MDCHSYNC = 0, MDCLSYNC = 1) ................ 205 DSM Full Synchronization (MDCHSYNC = 1, MDCLSYNC = 1) ................ 205 DSM No Synchronization (MDCHSYNC = 0, MDCLSYNC = 0) ................ 204 DSM On-Off Keying (OOK) Synchronization............ 204 Enhanced PWM Output (Active-High) ...................... 278 Enhanced PWM Output (Active-Low) ....................... 279 EUSART Synchronous Transmission (Master/Slave) .................................................. 586 EUSART/AUSART Synchronous Receive (Master/ Slave) ............................................................... 586 Example SPI Master Mode (CKE = 0) ...................... 578 Example SPI Master Mode (CKE = 1) ...................... 579 Example SPI Slave Mode (CKE = 0) ........................ 580 Example SPI Slave Mode (CKE = 1) ........................ 581 External Clock .......................................................... 570 Fail-Safe Clock Monitor (FSCM)............................... 482 First Start Bit Timing ................................................. 326 Full-Bridge PWM Output........................................... 282 T Table Pointer Operations (table) ....................................... 138 Table Reads/Table Writes ................................................ 109 TBLRD .............................................................................. 525 TBLWT .............................................................................. 526 Time-out in Various Situations (table) ................................. 86 Timer0 ............................................................................... 211 Associated Registers ................................................ 213 Operation .................................................................. 212 Overflow Interrupt ..................................................... 213 Prescaler................................................................... 213 Switching Assignment....................................... 213 Prescaler Assignment (PSA Bit) ............................... 213 Prescaler Select (T0PS2:T0PS0 Bits) ...................... 213 Reads and Writes in 16-Bit Mode ............................. 212 Source Edge Select (T0SE Bit)................................. 212 Source Select (T0CS Bit).......................................... 212 Timer1 ............................................................................... 215 16-Bit Read/Write Mode............................................ 220 Associated Registers ................................................ 226 Clock Source Selection............................................. 218 Gate .......................................................................... 222 Interrupt..................................................................... 221 Operation .................................................................. 218 Oscillator ................................................................... 215 Oscillator, as Secondary Clock ................................... 58 Resetting, Using the ECCP Special Event Trigger .................................................... 222 SOSC Oscillator........................................................ 220 Layout Considerations ...................................... 221 Use as a Clock Source ..................................... 221 TMR1H Register ....................................................... 215 TMR1L Register........................................................ 215 Timer2 ............................................................................... 227 Associated Registers ................................................ 228 Interrupt..................................................................... 228 Operation .................................................................. 227 Output ....................................................................... 228 PR2 Register............................................................. 268 TMR2 to PR2 Match Interrupt ................................... 268 Timer3 ............................................................................... 229 16-Bit Read/Write Mode............................................ 233 Associated Registers ................................................ 238 Gates ........................................................................ 234 Operation .................................................................. 232 Oscillator ................................................................... 229 Overflow Interrupt ............................................. 229, 238 SOSC Oscillator Use as the Timer3 Clock Source ...................... 233 Special Event Trigger (ECCP) .................................. 238 TMR3H Register ....................................................... 229 TMR3L Register........................................................ 229 2011 Microchip Technology Inc. Preliminary DS39977C-page 621 PIC18F66K80 FAMILY Half-Bridge PWM Output .................................. 280, 287 High-Voltage Detect Operation (VDIRMAG = 1)................................................. 393 HLVD Characteristics................................................ 575 I2C Acknowledge Sequence ..................................... 331 I2C Bus Data ............................................................. 583 I2C Bus Start/Stop Bits.............................................. 582 I2C Master Mode (7 or 10-Bit Transmission) ............ 329 I2C Master Mode (7-Bit Reception) ........................... 330 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = 01001) .............................................. 314 I2C Slave Mode (10-Bit Reception, SEN = 0) ........... 315 I2C Slave Mode (10-Bit Reception, SEN = 1) ........... 320 I2C Slave Mode (10-Bit Transmission)...................... 316 I2C Slave Mode (7-bit Reception, SEN = 0, ADMSK = 01011) .............................................. 312 I2C Slave Mode (7-Bit Reception, SEN = 0) ............. 311 I2C Slave Mode (7-Bit Reception, SEN = 1) ............. 319 I2C Slave Mode (7-Bit Transmission)........................ 313 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Addressing Mode)......... 321 I2C Stop Condition Receive or Transmit Mode ......... 331 Low-Voltage Detect Operation (VDIRMAG = 0)........ 392 MSSP Clock Synchronization ................................... 318 MSSP I2C Bus Data .................................................. 584 MSSP I2C Bus Start/Stop Bits .................................. 584 Parallel Slave Port (PSP) Read ................................ 200 Parallel Slave Port (PSP) Write ................................ 199 PWM Auto-Shutdown with Auto-Restart Enabled............................................................. 286 PWM Auto-Shutdown with Firmware Restart............ 286 PWM Direction Change ............................................ 283 PWM Direction Change at Near 100% Duty Cycle......................................................... 284 PWM Output ............................................................. 268 Repeated Start Condition.......................................... 327 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ...... 573 Send Break Character Sequence ............................. 356 Slave Synchronization .............................................. 299 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT)..................................................... 87 SPI Mode (Master Mode) .......................................... 298 SPI Mode (Slave Mode, CKE = 0) ............................ 300 SPI Mode (Slave Mode, CKE = 1) ............................ 300 Steering Event at Beginning of Instruction (STRSYNC = 1) ................................................ 290 Steering Event at End of Instruction (STRSYNC = 0) ................................................ 290 Synchronous Reception (Master Mode, SREN) ....... 359 Synchronous Transmission....................................... 357 Synchronous Transmission (Through TXEN) ........... 358 Time-out Sequence on POR w/ PLL Enabled (MCLR Tied to VDD).............................. 88 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ........................ 87 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ........................ 87 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) ............... 86 Timer0 and Timer1 External Clock ........................... 576 Timer1 Gate Count Enable Mode ............................. 223 Timer1 Gate Single Pulse Mode............................... 225 Timer1 Gate Single Pulse/Toggle Combined Mode ............................................... 226 Timer1 Gate Toggle Mode........................................ 224 Timer3 Gate Count Enable Mode ............................. 234 Timer3 Gate Single Pulse Mode............................... 236 Timer3 Gate Single Pulse/Toggle Combined Mode ............................................... 237 Timer3 Gate Toggle Mode........................................ 235 Transition for Entry to Idle Mode................................. 73 Transition for Entry to SEC_RUN Mode ..................... 69 Transition for Entry to Sleep Mode ............................. 72 Transition for Two-Speed Start-up (INTOSC to HSPLL) ......................................... 480 Transition for Wake from Idle to Run Mode ................ 73 Transition for Wake from Sleep (HSPLL) ................... 72 Transition from RC_RUN Mode to PRI_RUN Mode.................................................. 71 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) ................................... 69 Transition to RC_RUN Mode ...................................... 71 Timing Diagrams and Specifications Capture/Compare/PWM Requirements .................... 577 CLKO and I/O Requirements............................ 572, 573 EUSART/AUSART Synchronous Receive Requirements ................................................... 586 EUSART/AUSART Synchronous Transmission Requirements ................................................... 586 Example SPI Mode Requirements (Master Mode, CKE = 0)................................... 578 Example SPI Mode Requirements (Master Mode, CKE = 1)................................... 579 Example SPI Mode Requirements (Slave Mode, CKE = 0)..................................... 580 Example SPI Slave Mode Requirements (CKE = 1).......................................................... 581 External Clock Requirements ................................... 570 HLVD Characteristics ............................................... 575 I2C Bus Data Requirements (Slave Mode) ............... 583 I2C Bus Start/Stop Bits Requirements (Slave Mode) .................................................... 582 Internal RC Accuracy (INTOSC)............................... 571 MSSP I2C Bus Data Requirements .......................... 585 MSSP I2C Bus Start/Stop Bits Requirements........... 584 PLL Clock ................................................................. 571 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements......................................... 574 Timer0 and Timer1 External Clock Requirements ................................................... 576 Top-of-Stack Access......................................................... 107 TSTFSZ ............................................................................ 527 Two-Speed Start-up.................................................. 461, 480 IESO (CONFIG1H, Internal/External Oscillator Switchover Bit................................... 464 Two-Word Instructions Example Cases......................................................... 111 TXSTAx Register BRGH Bit .................................................................. 343 DS39977C-page 622 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY U Ultra Low-Power Mode Regulators Enable Mode..................................................... 478 Operation in Sleep ............................................ 479 Ultra Low-Power Wake-up Exit Delay.................................................................... 80 Overview ..................................................................... 79 W Watchdog Timer (WDT)............................................ 461, 476 Associated Registers................................................ 477 Control Register........................................................ 477 During Oscillator Failure ........................................... 481 Programming Considerations ................................... 476 WCOL ....................................................... 326, 327, 328, 331 WCOL Status Flag.................................... 326, 327, 328, 331 WWW Address ................................................................. 623 WWW, On-Line Support ..................................................... 11 V Voltage Reference Specifications ..................................... 567 X XORLW ............................................................................ 527 XORWF ............................................................................ 528 2011 Microchip Technology Inc. Preliminary DS39977C-page 623 PIC18F66K80 FAMILY NOTES: DS39977C-page 624 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2011 Microchip Technology Inc. Preliminary DS39977C-page 625 PIC18F66K80 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39977C FAX: (______) _________ - _________ Device: PIC18F66K80 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39977C-page 626 Preliminary 2011 Microchip Technology Inc. PIC18F66K80 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, such as pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) Device(1,2) PIC18F25K80, PIC18F26K80, PIC18F45K80, PIC18F46K80, PIC18F65K80, PIC18F66K80 VDD range 1.8V to 5V PIC18LF25K80, PIC18LF26K80, PIC18LF45K80, PIC18LF46K80, PIC18F65K80, PIC18F66K80 VDD range 1.8V to 3.6V Temperature Range I E PDIP QFN SOIC SPDIP SSOP TQFP a) = -40C to +85C = -40C to +125C = = = = = = (Industrial) (Extended) F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel, TQFP packages only. PIC18F66K80-I/MR 301 = Industrial temp., QFN package, Extended VDD limits, QTP pattern #301. PIC18F66K80-I/PT = Industrial temp., TQFP package, Extended VDD limits. Package Plastic Dual In-Line Plastic Quad Flat, No Lead Package Plastic Small Outline Skinny Plastic Dual In-Line Plastic Shrink Small Outline Plastic Thin Quad Flatpack Note 1: 2: Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) 2011 Microchip Technology Inc. Preliminary DS39977C-page 627 Worldwide Sales and Service AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 08/04/10 DS39977C-page 628 Preliminary 2011 Microchip Technology Inc. |
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